Lexical elements Declarations

Reserved words Type declaration

Subtype declaration
Constant declaration
Signal declaration
Variable declaration

page 1 page 3
 Type declaration Reserved words

architecture a of e is package p is

abs range
begin access record
end p; if
after register
end a; impure
alias reject
in
all rem
inertial
and report
inout
architecture return
is
array rol
label
assert ror
library
attribute select
in the STD.STANDARD package: linkage
begin severity
type boolean is (false, true); literal
block shared
type bit is ('0', '1'); loop
body signal
type character is (NUL, SOH, <...> '}', '~', DEL); map
buffer sla
type string is array(positive range <>) of character; mod
bus sll
type bit_vector is array(natural range <>) of bit; nand
case sra
new
component srl
next
configuration subtype
nor
constant then
not
disconnect to
null
in the IEEE.STD_LOGIC_1164 package: downto transport
of
type std_uLogic is ('U', 'X', '0', '1', 'Z', else type
on
'W', 'L', 'H', '-'); elsif unaffected
open
end units
or
type std_uLogic_vector is entity until
others
array(natural range <>) of std_uLogic; exit use
out
file variable
package
for wait
port
function when
procedure
generate while
process
generic with
in the IEEE.NUMERIC_STD package: pure
group xnor
type unsigned is array(natural range <>) of std_Logic; guarded xor
type signed is array(natural range <>) of std_logic;

page 4 page 2
 Subtype declaration Signal declaration

architecture a of e is package p is architecture a of e is

begin begin
end p;
end a; end a;

in the STD.STANDARD package: signal s1, s2, s3: std_ulogic;

subtype natural is integer range 0 to integer'high; signal sig1: std_ulogic;
subtype positive is integer range 1 to integer'high; signal sig2: std_ulogic;
signal sig3: std_ulogic;

in the IEEE.STD_LOGIC_1164 package:

subtype std_logic is resolved std_uLogic;
signal logic_out: std_uLogic;
subtype X01 is resolved std_uLogic range 'X' to '1'; signal open_drain_out: std_logic;
subtype X01Z is resolved std_uLogic range 'X' to 'Z'; signal tri_state_out: std_logic;
subtype UX01 is resolved std_uLogic range 'U' to '1';
subtype UX01Z is resolved std_uLogic range 'U' to 'Z';

signal counter: unsigned(nb_bits-1 downto 0);

subtype byte is std_uLogic_vector(7 downto 0); signal double: unsigned(2*nb_bits-1 downto 0);
subtype word is std_uLogic_vector(15 downto 0); signal sine: signed(nb_bits-1 downto 0);
subtype long_word is std_uLogic_vector(31 downto 0);

subtype BCD_digit is unsigned(3 downto 0); signal clock_internal: std_ulogic := '1';

subtype my_counter_type is unsigned(9 downto 0);
subtype sine_wave_type is signed(15 downto 0);

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 Variable declaration Constant declaration

p: process (s_list) architecture a of e is package p is

begin begin
end p;
end process p; end a;

constant bit_nb: positive := 4;

constant min_value: positive := 0;
constant max_value: positive := 2**bit_nb - 1;

variable v1, v2, v3: std_ulogic;

variable var1: std_ulogic;
variable var2: std_ulogic;
variable var3: std_ulogic; constant bit_nb: positive := 4;
constant patt1: unsigned(bit_nb-1 downto 0) := "0101";
constant patt2: unsigned(bit_nb-1 downto 0) := "1010";

constant address_nb: positive := 4;

constant data_register_address : positive := 0;
constant control_register_address : positive := 1;
constant interrupt_register_address: positive := 2;
constant status_register_address : positive := 3;
variable counter: unsigned(nb_bits-1 downto 0);
variable double: unsigned(2*nb_bits-1 downto 0);
variable sine: signed(nb_bits-1 downto 0);

constant clock_period: time := 5 ns;

constant access_time: time := 2 us;
constant duty_cycle: time := 33.3 ms;
constant reaction_time: time := 4 sec;
constant teaching_period: time := 45 min;

page 8 page 6
 Process statement

Concurrent architecture a of e is

begin

statements end a;

mux: process(sel, x0, x1)

begin
if sel = '0' then
y <= x0;
elsif sel = '1' then
Signal assignment y <= x1;
else
Process statement y <= 'X';
end if;
When statement end process mux;

With statement

count: process(reset, clock)

begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clock) then
counter <= counter + 1;
end if;
end process count;

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 When statement Signal assignment

architecture a of e is architecture a of e is

begin begin

end a; end a;

y1 <= a;
y2 <= a and b;
y3 <= to_integer(a);

y <= "00000011";
y <= x0 when sel = '0' else y <= "0000" & "0011";
x1 when sel = '1' else y <= ('0', '0','0', '0','0', '0', '1', '1');
'X'; y <= (7 downto 2 => '0', 1|0 => '1');
y <= (7 downto 2 => '0', others => '1');

y1 <= a;
y2 <= a after 2 ns;
y3 <= inertial a after 1 ns;
y4 <= transport a after 4 ns;
y5 <= reject 1 ns inertial a after 5 ns;

y <= x0 after 2 ns when sel = '0' else

x1 after 3 ns when sel = '1';
y <= '0',
y <= a and b after 5 ns; '1' after 2 ns,
'0' after 4 ns,
'X' after 10 ns,
'1' after 15 ns,
'-' after 23 ns;

page 12 page 10
 With statement

architecture a of e is

begin
Sequential
end a; statements

mux: with sel select

y <= x0 when "00",
x1 when "01",
x2 when "10", Variable assignment
x3 when "11",
'X' when others; If statement
Case statement
Loop statement

decoder: with binary_code select

y <= transport "0001" after 2 ns when "00",
"0010" after 5 ns when "01",
"0100" after 3 ns when "10",
"1000" after 4 ns when "11",
"XXXX" when others;

page 13 page 15
 Variable assignment

p: process (s_list)

begin

end process p;

y1 := a;

y2 := a and b;

y3 := to_integer(a);

page 16 page 14
 If statement Loop statement

p: process (s_list) p: process (s_list)

begin begin

end process p; end process p;

if gate = '1' then

q <= d;
if sel = '0' then
end if; for xIndex in 1 to xSize loop
y1 <= x0;
y2 <= x1; for yIndex in 1 to ySize loop
y3 <= '0'; if xIndex = yIndex then
else y(xIndex, yIndex) <= '1';
y1 <= x1; else
if sel = '0' then y2 <= x0; y(xIndex, yIndex) <= '0';
y <= x0; y3 <= '1'; end if;
else end if; end loop;
y <= x1; end loop;
end if;

if sel = 0 then
y <= x0;
elsif sel = 1 then multipl: for indexB in 0 to nBits-1 loop
y <= x1; partialProd: for indexA in nBits-1 downto 0 loop
elsif sel = 2 then partProd(indexA) <= a(indexA) and b(indexB);
y <= x2; end loop partialProd;
else if (a = '0') and (b = '0') then cumSum(indexB+1) <= cumSum(indexB) + partProd;
y <= x3; y <= '1'; end loop multipl;
end if; else
y <= '0';
end if;

page 17 page 19
 Case statement

p: process (s_list)

begin

end process p;

case sel is
when "00" => y <= x0;
case opCode is
when "01" => y <= x1;
when add => y1 <= x0;
when "10" => y <= x2;
y2 <= x1;
when "11" => y <= x3;
when sub => y1 <= x1;
when others => null;
y2 <= x0;
end case;
when others => null;
end case;

case value is
when 1 => nBits <= 1;
when 2|3 => nBits <= 2;
when 4 to 7 => nBits <= 3;
when 8 to 15 => nBits <= 3;
when others => nBits <= 0;
end case;

case to_integer(sel) is
when 0 => y <= x0 after 1 ns;
when 1 => y <= x1 after 1 ns;
when 2 => y <= x2 after 1 ns;
when 3 => y <= x3 after 1 ns;
when others => y <= 'X';
end case;

page 20 page 18
 Arithmetic operators
operator description

Operators +
-
addition
substraction
* multiplication
/ division
** power
abs absolute value
mod modulo
rem reminder of the division
sla arithmetic shift left
Logic operators sra arithmetic shift right
Arithmetic operators
Comparisons
Concatenation

maxUnsigned <= 2**nBits - 1;

maxSigned <= 2**(nBits-1) - 1;

page 21 page 23
 Comparisons Logic operators
operator description operator description
= equal to not inversion
/= not equal to and logical AND
< smaller than or logical OR
> greater than xor exclusive-OR
<= smaller than or equal to nand NAND-function
>= greater than or equal to nor NOR-function
xnor exclusive-NOR
sll logical shift left
srl logical shift right
rol rotate left
ror rotate right

if counter > 0 then

counter <= counter -1; y <= a and b;
end if;

if (a = '1') and (b = '1') then

y <= '1';
else
y <= '0';
end if;
if counter /= 0 then
counterRunning <= '1';
else if (a and b) = '1' then
counterRunning <= '0'; y <= '1';
end if; else
y <= '0';
end if;

count <= count sll 3;

page 24 page 22
 Concatenation
operator description
& concatenation
Attributes

address <= "1111" & "1100";

Type related attributes

constant CLR: std_logic_vector(1 to 4) := "0000";
Array related attributes
constant ADD: std_logic_vector(1 to 4) := "0001";
constant CMP: std_logic_vector(1 to 4) := "0010";
constant BRZ: std_logic_vector(1 to 4) := "0011";

constant R0 : std_logic_vector(1 to 2) := "00";

constant DC : std_logic_vector(1 to 2) := "--";

constant reg : std_logic := '0';

constant imm : std_logic := '1';

type ROMArrayType is array(1 to 255)

of std_logic_vector(1 to 9);

constant ROMArray: ROMArrayType := (

0 => ( CLR & DC & R0 & reg ),
1 => ( ADD &"01"& R0 & imm ),
2 => ( CMP &"11"& R0 & imm ),
3 => ( BRZ & "0001" & '-' ),
4 to romArray'length-1 => (others => '0') );

page 25 page 27
 Type related attributes
attribute result

T’base the base type of T

T’left the left bound of T
T’right the right bound of T
T’high the upper bound of T
T’low the lower bound of T
T’pos(X) the position number of X in T
T’val(N) the value of position number N in T
T’succ(X) the successor of X in T
T’pred(X) the predecessor of X in T
T’leftOf(X) the element left of X in T
T’rightOf(X) the element right of X in T

signal counterInt: unsigned;

signal count1: unsigned(counter'range);
signal count2: unsigned(counter'length-1 downto 0);

flip: process(count1)
begin
for index in count1'low to count1'high loop
count2(index) <= count1(count1'length-index);
end loop;
end process flip;

page 28 page 26
 Array related attributes Wait statement
attribute result

A’left the left bound of A p: process

A’right the right bound of A begin

A’high the upper bound of A

end process p;
A’low the lower bound of A
A’range the range of A
A’reverse_range the range of A in reverse order test: process
begin
A’length the size of the range of A test: process
testMode <= '0';
begin
dataByte <= "11001111";
a <= '0';
startSend <= '1';
b <= '0';
wait for 4*clockPeriod;
wait for simulStep;
startSend <= '0';
error <= y xor '0';
wait for 8*clockPeriod;
testMode <= '1';
a <= '1';
type stateType is (reset, wait, go); dataByte <= "11111100";
b <= '1';
signal state: stateType; startSend <= '1';
wait for simulStep;
wait for 4*clockPeriod;
error <= y xor '1';
… startSend <= '0';
wait;
end process test;
evalNextState: process(reset, clock) end process test;
begin
if reset = '1' then
state <= stateType'left;
elsif rising_edge(clock) then test: process
… begin
end if; playVectors: for index in stimuli’range
end process evalNextState; dataByte <= stimuli(index);
wait for clockPeriod;
assert codedWord = expected(index);
wait for clockPeriod;
end loop playVectors;
wait;
end process test;

page 29 page 31
 Assert statement

p: process

begin
Simulation
end process p; elements

assert output = '1';

assert output = '1'

report "output was '0'!"; Wait statement
Assert statement
assert output = '1'
report "output was '0'!"
severity error;

in the STD.STANDARD package:

type severity_level is (note,
warning,
error,
failure);

page 32 page 30
 Index

Lexical elements 1
Declarations 3
Concurrent statements 9
Sequential statements 15
Operators 21
Attributes 27
Simulation elements 29

Arithmetic operators
Array related attributes
Assert statement
Case statement
23
29
31
18
VHDL syntax
Comparisons
Concatenation
Constant declaration
24
25
6
shortform
If statement 17
Logic operators 22
Loop statement 19
Process statement 11
Reserved words 2
Type declaration 4
Type related attributes 28
Signal assignment 10
Signal declaration 7
Subtype declaration 5
Variable assignment 16
Variable declaration 8
Wait statement 30
When statement 12
With statement 13

Francois Corthay, HEVs, 4/25/02