1. Defect ---- The physical floss in a device. It is actually the physical problem.

Any physical imperfections

on the chip that is not intended to exist.

Fault --- It is actually the malfunctioning of the device due to the defects. It is the logical problem and
hence the device won't perform the actual way it is designed to be and giving an incorrect logical value
at the output. It is the logical and physical representation of a defect.

Hence fault and defect are not the same.

With a fault, the output of any basic gate can either be fault free output or a faulty output.

Eg: If any of the inputs in a 2 input AND gate is stuck at 0 which is basically called as Stuck at Zero Fault,
then there will be cases where the logical output will be 0 or 1 which will be either a required output
and termed as Fault free output or a not required output and termed as Faulty output.

Error --- The unexpected output values or erroneous output values obtained due to the faults are called
as error.

So in short we can say Defect in the manufacturing process of an IC leads to Faults and the faults leads
to the errors. So all are different but are interconnected one way or the other.

2. Compression ratio === total number of internal chains between the compressor and decompressor /
total number of external channels(no of pins to the decompressor)

3. a) Input files:

o We need the design netlist from the sythesis team. Will be in the form of basic verilog codes. This is
the sythesized gate level netlist.

o We need the standard library files including all the details of the design netlist files obtained from the
synthesis team itself.

o Do files or command files or the script files to run the input files. This DFT engineer has to create. This
deals with the clock, reset, onstate and offstate value, the scan chain length, the violations, fixing
violations, etc.

o tcd (Tessent Core Description)files. It is an optional one. During partial scan, few are scanned and few
are not. The number of scanned flops details will be there in this file and also the scanned chains. So
when we try to do the rescan it gives error. If there are no pre scanned flops, tcd is not required.

b) Outpul files generated after scan:

o Scan inserted netlist --- scan replaced flops details after stitching.
o ATPG setup files are generated. Two files --- do file and test proc file (TPF). The do file will have the
information about the clock, reset and the scan chain. The test proc will have the information on the
shift and the capture phase also on how many clock pulses are required for both shift and capture
phase. Frequency of the clock and all.

o Scan cells reports and scan chains reports. Scan chain report will have the details on how many flops
are there in a chain and how many chains are there. Scan cell report will have the in-depth detail on the
flops or cells in each and every chain with the flop names and everything. And the connectivity.

O Scan definition files. Similar to Scan cell file and scan chain file. This final file is to be handed over to
the PD domain for their work.

4. Controllability --- The ability to place nets, nodes, gates, or any sequential elements to a known state.
That is we are able to put a particular 0 or 1 at any node or gate or anywhere in the device. This comes
at the input side. It states that if we are able to control the values at all the nets and nodes in a design
from the top level and then it’s controllable.

o Observability ---- After having the controllability we have to observe the output response as well.
Comes at the output side. Each and every nets and nodes are observed from the top level. If controllable
then definitely observable as well.

5. This is the technology to identify the manufacturing defects. It is the design to test the faults in a
manufacturing chip. It checks the errors or faults in a chip before delivering into the industry. A testing
process which reduces the total cost and simplifies the debug process for the modern circuits.

Scan Insertion is the process of replacing the existing sequential design with an additional scan logic with
DFT Scan Input and Scan Enable pins. The logic can be of any form out of three – muxed, clocked or LSSD
designs based on the scan types.

6. Edge mixing is the scenario that happens where there are flops connected in series and if the clocks
driving them are of two types in terms of their edges. Like is one flop is of positive edge triggered and
the second is of negative triggerred there happens the edge mixing issue. Flops operating in same edge
like –ve, -ve and +ve,+ve are ok. And even flops operating –ve and +ve are also considered to be ok but
the flops operating +ve and then followed by –ve causes a major edge mixing issue as in one clock pulse
itself there happens two shifts at intersection of a +ve and –ve flops and this has to be rectified with the
use of a lock up latch to induce half cycle delay triggered provided with an inverted clock that of the first
flop.
7. Flow of scan or the steps in scan Insertion:

O Setup/Build up --- input files, output files, libraries, etc.

O Analysis --- Scan DRC's.

O Insertion --- Replacement of all the flops to the scan flops and then building the scan chains or the
stitching process.

a. Setup:

o Input files.

o Output files.

--Input files:

o We need the design netlist from the sythesis team. Will be in the form of basic verilog codes. This is
the sythesized gate level netlist.

o We need the standard library files including all the details of the design netlist files. This also will be
provided by the sythesis team.

o Do files or command files or the script files to run the input files. This DFT engineer has to create. This
deals with the clock, reset, onstate and offstate value, the scan chain length, the violations, fixing
violations, etc.

o tcd (Tessent Core Description)files. It is an optional one. During partial scan, few are scanned and few
are not. The number of scanned flops details will be there in this file and also the scanned chains. So
when we try to do the rescan it gives error. If there are no pre scanned flops, tcd is not required.

--Outpul files generated after scan:

O Scan inserted netlist --- scan replaced flops details after stitching.
o ATPG setup files are generated. Two files --- do file and test proc file (TPF). The do file will have the
information about the clock, reset and the scan chain. The test proc will have the information on the
shift and the capture phase. How many clock pulses are required for both shift and capture phase.
Frequecy of the clock, etc.

o Scan cells reports and scan chains reports. Scan chain report will have the details on how many flops
are there in a chain and how many chains are there. Scan cell report will have the indepth detail on the
flops or cells in each and every chain with the flop names and everything. And the connectivity.

O Scan definition files. Similar to Scan cell file and scan chain file. This final file is to be handed over to
the PD domain for their work.

o Scan configuration ---- In order to reduce the scan cycles, we break the complete chain into multiple
chain and then chain execution becomes parallel and hence reduced scan time. Hence this step talks
about the number of scan chains based on the number of pins and pads in the design or the number of
primary inputs and outputs the designer has allocated for DFT. Dedicated pins are required for the SE, SI,
TM signals.

b. Analysis:

In this we need to check wth DRC's or rules and then analyse whether the proposed design is suitable for
subjecting to insertion or not.

--Scan DRC's: It is the design rule checks or DFT rule checks.

o Clock controllability.

o Set/Reset controllability.

o Tri state Buses/Buffers.

o Potential race condition.

o X source violation.

o Feedback loops.

c. Insertion Phase:

After the analysis phase, all the violations are fixed and then in this insertion phase the proper scan
logics are inserted in the whole design. The proper stitching happnes.

8. The compressor is the module which converts the internal more number of chains to external minimal
channels. It consists of exor gates to compress the data which can be used as either a buffer or an
inverter. But there are possibilities of X value propogation from the chains to the output channels which
will damage or corrupt the output and can also stop the propogation og correct data to the output.

Masking Logic: Hence in order to rectify this problem of X values we use a decoder logic and AND gates.
A fanout of shift registers from the top level chain is used as the masking register. This output is given as
the input to the decoder and then forwarded to the AND gate whose other input is the internal scan.
The decoder will make the AND gate output as 0, if the flop is propogating X value. The AND gates are
called as masking logic.

Pipeline flops: In order to meet the timing by avoiding the delays added by the EX-Or gates, pipeline
flops are added in the design which breaks the total reg-out path into reg-reg and reg-out path.

The pipeline flops are provided with EDT clock and the scan flops are with Scan clock.

9. The compression technique aids in reducing the test data volume and the overall test time.
Test Time, TT = no.of patterns * no.of shift cycles per pattern * clk period

Without compression:

O Let there be 1500 patterns, 500 shift cycles per patterns and clk period be 20ns, then

TT = 1500 * 500 *20 = 15 ms.

With compression:

Let there be 2000 patterns, 50 shift cycles per patterns and clk period be 20ns, then

TT = 2000 * 50 * 20 = 2 ms

Though the number of patterns required for compression is more, the total test time requried is
comparatively very less.

Test Data Volume, TDV = no. of patterns * no.of shift cycles * no. of channels

Without compression:

O Let there be 1500 patterns, 500 shift cycles per patterns and no. of channels be 2, then

TDV= 1500 * 500 *2 = 2.25 MB

With compression:

Let there be 2000 patterns, 50 shift cycles per patterns and no. of channels be 2, then

TDV = 2000 * 50 * 2 = 0.2 MB

11.Types of scan insertion:

Full scan ---- If the entire flop designs in the entire chip is replaced as scan flip flops then it is called as
full scan. Combinational ATPG algorithm methodology is applied. The non scan elements are called the
balck box cells.

Partial scan ---- Only few of the flop designs are converted to SDflops and may be few are not. Non
scanned cells are tested by Sequential ATPG algorithm.

To Down or flat --- Single DFT insertion operation at the top level of the design. This flow is simple in
overall but requires to be altered and repeated in the entire design if there is any change in the design.
Hence not suitable for very large design as it involves hude complexity and time consuming. Causes huge
routing congestion.
Bottom up: In this hierarchical scan synthesis, The DFT insertion is performed at lower level of hierarchy
then incorporated into DFT insertion at higher level of hierarchy. Introduced on high level gate designs.
Any alteration in the design doesn’t require the whole design changes. Time consuming and complexity
is also less compared to the top down. The DFT inserted block is created and can be used in future
designs. The routing congestion will anyways be there.

12. Lockup Latch is a latch cell that is inserted between two scan cells and clocked by the inversion
of the previous scan cell’s clock. A lockup latch prevents hold violations for scan cells that might
capture data using a skewed clock edge.
If we keep a buffer, it will not provide half cycle delay. Only latch will give half cycle delay. Flop
is full cycle delay. Lock up latch is synchronized and it is work with clock, there have much
controllability.
Same lock up latch, if it is sitting between the ends of the chain to the EDT.
Considering the above scenario, since the latch is placed at the end of the first scan chain, which
acts as a delay element for next scan chain, is called as terminal lock-up latch.
The clock mixing also called as domain mixing is a scenario caused while mixing or stitching two
different flops that belong to two different clocks in a single chain.
In a scan chain if the flops are having different clocks, then it is called clock mixing.

Before doing clock mixing, we should check with team lead. To balance the tool will remove 25
flops from upper chain and put them in 2nd chain. By default tool will insert a lockup latch as there
is a clock domain crossing.
13. Scan chains are said to be balanced if all the chains present internally are having equal number
of scan flops.
The main advantage of doing this is in the shift phase the number of clock pulses required to
initialize the scan flops are equal to the chain length. So if there are 100 flops per chain then only
100 clock pulses is required to initialize during shift phase. But if there is an imbalance in the chain
length like one chain is having 150 flops and other chains are having 75 flops each then by default
the shift phase should be given with 150 clock pulses as that of the maximum chain length but the
smaller chains will only be using 75 pulses keeping all the remaining as of no use resulting in
unnecessary delays and power loss. And also it increases the overall test time and testing cost of
the design.

14. tcd (Tessent Core Description)file is an optional one. During partial scan, few flops are scanned
to scan flops and few are not. The number of scanned flops details will be there in this file and also
the scanned chains. So when we try to do the rescan it gives error. If there are no pre scanned flops,
tcd is not required. This is especially required in the bottom up approach where the tcd files will
have the sub block scanned informations.

15. Design Rule Checking (DRC) verifies as to whether a specific design meets the constraints
imposed by the process technology to be used for its manufacturing. DRC checking is an essential
part of the design flow and ensures the design meets manufacturing requirements and will not
result in a chip failure.
Bus contention is one of the scan DRC’s which happens when many of the flop outputs access the
bus at the same time and hence the bus becomes in a dilemma to choose which output has to passed
on further. The confusion arrives when there are multiple output values coming out but if all the
values are same there won’t be any confusion.
This violation is fixed with tri state buffers having active high control signals. Out of many outputs
coming only for that the SE is given direct and to rest all the SE is inverted and hence during shift
the output corresponding to SE = 1 will only be passed to the bus and restricting remaining all
other outputs.
The same logic can be attained with the use of AND and OR logics as well.
10. In Scan chains, each flop is converted to a scan flop as per the different scan methodologies.
The below is the muxed based design with additional mux along with the flop. The inputs SI and
SE are the scan input and the scan enable input added as per the scan convertion.

The flop combi designs present internally is replaced into the below form with scan flop combi designs
working in two modes --- fundtional and DFT mode based on the scan mode or the test mode signal.
When TM = 0, Functional mode.
TM =1, DFT mode.
Furthure in the DFT mode, there are two modes of operation, Shift mode and the caapture mode as per
the SE signal. When SE = 1, Shift phase and when SE = 0, Capture phase.
The below deiagram shows the shift and capture phase operation. During shift phase, the initialization of
all the flops happen bypassing the combi path and hence during this the scan path is formed and is tested
and during the capture phase the flop takes value from the combi path and this is when the combi path is
tested.

The number of clock pulses required in the shift phase depends on the number of flops per chain. And
ideally only one clock pulse ir required for capture phase, called as combinational ATPG algorithm and if
more than one clock pulse is required then called as sequential ATPG algorithm.
16. In order to find the degug issuues in the EDT logic we need to bypass the EDT logic with the use of
bypass logic. Whenever there happens an X value in the chain, the corresponding cycle report will not
locate the exact error location and hence the bypass logic is inserted which adds extra mux logics at the
beginning of all chains so that all the parallel chains will be converted to a single serial chain passing
through the MUX where each mux is connected with one input of the previous chain output.
The selection pin to all the MUX is a newly added EDT_bypass logic pin.
At the output also there is one mux with inputs from the last chain and the channel output.
When the bypass = 1, the path will bypass the compressor and the decompressor logics and will be directly
from the input channels to the mux and then to the chain I and then to another mux and chain two and
this goes till end and then to the output channel. This single big chain also called as Daisy chain.
Only few test patterns are provided to the chain and not all just for the debug case.
18. If there are pre existing scan chains in the design and if we subject them for full scan then the design
will throw error under S6 violation and hence we have provide information regarding these pre existing
scan chains also called as sub chains and also on the sub chain clocks tio the design with proper commands.
add sub_chains block1 sub_chain1 scan_in1 scan_out1 5 mux_scan scan_en
add subchain clocks sub_chain1 0 rx_clk –first_cell_clock –last_cell_clock –leading_edge

The same process for other scan chains if any.

Block1 is the scan chain name with scan_in1 and scan_out1 as the primary input and output of the
particular scan chain. There are 5 flops in that chain which are using muxed scan style and the scan enable
input is given as scan_en. About the clock information all the 5 flops are having same clock with leading
edge and 0 as the offset value with name rx_clk.

20. The ICGS are the integrated clock gating circuits used to overcome the problem of normal clock gating
circuits. The clock gating circuits are basically used to control the clocking to certain modules in a design
thereby turning them off when working unnecessorily and hence reducing the power wastage and the
module efficiency as well. A basic clock gating circuit is obtained with a simple AND gate but inorder to
avoid the presence of glitches in the output clock behavior which eliminates the required clock behavior
we use the latch based clock gated circuits which add a furthur half cycle delay resulting to avoid the
glitches. The ICGs are simply available as simple modules which can be easily added into the design by
simply decalring them in the library files. In order to ensure proper clocking the test enable is always
grounded so that the clock is always obtained in the output. But for DFT mode of operation this test_en
is connected to TM so that the top clock is always obtained to rest of the design.
During scan, these ICG’s latch designs are converted to transparent latch designs.

21. In any IC there will be:

o Pin -- is specific to logic gates or flip flops or the standard cells.

o Port --- is specific to block level or chip level or which is top level module on the standard cells. Both
inputs and outputs.
o Pad --- If any component working with a low voltage is given straight with an output from another
component working with a different voltage will definitly affect the performance of the latter component
and hence we use the concept of pads which is designed to give a fixed rated output irrespective of the
input rate and hence avoids the damage of the subsequent components.
Hence, pads are an intermediate connections between ports to ports or port to pin or pin to port similar
to the way of a stabilizer which controls the voltage fluctuations without affecting the product
performance. So pads can be called as a voltage regulators or Controllers.
These are present in both the input level and the output level. It can be input pad, output pad or
bidirectional pads.

Functionality of a bidirectional pads:

This can function as both I/P and O/P pads. Input pad means connecting the external data from the input
port to the corelogic and output pad means transferring the internal data out to the output port.
When the IE = 1 and OE = 0, the pad acts as an Input pad and thus it passes the input port data to the core
logic. When the IE = 0 and OE = 1, the pad acts as an Output pad and thus it passes the internal data to
the output port.

23. In combinational ATPG, only one clock pulse is enough in the capture phase for testing the
combinational logic but in the sequential ATPG more than one clock pulse is required for the same purpose
which depends on the sequential depth. If the depth = 3, then 3 clock pulses are required for the test and
if its 2 then only two are required.
22. The number of scan chains in the design depends on the following:

O The number of alloted pins for the whole design.

O The compression ratio according which the number of external channels are converted to internal
chains which infact determine the below factors.
O The overall test coverage.
O Data and time compression. (X source tolerance)
O Area and layout overhead.
O Diagnostics and impact on manufacturing flow.
O Low pin counts for multiple chip testing.

If adopted with more compression ratio, then the quality of the design will get reduced ad there will be
multiple scan chains which are not being managed properly.

24. The functional engineer will only check whether the AND gate is working as per the truth table or not.
ABY
000
010
100
111
We will never come to know if there is any transition problem internally between the nodes to the output
or any other physicall defects in the design. These all things will definitely affect the overall performance
of the design which is actually done by the DFT engineer where the transition delay faults, path delay
faults, IDDq faults, Stuck at faults are all covered resulting in the overall performance testing of the gate.

25. EDT update is used to reset the LFSR flops before starting a new pattern for the EDT clock.
26.
i. This is a clock DRC that comes in the C5 and C6 violations which prevents the scan insertion process and
the corresponding flop will not replaced to its scan equivalent as the data pin is also provided with the
clock value the flop output will always be a constant value.
The same has to fixed with manual hacking process where a mux is introduced inbetween the clock and
the D input so that during the DFT mode the data pin gets a data from amy of the nearby flop output or
from any other combinational output value with TM as the selection line and the clock as data during the
functional mode.

ii. For any flop to be replaced to its scan equivalent all the flops should have a top level clock and if not
then the flop wont be replaced to the scan equivalent. Hence there also a mux has to be introduced to fix
this C4 violation which provides the top level clock for the DFT mode and the flop output as the clock input
for the functional mode.

17. Out of the three scan approaches – full scan, partial and partition scan, the partial and partition scan
approaches are preffered for the designs having sub blocks in the design.
As in the full scan method, the entire design from top to bottom will completely be replaced to the scan
equivalent which is not practical for the designs where pre existing sub blocks are present as the design
will throw errors like S6 if subjected to scan again. Hence will have to proceed with either partition or
partial where not the full buit some exemptions will be there for scan process and also we can specify the
pre scan chain details with the names, ports, number of flops, scan style used and the clock informations
with proper commands as shown below.

add sub_chains block1 sub_chain1 scan_in1 scan_out1 5 mux_scan scan_en

add subchain clocks sub_chain1 0 rx_clk –first_cell_clock –last_cell_clock –leading_edge

19.
Highly automated process:- using scan insertion tools ,the process for inserting scan circuitry into a design
is highly automated ,thus requires very little manual effort.
Highly effective and predictable:-scan design is highly effective ,well understood ,and well accepted
method for generating high test coverage for design.
Ease of use:-using scan methodology we can insert both scan circuitry and run atpg without the aid of a
test engineer.
To reduce the tet time
To get controllability aand observability over the device.