Chapter 7

Input/Output (I/O)
Input/Output (I/O) Architecture
• After Processors & Memory Module, third key
element
• Interface outside world with inside of computer
through system bus
• Why not directly connect peripherals to the
system bus
— Wide variety of peripherals with various methods of
operation, necessary logic impractical
— Speed difference
— Different data format/word length
• Structure
— Interface to CPU and Memory
— Interface to one or more peripherals
Generic Model of I/O Module
Input/Output Problems
• Wide variety of peripherals
• Delivering different amounts of data
— At different speeds
— In different formats
• Almost all of them slower than CPU and
RAM
• Solution
— Need I/O modules
External Devices
• External Device = Peripherals
• Three categories
— Human readable
– Screen, printer, keyboard
— Machine readable
– Suitable for communication with equipment e.g.?
— Communication
– Suitable for communication with remote devices
e.g.?
External Device Block Diagram
I/O Module Function
• Control & Timing
• CPU Communication
• Device Communication
• Data Buffering
• Error Detection
Control & Timing
• Internal resources are shared – thus I/O include
control & timing to coordinate flow of data b/w recourses/devices

• For example control of the transfer of data

from an external device to the processor might
involve following I/O steps:
— CPU asks I/O module to check device status
— I/O module returns status
— If ready, CPU requests data transfer
— I/O module gets data from device
— I/O module transfers data to CPU
• Variations for output
I/O Module Communication With Processor
• Involves the following
— Command decoding
– Accepts signals e.g. READ SECTOR etc
— Data exchange
– Data exchanged over data bus
— Status reporting
– Important to know the status of I/O module why?
– BUSY or READY
— Address recognition
– I/O module must recognize one unique address for
each peripheral it controls
I/O Module Communication With Devices
• Involves the following
— Commands
– Dictates the function device has to perform e.g.
READ, WRITE etc
— Data exchange
– Data in the form of a set of bits to be sent or
received from devices
— Status Signals
– State of the device
– BUSY or READY
— Address recognition
– I/O module must recognize devices uniquely
Data Buffering
• Why need it, we all know it…. speed gap!
• Data exchange
— WRITE
– Data from main memory sent to I/O module in a
rapid burst
– Data then sent to device at its rate
— READ
– Data from Device buffered into I/O module so that it
does not tie up main memory for slow speed
• I/O module must be able to operate at
both device & memory speed
Error Detection
• Two classes of errors
— Mechanical/Electrical malfunction
– E.g. paper jam, bad sector etc
— Unintentional changes to the bit pattern
– Some form of error detecting code is usually used,
e.g. even parity or odd parity
I/O Module Diagram
I/O Module Diagram
I/O Module Decisions
• May hide or reveal device properties to
CPU
— I/O module may hide details of timing, format
and electromechanics of devices
• Support multiple or single device
• Control device functions or leave for CPU
— I/O module may leave much of the work of
controlling a device (e.g. rewind a tape) visible
to the processor
• I/O channels Vs I/O controllers
— Channels are modules presenting high level
interface
— Controllers are most primitive modules
Input Output Techniques
• Programmed
• Interrupt driven
• Direct Memory Access (DMA)
Programmed I/O - Steps
• During execution of a program CPU
encounters instruction relating to I/O
— CPU executes instruction by issuing command to I/O
module
— I/O module performs operation
— I/O module sets status bits
— CPU checks status bits periodically
— I/O module does not interrupt CPU
— CPU waits for I/O module to complete
operation – waste of time
• To explain further we view it from
— I/O command (issued by processor) point of view
— I/O instructions (executed by processor) point of view
I/O Commands point of view
• To execute an I/O related instruction
— CPU issues address
– Identifies module (& device if >1 per module)
— CPU issues command – 4 types of commands
– Control - telling module what to do, e.g. spin up disk
– Test - check status, e.g. powered on? Busy? Error?
– Read &
– Write, Module transfers data via buffer from/to device
I/O Commands- example READ command
I/O Instruction point of view
• Close correspondence b/w I/O related
instructions and commands one-to-one relationship
• CPU commands contain address of the
device
• I/O module interprets the address line to
see if the command is for itself
• When processor, memory and I/O share a
common bus, two modes of addressing
are possible
— Memory mapped I/O
— Isolated I/O
Memory Mapped and Isolated I/O (1/3)

• Memory mapped I/O

— Devices and memory share an address space
— With 10 bit address line a combined total of 1024
memory locations and I/O addresses can be supported in any
combination
— I/O looks just like memory read/write Load AC 517
— No special commands for I/O - Large selection of
memory access commands available from set architecture

• Memory mapped I/O allows efficient

programming (advantage) but valuable memory
space wasted (disadvantage)
Memory Mapped and Isolated I/O (2/3)

• Isolated I/O
— Separate address spaces 10 bit address line can now
support 1024 memory location and 1024 devices
— Need I/O or memory select lines to differentiate if
this instruction (Load AC 517) is for memory or I/O device
— Special commands for I/O
— Limited instruction set
Memory Mapped and Isolated I/O (3/3)
Interrupt Driven I/O
• Overcomes CPU waiting
• No repeated CPU checking of device
• I/O module interrupts when ready
Interrupt Driven I/O
Basic Operation
• How it works? Let’s see it from I/O module point of view:
— I/O recieves read command from CPU
— I/O module gets data from peripheral whilst
CPU does other work
— I/O module interrupts CPU
— CPU acknowledges the interrupt
— I/O module transfers data
CPU point of view
• CPU issues read command
• Does other work
• Checks for interrupt at end of each
instruction cycle
• If interrupted:-
— Saves context (registers)
— Processes interrupt
– Fetches data & stores
• Restores context of the paused program
Interrupt Driven I/O Technique for
READ Command
 Simple Interrupt
Processing

• Occurrence of an interrupt triggers a

number of events
• When I/O device completes an I/O
operation, the sequence of events that
occurs is shown in the figure
Changes in Memory and Registers
for an Interrupt
Design Issues
• Two design issues arise in implementing
interrupt I/O
— Multiple I/O modules with numerous devices
so how to identify which device issued the
interrupt?
— Which interrupt to process incase of multiple
interrupts?
Identifying Interrupting Module (1/2)

• Four general categories of techniques

— Different line for each module
– Impractical to dedicate more than few bus lines or processor
pins to interrupt lines
– Limits number of devices
– What if module has more than one device?
— Software poll
– At interrupt, processor branches to Interrupt service
routine (ISR)
– Job of ISR is to poll each I/O module to determine
which module has issued interrupt
– Can be in form of asking each module in turn through
TEST I/O
– Disadvantage guess?
Identifying Interrupting Module (2/2)

• Daisy Chain or Hardware poll

— All module share a common interrupt request line
— Interrupt Acknowledge sent down a chain by CPU
— Module responsible places vector on data bus
— CPU uses vector to identify handler routine – avoids
executing general ISR
— Vectored interrupt
• Bus Arbitration
— Module must claim the bus before it can raise interrupt
— When processor detects interrupt, it responds on INTA
line
— The requesting module then places its vector on the
data line
— e.g. PCI & SCSI
Multiple Interrupts
• The techniques mentioned also provide a
way of assigning a priority
— With multiple lines the processor just picks the
interrupt line with highest priority
— With software poll, the order in which the
modules are polled determine the priority
— Similarly the order of modules on a daisy chain
determines their priority
— Finally bus arbitration can also employ a
scheme for giving priority as was discussed in
chapter 3
Example - PC Bus
• Intel 80x86 has one interrupt request
INTR line and single interrupt ack INTA
line
• To handle variety of devices and priority
structure - it is usually configured with external arbiter
• 8086 based systems use one 82C59A
interrupt controller
• 82C59A has 8 interrupt lines, thus can
handle up to 8 modules
• If control of more than 8 modules is
required, cascade arrangement is used
Sequence of Events
• 82C59A’s sole responsibility is to manage
the interrupts
— 82C59A accepts interrupts
— 82C59A determines priority
— 82C59A signals 8086 (raises INTR line)
— CPU Acknowledges, using INTA line
— 82C59A puts correct vector on data bus
— CPU processes interrupt
82C59A Interrupt
Controller
Direct Memory Access
• Interrupt driven and programmed I/O
require active CPU intervention
— Transfer rate is limited
— CPU is tied up
• DMA is the answer especially when large volumes of
data
DMA Function
• Additional Module (hardware) on bus is
capable of:
— Mimicking processor
— Taking control from CPU for I/O
Typical DMA Module Diagram
DMA Operation
• CPU issues command to DMA module by
sending the following information:
— Read/Write
— Device address
— Starting address of memory block for data
— Amount of data to be transferred – number of
words
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when
finished
Direct Memory Access – READ Command
DMA Transfer - Cycle Stealing
• DMA uses bus
— only when free from processor
— Or it must force processor to suspend its operation
temporarily – called cycle stealing
• DMA controller takes over bus for a cycle
• Transfer of one word of data
• Not an interrupt
— CPU does not switch context - why?
• CPU suspended just before it accesses bus
— i.e. before an operand or data fetch or a data write
• Slows down CPU but not as much as CPU
doing transfer
DMA and Interrupt Breakpoints During an
Instruction Cycle
The diagram shows where in the instruction cycle
the processor can be suspended
DMA Configurations (1/3)

• Single Bus, Detached DMA controller

• Each transfer uses bus twice
— I/O to DMA then DMA to memory
• CPU is suspended twice
• Clearly inefficient
DMA Configurations (2/3)

• Single Bus, Integrated DMA controller

• Controller may support >1 device
• Each transfer uses bus once
— DMA to memory
• CPU is suspended once
DMA Configurations (3/3)

• Separate I/O Bus

• Bus supports all DMA enabled devices
• Each transfer uses bus once - DMA to memory
• CPU is suspended once
• I/O interfaces in the DMA module reduced to one
• Easily expandable configuration
• Data exchange between I/O module and DMA takes place
off the system bus
Intel 8237A DMA Controller
• Interfaces to 80x86 family and DRAM
• When DMA module needs bus it sends HOLD signal to
processor
• CPU responds HLDA (hold acknowledge)
— DMA module can use buses
• E.g. transfer data from memory to disk
1. Device requests service of DMA by pulling DREQ (DMA
request) high
2. DMA puts high on HRQ (hold request),
3. CPU finishes present bus cycle (not necessarily present
instruction) and puts high on HDLA (hold acknowledge).
HOLD remains active for duration of DMA
4. DMA activates DACK (DMA acknowledge), telling device to
start transfer
5. DMA starts transfer by putting address of first byte on
address bus and activating MEMR; it then activates IOW to
write to peripheral. DMA decrements counter and increments
address pointer. Repeat until count reaches zero
6. DMA deactivates HRQ, giving bus back to CPU
8237 DMA Usage of Systems Bus
Fly-By
• 8237 DMA is known as fly-by DMA
controller
• Data does not pass through and is not
stored in DMA chip
— DMA can only transfer between I/O port and
memory
— Not between two I/O ports or two memory
locations
• However the DMA can do memory to
memory transfer via a register Read page 225
I/O Channels
• Handling I/O devices evolved with time
— Initially CPU directly handled the devices
— I/O Module added, Programmed I/O, then Interrupt
driven I/O
— DMA
— DMA enhanced, I/O module could execute I/O related
instructions without CPU – I/O channel
— Memory added and I/O module became a computer in
its own right – I/O processor
• Improves speed
— Takes load off CPU
— Dedicated processor is faster
• Can handle sophistication- I/O devices getting more
sophisticated, e.g. 3D graphics cards
I/O Channel - Types

• Controls multiple devices

• Dedicated to transfer of data with one
device at any one time

• Multiple devices at the same time

• Byte multiplexer for slow speed devices
• Block Multiplexer for hi speed devices
Interfacing
• Connecting devices to the I/O module
• Major characteristic of the interface is
whether it is Parallel interface Or Serial interface
• Parallel interface has been traditionally
used for high speed devices
• New generation of high speed serial
interface dominates parallel interface now
• Two configuration
— Point to Point interface provides a dedicated line between
I/O module and device e.g. keyboard
— Multipoint are in effect buses e.g. Firewire, InfiniBand
IEEE 1394 FireWire
• Gigabyte speed & capacity of processor
and storage device respectively require
high speed interfacing
• Efforts in this regards resulted in High
performance serial bus - FireWire
• Fast
• Low cost
• Easy to implement
• Also being used in digital cameras, VCRs
and TV
FireWire Configuration
• Daisy chain
• Up to 63 devices on single port
— Really 64 of which one is the interface itself
• Up to 1022 buses can be connected with
bridges
• Automatic configuration
• No bus terminators
• May be tree structure
Simple FireWire Configuration
FireWire 3 Layer Stack
• Physical
— Transmission medium, electrical and signaling
characteristics
• Link
— Transmission of data in packets
• Transaction
— Request-response protocol
FireWire Protocol Stack
FireWire - Physical Layer
• Data rates from 25 to 400Mbps
• Two forms of arbitration
— Based on tree structure
— Root acts as arbiter
— First come first served
— Natural priority controls simultaneous requests
– i.e. who is nearest to root
— Fair arbitration
— Urgent arbitration
FireWire - Link Layer
• Two transmission types
— Asynchronous
– Variable amount of data and several bytes of
transaction data transferred as a packet
– To explicit address
– Acknowledgement returned
— Isochronous
– Variable amount of data in sequence of fixed size
packets at regular intervals
– Simplified addressing
– No acknowledgement
FireWire Subactions
InfiniBand
• I/O specification aimed at high end
servers
— Merger of Future I/O (Cisco, HP, Compaq,
IBM) and Next Generation I/O (Intel)
• Version 1 released early 2001
• Architecture and spec. for data flow
between processor and intelligent I/O
devices
• Intended to replace PCI in servers
• Increased capacity, expandability,
flexibility
InfiniBand Architecture
• Remote storage, networking and connection
between servers
• Attach servers, remote storage, network devices
to central fabric of switches and links
• Greater server density
• Scalable data centre
• Independent nodes added as required
• I/O distance from server up to
— 17m using copper
— 300m multimode fibre optic
— 10km single mode fibre
• Up to 30Gbps
InfiniBand Switch Fabric
InfiniBand Operation
• 16 logical channels (virtual lanes) per
physical link
• One lane for management, rest for data
• Data in stream of packets
• Virtual lane dedicated temporarily to end
to end transfer
• Switch maps traffic from incoming to
outgoing lane
InfiniBand Protocol Stack
Foreground Reading
• Check out Universal Serial Bus (USB)
• Compare with other communication
standards e.g. Ethernet