UNIT III

MEMORY MANAGEMENT
CHAPTER 1
BASIC OF MEMORY MANAGEMENT
Definition:
Memory management is process of managing the primary memory
This is done by the memory management modules of the operating system
called memory manager.
Functions of Memory management as follows
• Keeping track of the status of each location of the memory.
• In Multiprogramming system it decides which process gets memory first.
• Allocation of memory.
• Getting back the memory when the user finishes the job.
• Protection of program in memory from interference by other programs.

TWO TYPES OF MEMORY

• Main memory or Primary Memory
• Secondary Memory
Main memory or Primary Memory
• The memory which is placed in the boundary of the cpu circuitry is called
primary memory or main memory.
• Program, data to be processed by computer are kept ready in this
memory.
• The results obtained after processing are stored in primary memory.
• The capacity of the main memory depends on the total instruction, data
and results that are kept in the memory at a time.
• This memory loses its content when power is removed. So it is Volatile.
Secondary Memory:
• The memory which is placed outside the boundary of CPU circuitry is
called secondary memory.
• Programs and data are stored permanently in this memory.
• Non Volatile Memory: It will not lose the data when power off.
 • Information transferred from main memory to secondary memory during
execution

LOGICAL & PHYSICAL ADDRESS MAP

Logical or Virtual Address:
• Logical address is a memory address given by the user.
• Logical address is generated by the CPU.
• CPU requests the data from the physical memory using logical address.
Physical address:
• Physical address is an address given to each storage cell of the main
memory.
•Physical address is the actual address where the data is stored.
Explanation:
• During compilation Physical and logical address are the same.
• During execution Physical and logical address are different.
• Logical address space: A set of logical address generated by the
program.
• Physical address space: A set of physical address corresponding to
logical address

Relocation or (memory mapping hardware)

• Relocation is a process of converting logical address into physical
address by a register called Relocation Register
• The relocation register has a value. This value is added with the logical
address to generate actual physical memory address.

Logical
Relocation Value Main memory
+
CPU Register

Address Physical
Address
Memory allocation
• Memory allocation is defined as a process of assigning blocks of memory
to processes an request by the operating system.
Types of memory allocation
1. Contiguous memory allocation
2. Non contiguous memory allocation

Contiguous memory allocation

• In Contiguous allocation methods the available memory is divided into
two partitions.
• In one portion operating system is stored. The other portion is used to
store user processes.

During execution:
• Protection must be given to avoid user process from accessing the
operating system.
• Protection must be given to protect the processes from one another.

This is achieved by two register

• Limit register
• Relocation register
Limit register: It contains the range of the process logical address.
Relocation register: It contains the value of the starting physical address
where the user process can use.
 Limit Relocation
register register

Logical

CPU + Main memory

<
Address Physical Address

Addressing error

Example:
Logical address ➔346
Relocation registers ➔1000
Relocation register + logical address ➔physical address
Physical address ➔1346
Types:
1. Single partition allocation
2. Fixed sized partition allocation
3. Variable sized partitioned allocation

Single partition allocation:

• This is the simplest memory management method.
• It won’t support multiprogramming
• In this memory area is divided into two partitions.
• The operating system occupies some fixed memory area of 100k.
• The remaining area of 412k is allocated to a single user process.
Explanation:
• Even though a free memory area of 112k is available it is not possible to
allocate it to process p2 of size 100k.
• 112k of memory is left unused until the process p1 terminates when p1
terminates.p2 is given the memory.
Demerits:
• Inefficient usage of memory area
• If the running process needs an IO the CPU has to wait until IO is
completed this causes wastage of CPU time.
• It won’t support multiprogramming.

Fixed sized partition allocation

• This memory management technique supports multiprogramming.
• In this the operating system occupies some fixed portion of the memory
and the rest is divided into number of fixed partition of equal or unequal
size by operating before processing starts.
• A process whose size is equal or less than the partition size can be
loaded into a partition. When a partition is free a process is selected
from the long queue by the operating system.
PROCESS MEMORY SIZE
P1 500K
P2 524K
P3 450K
Main memory size ➔2048k
Fixed partition ➔ 512k size
Process p1,p2,p3 are given memory
Explanation:
• In this memory management a process with size less or equal to
partition size will be loaded in the memory.
• The small memory area will be left unused inside the partition as shown
in figure.
• This area cannot be used by other processes.
• This wastage of memory area inside the partition is called internal
fragmentation.
Demerits:
1. Process whose size is larger than the partition size cannot be loaded.
2. Wastage of memory due to internal fragmentation.

Variable sized partition allocation

• This memory management technique supports multiprogramming.
• In this OS occupies some fixed portion and the remaining is divided into
number of partitions.
• The partitions are created during processing so as to match the process
sizes with partition sizes.
Main memory size ➔ 2560k Operating system ➔400k
Remaining area is allocated to the processes
 PROCESS MEMORY SIZE
P1 600K
P2 1000K
P3 300K
P4 700K
P5 500K

Types of fragmentation:

Internal fragmentation
• Internal fragmentation is wastage of memory space inside a fixed partition.
• It happens when a process of size less than the partition size in fixed
memory allocation.

PROCESS MEMORY
SIZE
P1 600K
P2 1000K
P3 300K
P4 700K
P5 500K
External fragmentation
Inability to use the free memory space created during variable partition
allocation. It is because the available free space is not contiguous.

After some times p2 terminates.At this place process p4 is loaded.

Total memory size of 300 + 260K = 560K is available; it cannot be allocated to
process p5. This is because the available space is not contiguous

Compaction:
It a process of moving the contents of all allocated partitions in variable
partition in one side so that they become contiguous and all free memory
space on the other side so they become contiguous.
Example:

Process Memory
size
P1 600k
P2 1000k
P3 300k
P4 700k
P5 500k

• As the fig (b) the memory has three processes p1, p4, p3 and two holes of
size 300k and 260k.
• After compaction all the free holes are compacted so that a free memory
space of 560k is available.
• Now the process p5 of size 500k can be loaded into the memory.

DEMERITS:
• Relocation hardware increases the cost of computer and slows down the
speed
• Compaction time is high
• Some memory area is still unused.
Paging:
• Paging is a memory management technique.
• In this memory management there is no problem of fragmentation
This technique uses the following principle:
• Each user process is divided into equal pieces called pages.
• The physical memory is divided into equal pieces of same size as pages
called frames
• By using a special hardware called page map table any page can be
placed in any frame.
Principle of Operation:
Let the size of the memory be 16k. In which 2k is allocated for OS.
The remaining area is divided into equal size pages.
we are using 1k pages the processes
Example:
Let the size of the memory be 16k. In which 2k is allocated for OS.
The remaining area is divided into equal size pages.
Processes are divided into pages
process P1 is divided into 4 pages
Process P2 is divided into 3 pages
process P3 is divided into 2 pages
Using page map table the pages can be placed in any frame

Process Memory size

P1 4K
P2 3k
P3 2k
 • Page map table is a hardware which is used to give the location of page in
the memory.
• Paging solves fragmentation without physically moving the partition.
• In our example 5k bytes of memory are available but they are not
contiguous.
• If there is a fourth process p4 of 4k size ,this can be divided it into four
pages and can be placed in the frames 2, 4,6,8 and 15
• Demerits:
• Page map hardware increases the cost of computer and slows down the
speed.
• Some memory area is still unused due to page breakage.
• Processor time is wasted in maintaining and updating page map table.
Page allocation:

Let S be the size of the given process and P be the size of each page
It process requires
n =|S/P| pages
To load the above process into physical memory we need n frames.
The efficiency of the page allocation depends on the quick selection of n free
frames.
Free frames are randomly distributed in the physical memory.

Let q be the Probability of free frames.

Average number of frames to be tested in MMT x = n/q
Suppose if n=10 and q = ½
Then x=20 frames
We have to check an average of 20 frames to get 10 frames

Address translation:
The process of converting the logical address to physical address is called
translation.
Paging
• Paging is a memory management technique.
• In this memory management there is no problem of fragmentation
This technique uses the following principle:
• Each user process is divided into equal pieces called pages.
• The physical memory is divided into equal pieces of same size as pages
called frames
• By using a special hardware called page map table any page can be
placed in any frame.
Logical address generated by CPU has two parts:
Page number p and Page offset d
The value of d is combined with F to find the actual physical address .
The logical address = 01101011 Page number p = 011 page offset d
= 01011

Address translation:

The process of converting the 2D logical address generated by the CPU

to 1D actual physical address is called Translation
 Logical address

CPU Page no(p) Offset(d)

Physical addressing
Page frame No
number
0 - C
1 -
2 -
3 -
m- -
1
PMT

Example:
Logical address generated by CPU has two parts:
Page number p
Page offset d
Page number p gives the page number and the offset d gives the displacement
within the page.
During execution,
The address translation has to find the corresponding frame F for given page no
p.
The value of d is combined with F to find the actual physical address of the
requested instruction by the cpu.
Normally computer use 8 bit or 16 bit or 32 bit etc addressing. So the page
number p and offset d are to be separated from this logical address.

Let the size of the logical address space be 2 m

Let the size of the page be 2npage numbers = (m-n)bits
The lower order n bits gives the offset (d)

Example:
Let Logical address be 256k ie 28k
Let Size of the page be 32k ie 25k
 Let The size of addressing be 8 bits
Therefore Page number (p) = m-n= 8-5 =3 bits.
Page offset(d) = 5 bits
Therefore
The location 0 to 31 are in page 0
The location 32 to 63 are in page 1
The location 63 to 95 are in page 2
The location 95 to 128 are in page 3

The logical address 01101011 ie (107)10

Page number p= 011 ie (3) 10
Page offset d = 01011 ie (11) 10
011 01001
1 11
Page 0 (1*32)+11 0 Frame 0
Page 1 + 32 Frame 1
Page 2 42 Frame 2
Page3 1 64 Frame 3
96
Page 7 128
255 Frame 7

The logical address 01101011 = page no p =3 and offset d =11

Therefore Physical address =43

HARDWARE SUPPORT FOR PAGING

• Page Map Table – PMT
• Translation Look aside Buffer – TLB
• Page Map Table Limit Register – PMTLR
Page map table: (PMT)
• Each process has a Page Map Table.
• Pointer to this table is maintained in PCB.
• This table is made up of fast register.
• It is used to store the page no and the corresponding frame no in the
memory.
• This table is present in the main memory

Translation Look aside Buffer:(TLB)

• This technique overcomes the problem of time delay in PMT.
• It is a high speed associative memory.
• Associative memory is a memory which can be accessed only by the
memory content not by address.

Page Map Table Limit Register:(PMTLR)

• PMTLR contains the maximum number of pages for the process running
at that time.
• This is used to check whether the pages accessed belong to the
executing process.

Working:
The cpu generated address consists of two parts
1. Page number(p)
2. Page offset(d)

Page number:
It gives the page number requested by cpu.
Page offset:
• It contains the position of the requested instruction in the page.
• The page number is checked with the TLB entries.
• If that page is present in TLB, the corresponding physical address is
calculated using the frame number and offset.
 • If the particular page is not in TLB, the page number is checked with
PMTLR.
• If it is a valid page number, the corresponding frame number is found
out from PMT.
• Using frame number and offset the physical address is calculated.

PROTECTION:
Protection is the process of protecting memory from unauthorized
access.

PMTLR (Page Map Table Limit Register)

• It contains the address range, which the process can access.
• It controls the running process to access its own address space.
• Accessing other address space is protected by PMTLR

Valid-Invalid Bit in PMT

This bit is attached to every entry in the PMT
• Valid –v, Invalid –i
• If bit == “v”, then the corresponding page is valid ,page can be used
by the process
 • If bit == “i” , then the corresponding page is invalid ,page cannot be
used by the process

Page Frame bit

no no
0 2 v
1 5 i
2 7 v
Access bit in PMT:
This bit is attached to every entry in the PMT
• Using this bit, access to particular page is restricted.
• The following are different access bits
1. Read
2. Write
3. Execute
• During execution the access bit is checked, any attempt to violate will
cause a hardware interrupt.

Sharing
• Sharing is the process of mapping a page with many other processes.
• This is achieved by keeping only one copy of that process in physical
memory and adding a special entry named ‘shared’ in PMT.
• If process P1 and P2 is in need of process P3 then process P3 is declared to
be shared.
Advantage:
1. Eliminates fragmentation.
2. It supports multiprogramming.
3. It increases the memory and processor utilization
4. Relocation overhead is eliminated.

Disadvantage:
1. PMT hardware increases the cost of the computer.
2. Inefficient usage of memory.
 3. Processor time is wasted in maintaining and updating PMT.

CHAPTER 2 VIRTUAL MEMORY

It is a concept that permits the programmers to construct their programs
to the size of secondary storage without the restriction of main memory.

Basic principle:
Programs size (Virtual Address Space) can exceed the available main
memory.

Implementation
• During process execution, required sections are only loaded in main
memory.
• The OS takes care of
1. Which section to bring into memory
2. When to bring the section into memory
3. Where to place the sections in the memory.

Necessity of virtual memory:

• Large virtual memory
• Efficient use of memory
• Unconditioned multiprogramming

1. Large virtual memory:

In Virtual Memory, the programmer can write large programs without
worrying about the size of the main memory.

2. Efficient use of memory:

In VM during execution only the needed sections of a program are loaded
in memory. Example: codes which are executed very rarely are loaded
only when they are required.
3. Support multiprogramming:
In VM, each process occupies only less memory. Hence, pages of many
process can loaded in memory at a time. This increases multiprogramming.

Hardware & control structures

1. Page Map Table (PMT)
2. Page Map Table Limit Register (PMTLR)
3. File Map Table (FMT)
Page Map Table (PMT):
This register stores the page number and its corresponding frame
number in memory. The status bit is set to 1 if the page is in main memory
else it is 0.

Frame no
Page no (P) Status
(F)
0 0 or 1
1 0 or 1
2 0 or 1
m-1 0 or 1

Page Map Table Limit Register (PMTLR)

It checks whether the page needed by the CPU is related to the
executing process.
File Map Table (FMT):
It stores the process page number and its corresponding address in secondary
memory

Page Address in secondary

no P memory
0
1
2
m-1
Working:

Extracting the page number:

• The logical address generated by the cpu consist of page number (p) and
the offset(d).
• The page number (p) is checked with the PMTLR.If it is less than or equal to
the value of PMTLR the page is a valid page else an error occurs.

Check for page fault:

• The corresponding status bit for this page number (p) is checked in the page
map table.
• The value of status bit can be 0 or 1.
• If the status bit is 1 the corresponding frame number address is added with
offset(d) to get the actual memory address.
• If the status bit is 0 the corresponding page is not in memory. This condition
is called page fault.

Handling page fault:

• The page fault routine in the operating system finds the address of the
needed page (p) in the secondary memory using FMT
Reading the page:
• With the help of the page p secondary memory address using FMT the
corresponding page is read from the secondary memory in to a free
frame in main memory.
Restarting the interrupted execution:
The operating system restarts the execution from step 1 now page fault will
not happen and the execution proceeds normally.

Demand paging:
It is a memory management technique. The process of moving the pages
from secondary memory to main memory on demand by CPU is called Demand
Paging.
Concepts:
• Each user process is divided into equal pieces called pages.
• Physical memory is divided into equal pieces of same size as pages
called frames
• Then by using a special hardware called page map table any page can be
placed in any frame depending on the demand by cpu.

0 0
1000
1500 LOAD 1 , 7200 1
2000
3000 2
4000 4
5000 5
6000 6 0
Operating
7000 1 system
7200 007000 2
8000 7 3 2
9000 8 4 3
10000 9 5 4
 Logical address Main memory
space
Example
✓ Consider a process of size 10k (10x1 k size) stored in secondary
memory with logical address space.
✓ Let the size of main memory be 5k (5x1 k size) in which OS occupies 2k
space.
✓ The status of loaded page & location of page in main memory are given
in PMT
Page Frame
Status
no no
0 1 4 Page No: gives the no. of pages in the
1 1 2 process.
2 0 - Status: page is loaded in the memory or not
3 0 - (1 stored, 0 not stored)
4 0 - Frame no: Gives the corresponding frame
5 0 - no for the page in main memory
7 0 -
8 0 -
9 0 -
Let us assume that initially first 2 pages say page 0 and page 1 are loaded
from secondary memory into the main memory.
➢ The status bit 1 in PMT tells the corresponding pages are loaded in
the main memory and main memory locations are given by the value
in the frame number.
➢ Suppose if there is a reference to Page7, but its bit is 0, then the
page fault mechanism load the page into main memory and change
the status bit as 1
 Address space

Page replacement policies

When a page needed by the CPU is not in the main memory, page fault occurs.
To overcome the page fault the required page must be brought into the main
memory by the operating system.
The principle used to select the frame for freeing is called page replacement
Policy.
The following are the steps used during page replacement policy.
1. Find the location of the needed page on the secondary memory using
FMT
2. Find a free frame in memory
• If there is a free frame, load the needed page in it.
• Else use the page replacement algorithm to select the page
frame to be replaced.
• If the dirty bit is 1, write the page to the secondary memory
and load the needed page.
• If the dirty bit is 0, load the needed page.
Reference String:
During execution, the program refers the page in memory in some order.
This order is called reference string.
Page replacement algorithm:
It is used to select a page frame for loading a new page on it.
FIFO (First In First Out):
• This is the simplest page replacement algorithm.
• The page that spent long time in memory is replaced by a new page.
Principle:
• When a page is replaced in the memory it is placed in the tail of the
queue.
• When a page is to be replaced ,it is replaced from the head of the queue.
• That is one which stays longer time
• The time for replacement is calculated from the time the page was
loaded into the memory.
Step Initially 3 frames are empty
1

Step First reference is page 7.

2 This cause page fault and is loaded in tail of 7
the queue.

Step Second reference is page 0.

3 This cause page fault and is loaded in next free 0 7
frame.

Step Third reference is page 1.

4 This cause page fault and is loaded in next free 1 0 7
frame.

Step Fourth reference is page 2. This cause page

5 fault. 1 0 2
But there is no free frame.
So FIFO algorithm replaces page 7 by 2.
 Step Fifth reference is page 0.
6 Since it is in the memory no page fault. 1 0 2

Step Sixth reference is page 3. This cause page

7 fault. 1 3 2
But there is no free frame.
So FIFO algorithm replaces page 0 by 3.

Step Seventh reference is page 0. This cause page

8: fault. 0 3 2
But there is no free frame.
So FIFO algorithm replaces page 1 by 0.

Step Eight reference is page 4. This cause page

9: fault. 0 3 4
But there is no free frame.
So FIFO algorithm replaces page 2 by 4.
Therefore 7 page faults.
Demerits:
• If an active page which is in the head of the node is replaced page
fault occurs immediately.
• Number of page faults increases with increases with increase in the
number of frame.

Optimal (Opt):
This algorithm replaces the page that has to be referenced after long time.
Example:
Let the reference string be 7 0 1 2 0 3 0 4

Step Initially 3 frames are empty

1
Step First reference is page 7.
2 This cause page fault and is loaded in tail of the 7
queue.

Step Second reference is page 0.

3 This cause page fault and is loaded in next free 0 7
frame.

Step Third reference is page 1.

4 This cause page fault and is loaded in next free 1 0 7
frame.

Step Fourth reference is page 2. This cause page

5 fault. 1 0 2
But there is no free frame.
So OPT algorithm replaces page 7 by 2.

Step Fifth reference is page 0.

6 Since it is in the memory no page fault. 1 0 2

Step Sixth reference is page 3. This cause page fault.

7 But there is no free frame. 3 0 2
So OPT algorithm replaces page 1 by 3.

Step Seventh reference is page 0.

8: Since it is in the memory no page fault. 3 0 2

Step Eight reference is page 4. This cause page fault.

9: But there is no free frame. 3 4 2
So OPT algorithm replaces page 0 by 4.
Therefore 3 page faults.
LRU (Last Recently Used):
This algorithm replaces the page that has not been used for long
time.

Example: Let the No. of Frames in the memory be 3

Let the reference string be 7 0 1 2 0 3 0 4.
Step Initially 3 frames are empty
1

Step First reference is page 7.

2 This cause page fault and is loaded in tail of 7
the queue.

Step Second reference is page 0.

3 This cause page fault and is loaded in next 0 7
free frame.

Step Third reference is page 1.

4 This cause page fault and is loaded in next 1 0 7
free frame.

Step Fourth reference is page 2. This cause page

5 fault. 1 0 2
But there is no free frame.
So LRU algorithm replaces page 7 by 2.

Step Fifth reference is page 0.

6 Since it is in the memory no page fault. 1 0 2

Step Sixth reference is page 3. This cause page

7 fault. 3 0 2
But there is no free frame.
 So LRU algorithm replaces page 1 by 3.

Step Seventh reference is page 0.

8: Since it is in the memory no page fault. 3 0 2

Step Eight references is page 4. This cause page

9: fault. 3 0 4
But there is no free frame.
So OPT algorithm replaces page 2 by 4.
Therefore 3 page faults.
NRU (Not Recently Used):
This algorithm replaced the page which was not recently used. To
implement this algorithm, the following are need.
Steps:
1. The memory is considered as circular queue.
2. Each frame has a bit called use bit. When the page is loaded first, dirty
bit=0. When the Page is referenced, the dirty bit=1.
3. When the page is to be replaced, OS moves round the queue and checks
for the dirty bit. If it is 0, the frame is freed up and new page is loaded.
If dirty bit is 1, it is cleared to 0.
4. This process continues until all the required frames are freed for loading
the pages.
Example:
Pointer P, points to page 10. Since, its dirty bit is 1, it is not removed, but it
is set to 0.
Then the pointer moves to page 17. Since its dirty bit is 0, the page is
removed and new page is loaded in this frame. The figure below shows this:
• This algorithm is a simple modification of FIFO algorithm
• The, memory is considered as a circular queue of fixed size frames
• Each frame has a bit called reference bit when a page is loaded the
reference bit is set to1
 • A pointer moves over the circular queue and these points to the page to
be replaced next.

Step:
• The pointer (p) checks the value of the reference bit if it is 0 the page is
replaced and the new page in loaded
• If the reference bit in 1 the reference bit is cleared and its arrival time is
reset to the current time this concept is called second chance.
• Steps (i) & (ii) are replaced until a page with reference bit 0 or a page
which is given the second chance is found and is replaced.
Example: 7 0 1 2 0 3 0 4
Initially 3 frames are empty
Step
1
0 0 0

The page 7, 0 and 1 are loaded one by one in

Step time 0, 3, 7 and reference bits are all 1 .No 1 0 7
2 page fault.

1 1 1

The next reference to page 2 occurs at time 10

and it causes a page fault. 1 0 7
Step
The pointer p pointes to the page to be replaced
3
Reference bit is checked value is 1 . 0 0 1
Then it is cleared and the loading time is reset
 to the current time 10.

The next frame is checked this process until a

Step page with reference bit 0. 1 0 2
4 so the page 7 will be replaced by 2.

0 0 1