EE214B

Advanced Analog Integrated Circuit Design

- Winter 2014 -

Boris Murmann
Stanford University
[email protected]

Table of Contents

Chapter 1 Introduction
Chapter 2 Bipolar Junction Transistors
Chapter 3 Elementary BJT Amplifier Stages
Chapter 4 MOS Transistor Modeling
Chapter 5 gm/ID-Based Design
Chapter 6 Electronic Noise
Chapter 7 Feedback: Introduction
Chapter 8 Feedback: TIA Example
Chapter 9 Feedback: Cherry-Hooper Example
Chapter 10 Feedback: Root Locus and Frequency Compensation
Chapter 11 Low-Frequency Distortion Analysis
Chapter 12 High-Frequency Distortion Analysis
Chapter 13 Mismatch
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 Chapter 1
Introduction

Boris Murmann
Stanford University
Winter 2013-14

Analog Circuit Sequence

Design of mixed-signal
and RF building blocks

Analog IC Fundamentals Analysis and design of

for undergraduates and high-performance EE314A
entry-level graduate circuits in advanced
RF Integrated Circuit
Design
students technologies

EE314B
Advanced RF
Integrated Circuit
EE114/EE214A EE214B Design
Fundamentals of Advanced Analog
Analog Integrated Integrated Circuit
Circuit Design Design EE315A
VLSI Signal
Conditioning Circuits

EE315B
VLSI Data
Conversion Circuits

B. Murmann EE214B Winter 2013-14 – Chapter 1 2

 The Evolution of a Circuit Designer

EE101A,B EE114 EE214 EE314A,B

EE315A,B

B. Murmann EE214B Winter 2013-14 – Chapter 1 3

Key Elements of This Course

EE 214A
Bandwidth

Power Dissipation

EE 214B

Electronic Noise Nonlinear Distortion

Advanced Technologies

B. Murmann EE214B Winter 2013-14 – Chapter 1 4

 Significance of Electronic Noise (1)

Signal-to-Noise Ratio
2
Psignal Vsignal
SNR = ∝ 2
Pnoise Vnoise

B. Murmann EE214B Winter 2013-14 – Chapter 1 5

Significance of Electronic Noise (2)

Example: Noisy image

http://www.soe.ucsc.edu/~htakeda/kernelreg/kernelreg.htm

B. Murmann EE214B Winter 2013-14 – Chapter 1 6

 Significance of Electronic Noise (3)

The "fidelity" of electronic systems is often determined by their SNR

– Examples
• Audio systems
• Imagers, cameras
• Wireless and wireline transceivers

Electronic noise directly trades with power dissipation and speed

– In most circuits, low noise dictates large capacitors (and/or small R,
large gm), which means high power dissipation

Noise has become increasingly important in modern technologies with
reduced supply voltages
– SNR ~ Vsignal2/Vnoise2 ~ (αVDD)2/Vnoise2

Designing a low-power, high-SNR circuit requires good understanding of
electronic noise

B. Murmann EE214B Winter 2013-14 – Chapter 1 7

Nonlinear Distortion

vo

vi

Small-signal approximation

All electronic circuits exhibit some level of nonlinear behavior

– The resulting waveform distortion is not captured in linearized small-
signal models

The distortion analysis tools covered in EE214B will allow us to quantify
the impact of nonlinearities on sinusoidal waveforms

B. Murmann EE214B Winter 2013-14 – Chapter 1 8

 Significance of Distortion

For a single tone input, the nonlinear terms in a circuit’s transfer function
primarily result in signal harmonics

For a two-tone input, the nonlinear terms in a circuit’s transfer function

result in so-called “intermodulation products”

Example: Two interferer tones create an

intermodulation product that corrupts the
signal in a desired radio channel

B. Murmann EE214B Winter 2013-14 – Chapter 1 9

Noise and Distortion Analysis in EE214B

Main objective
– Acquire the basic tools and intuition needed to analyze noise and
distortion in electronic circuits
– Look at a few specific circuit examples to “get a feel” for situations
where noise and/or distortion may matter

Leave application-specific examples for later

– EE314A/B: Noise and distortion in LNAs, mixers and power amplifiers
– EE315A: Noise and distortion in filters and sensor interfaces
– EE315B: Noise and distortion in samplers, A/D & D/A converters

B. Murmann EE214B Winter 2013-14 – Chapter 1 10

 Feedback Circuit Analysis in EE214B

Builds on what you have already learned in EE114/214A

– Return ratio analysis

Goals for this quarter
– Reinforce your understanding of return ratio analysis using a broader
set of applications
– Establish alternative methods using a two-port approach to extend
your understanding of feedback analysis in practical circuits
– Learn about advanced frequency compensation techniques
– Investigate the effect of feedback on noise and distortion

B. Murmann EE214B Winter 2013-14 – Chapter 1 11

Technology

MOSFET Bipolar Junction Transistor (BJT)

EE214A

EE214B

B. Murmann EE214B Winter 2013-14 – Chapter 1 12

 Bipolar vs. CMOS (1)

Advantages of bipolar transistors

– Higher fT for a given feature size/lithography
– Higher supply voltages
– Higher intrinsic gain (gmro)
– Lower parametric variance

Disadvantages of bipolar transistors

– Lower integration density, larger features
– Higher cost (due to higher fabrication process complexity)
– Poor ohmic switch (as required for switched capacitor circuits)

B. Murmann EE214B Winter 2013-14 – Chapter 1 13

Bipolar vs. CMOS (2)

A.J. Joseph, et al., "Status and

Direction of Communication
Technologies - SiGe BiCMOS and
RFCMOS," Proceedings of the
IEEE, vol. 93, no. 9, pp.1539-
1558, September 2005.

• CMOS tends to require finer lithography to achieve same speed as

BiCMOS process with advanced BJT

B. Murmann EE214B Winter 2013-14 – Chapter 1 14

 Example that Leverages Densely Integrated CMOS:
RF Transceiver System-on-a-Chip (SoC)

S. Abdollahi-Alibeik et al., “A 65nm dual-Band 3-Stream

802.11n MiMo WLAN SoC," ISSCC 2011

In modern CMOS technology, millions of logic gates can be integrated

together with moderate- to high-performance analog/RF blocks

B. Murmann EE214B Winter 2013-14 – Chapter 1 15

Example that Leverages High-Speed BJTs:

Long Range Automotive Radar

Lee, JSSC 12/2010

Ragonese et al., ISSCC 2009

H.P. Forstner et al., A 77GHz 4-Channel Automotive Radar

Transceiver in SiGe, RFIC 2008.

B. Murmann EE214B Winter 2013-14 – Chapter 1 16

 Example that Leverages High-Speed BJTs:
Transimpedance Amplifier for Optical Communications

C. Knochenhauer et al., “40 Gbit/s transimpedance amplifier with high linearity range in 0.13 µm SiGe
BiCMOS, Electronics Letters, May 12, 2012.

B. Murmann EE214B Winter 2013-14 – Chapter 1 17

Trends

K. Roberts et al., “100G and Beyond with Digital Coherent

Signal Processing,” IEEE Communications Magazine, July 2010.

Optical network systems are beginning to use complex modulation

schemes (going away from simple on/off keying)

Need linear front-end circuits and very high-speed A/D converters

B. Murmann EE214B Winter 2013-14 – Chapter 1 18

 Summary of Learning Goals

Understand device behavior and models for transistors available in

advanced integrated circuit technologies
– SiGe BJT, short channel MOS

Acquire the basic intuition and models for
– Noise analysis
– Distortion analysis
– Feedback circuit analysis
– Frequency compensation and related design techniques for
broadband amplification

Solidify the above topics in a hands-on project involving the design and
optimization of a broadband amplifier circuit

B. Murmann EE214B Winter 2013-14 – Chapter 1 19

Staff and Website

Instructor
– Boris Murmann

Teaching assistant
– Valerie Barry

Administrative Assistant
– Ann Guerra, Allen-207

Lectures are available online
– But please come to class to keep the discussion interactive!

Web page
– http://coursework.stanford.edu/homepage/W14/W14-EE-214B-01.html
– Check regularly, especially the discussion board
– Register for online access to grades and solutions

B. Murmann EE214B Winter 2013-14 – Chapter 1 20

 Text and Prerequisites

Required textbook
– Chan Carusone, Johns, Martin, Analog Integrated Circuit Design, 2nd
Edition, Wiley, 2011
– Errata: http://analogicdesign.com/students/errata/

Reference texts
– B. Razavi, Design of Integrated Circuits for Optical Communications,
2nd Edition, McGraw-Hill, 2012
– Gray, Hurst, Lewis and Meyer, Analysis and Design of Analog
Integrated Circuits, 5th Edition, Wiley, 2008

Course prerequisite: EE114/214A or equivalent
– Basic device physics and models
– Frequency response, dominant pole approximation, ZVTC
– Biasing, small-signal models
– Common source, common gate, and common drain stages
– Port impedance calculations
– Feedback basics

B. Murmann EE214B Winter 2013-14 – Chapter 1 21

Textbook Content Overview

EE214B EE315A
EE315B

B. Murmann EE214B Winter 2013-14 – Chapter 1 22

 Tools and Technology

Simulation
– HSpice + circuit netlists
– Cscope and/or Matlab for post-processing
– You can use your own tools/setups “at own risk“

Getting started
– Read “CAD basics” handout provided on the course website

EE214B Technology
– 0.18-µm SiGe BiCMOS
– BSIM3v3 models provided under /usr/class/ee214b/hspice
– Models correspond to a typical technology as described in
• Wada, et al., “A manufacturable 0.18-um SiGe BiCMOS
technology for 40-Gb/s optical communication LSIs,” BCTM 2002

B. Murmann EE214B Winter 2013-14 – Chapter 1 23

Assignments

Homework (20%)
– Handed out on Wednesdays, due following Wednesdays in class
– Late submission penalty: 0.5 dB/hour
– Lowest HW score will be dropped
– Policy for off-campus students
• Fax or email to SCPD before deadline stated on handout

Midterm Exam (30%)

Design Project (20%)
– Design of an amplifier using HSpice (no layout)
– Work in teams of two
– OK to discuss your work with other teams, but no file exchange!

Final Exam (30%)

B. Murmann EE214B Winter 2013-14 – Chapter 1 24

 Honor Code

Please remember that you are bound by the honor code

– We will trust you not to cheat
– We will try not to tempt you

But if you are found cheating it is very serious
– There is a formal hearing
– You can be thrown out of Stanford

Save yourself a huge hassle and be honest

For more info
– http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/honorcode.pdf

B. Murmann EE214B Winter 2013-14 – Chapter 1 25

Course Outline

Bipolar Junction Transistors

Elementary BJT Amplifier Stages

MOSFET Modeling and gm/ID Based Design

Noise Analysis

Feedback Circuits
– Analysis tools
– Frequency compensation techniques
– Wideband gain stages

Distortion Analysis

B. Murmann EE214B Winter 2013-14 – Chapter 1 26

 Chapter 2
Bipolar Junction Transistors

Boris Murmann
Stanford University
Winter 2013-14

Textbook Sections: 8.1–8.4, 8.6

History

W. Brinkman, D. Haggan, and W. Troutman, “A history of the invention

Bardeen, Brattain, and Shockley, 1947 of the transistor and where it will lead us,” IEEE J. Solid-State Circuits,
vol. 32, no. 12, pp. 1858-1865, Dec. 1997.

W. Shockley, M. Sparks, and G. K. Teal, “P-N junction

transistors,” Phys. Rev. 83, pp. 151–162, Jul. 1951.

B. Murmann EE214B Winter 2013-14 – Chapter 2 2

 Conceptual View of an NPN Bipolar Transistor (Active Mode)

VBE

Device acts as a voltage
IC ∝ e kT / q controlled current source
– VBE controls IC

The base-emitter junction is
forward biased and the base-
collector junction is reverse
IB << IC n- C
biased
p B VCE
The device is built such that
– The base region is very thin
VBE n+ E
– The emitter doping is much
higher than the base doping
– The collector doping is much
lower than the base doping

B. Murmann EE214B Winter 2013-14 – Chapter 2 3

Outline of Discussion

In order to understand the operation principle of a BJT, we will look at

– The properties of a forward biased pn+ junction
– The properties of a reverse biased pn- junction
– And the idea of combining the two junctions such that they are joined
by a very thin (p-type) base region

The treatment in the following slides is meant to be short and qualitative

– See any solid-state physics text for a more rigorous treatment
(involving band diagrams, etc.)

B. Murmann EE214B Winter 2013-14 – Chapter 2 4

 pn+ Junction in Equilibrium (No Bias Applied)

nn0 ≅ ND (Donor concentrat ion)

pp 0 ≅ NA (Acceptor concentrat ion)
ni2 n2
np 0 = ≅ i
p p 0 NA
ni2 n2
pn 0 = ≅ i
nn0 ND

nn Concentration of electrons on n side (majority carriers)

pn Concentration of holes on n side (minority carriers)
np Concentration of electrons on p side (minority carriers)
pp Concentration of holes on p side (majority carriers)

The subscript “0” in the carrier concentrations

denotes equilibrium (no bias applied)

B. Murmann EE214B Winter 2013-14 – Chapter 2 5

Built-in Potential

The built in potential sets up an electric field that opposes the diffusion of
mobile holes and electrons across the junction
dp
(Drift ) qµ ppE = qDp (Diffusion )
dx
p  n  N N  kT
⇒ ψ 0 = VT ln p 0  = VT ln n0  ≅ VT ln A 2 D  VT =
 
 pn0   np 0   ni  q

B. Murmann EE214B Winter 2013-14 – Chapter 2 6

 pn+ Junction with Forward Bias (1)

Depletion region narrows, diffusion processes are no longer balanced by

electrostatic force

At the edge of the depletion region (x=0), the concentration of minority
carriers [np(0)] can be computed as follows

 n   N  ND
VBE VBE
n2 BE
V

ψ 0 − VBE = VT ln  n  ≅ VT ln  D  ∴np (0) = ⋅e VT

= np0 e VT
≅ i e VT
 n (0)   n (0)  ψ0
NA
 p   p  e VT

B. Murmann EE214B Winter 2013-14 – Chapter 2 7

pn+ Junction with Forward Bias (2)

The result on the previous slide shows that forward biasing increases
the concentration of electrons at the “right” edge of the depletion region
by a factor of exp(VBE/VT)

The same holds for holes at the “left” edge of the depletion region
VBE VBE
ni2
pn (0) = pn0 ⋅ e VT ≅ ⋅ e VT
ND

Since ND >> NA, it follows that pn(0) << np(0), i.e. the concentration of
minority carriers is much larger at the lightly doped edge

Since there must be charge neutrality in the

regions outside the depletion region, the
concentration of the majority carriers at the
edge of the depletion region must also increase
− However, this increase is negligible when
np(0) << pp ≅ NA (or pn(0) << nn ≅ ND)
− These conditions are called “low-level
injection”

B. Murmann EE214B Winter 2013-14 – Chapter 2 8

 What Happens with the Injected Minority Carriers?

The carriers would “like” to diffuse further into the neutral regions, but
quickly fall victim to recombination

The number of minority carriers decays exponentially, and drops to 1/e
of the at the so-called diffusion length (Lp or Ln, on the order of microns)

In each region, there are now two types of currents

− Diffusion of injected minority carriers due to non-zero dnp/dx (or dpn/dx)
− Majority carrier currents for recombination

B. Murmann EE214B Winter 2013-14 – Chapter 2 9

Summary – Forward Biased pn+ junction

Lots of electrons being injected into the p-region, not all that many holes
get injected into the n+ region
– The heavier n-side doping, the more pronounced this imbalance
becomes

The electrons injected in the p region cause a diffusion current that
decays in the x-direction due to recombination

The recombination necessitates a flow of holes to maintain charge
neutrality; as the diffusion current decays, the hole current increases,
yielding a constant current density along the device

Near the edge of the depletion region, the electron diffusion current
dominates over the hole current that supplies carriers for recombination
– This is a very important aspect that we will come back to

B. Murmann EE214B Winter 2013-14 – Chapter 2 10

 Reverse Biased pn- Junction

Reverse bias increases the

width of the depletion
region and increases the
electric field

Depletion region extends
mostly into n- side

Any electron that would
E
“somehow” make it into the
depletion region will be
e-
swept through, into the n-
region
– Due to electric field

B. Murmann EE214B Winter 2013-14 – Chapter 2 11

Bipolar Junction Transistor – Main Idea

“cut here”

Make the p-region of the pn+ junction very thin

Attach an n- region that will “collect” and sweep across most of the
electrons before there is a significant amount of recombination

B. Murmann EE214B Winter 2013-14 – Chapter 2 12

 Complete Picture

n+ p n-

Straight line because base is thin; negligible recombination

(“short base” electron profile)

B. Murmann EE214B Winter 2013-14 – Chapter 2 13

BJT Currents

http://en.wikipedia.org/wiki/Bipolar_junction_transistor

Primary current is due to electrons captured by the collector

Two (undesired) base current components
– Hole injection into emitter ( 0 for infinite emitter doping)
– Recombination in the base ( 0 for base width approaching zero)

B. Murmann EE214B Winter 2013-14 – Chapter 2 14

 First-Order Collector Current Expression

dnp (x) np (0)

Jn = qDn ≅ −qDn Current density
dx WB
np (0) A is the cross-sectional area WB
IC ≅ qADn
WB is the base width
V
n2 BE
np (0) ≅ i e VT Result from pn+ junction analysis
NA
V
qADnni2 VBET
∴ IC ≅ e
WBNA

VBE qADnni2
∴ IC ≅ IS e VT IS =
WBNA

B. Murmann EE214B Winter 2013-14 – Chapter 2 15

Base Current

IB = IB1+ IB2 where IB1 = Recombination in the base

IB2 = Injection into the emitter

IB1 follows from dividing the minority carrier charge in the base (Qe) by its
“lifetime” (τB)
1 VBE
Qe 2 np (0)WBqA 1 WBqAni2 VT
IB1= = = e
τb τb 2 τbNA

IB2 depends on the gradient of minority carriers (holes) in the emitter. For a
“long” emitter (all minority carriers recombine)

  2 VBE − x  VBE
qADp ni2 V
= −qADp   i e VT e p 
dpn (x) d n L
IB2= −qADp = e T
dx x =0  dx  N   Lp ND
  D   x =0

In modern narrow-base transistors IB2 >> IB1.

B. Murmann EE214B Winter 2013-14 – Chapter 2 16

 Terminal Currents and Definition of αF, βF

IE = − (IC + IB )

IC
βF = (ideally infinite)
IB
IC β
αF = = F (ideally one)
( −IE ) 1 + βF

The subscript “F” indicates that the device is assumed to operate in the
forward active region (BE junction forward biased, BC reverse biased, as
assumed so far)
– More on other operating regions laterB

B. Murmann EE214B Winter 2013-14 – Chapter 2 17

Basic Transistor Model

Simplified model; very useful for bias point calculations

(assuming e.g. VBE(on) = 0.8V)

B. Murmann EE214B Winter 2013-14 – Chapter 2 18

 Basewidth Modulation (1)

Side note:
BJT inherently has better (higher)
ro than MOS since lower doping
on n-side (collector) has most of
the depletion region inside the
collector

∂  qADnni2 
VBE
∂IC I dWB
=  e VT =− C
∂VCE ∂VCE  WB (VCE ) ⋅ NA 
 W B dVCE

B. Murmann EE214B Winter 2013-14 – Chapter 2 19

Early Voltage (VA)

IC WB
VA = =− = const. (independent of IC )
∂IC dWB
∂VCE dVCE

VBE
VT  VCE 
IC ≅ ISe 1 + 
 VA 

B. Murmann EE214B Winter 2013-14 – Chapter 2 20

 Small-Signal Model

 VBE 
dIC d  VT  VCE   IC
gm = = ISe 1 +  =
dVBE dVBE   VA   VT
 

I 
d C 
β 1 IC
=  F=
1 dIB g
gπ = = = m (assuming βF = const.)
rπ dVBE dVBE βF VT βF

 VBE 
1 dIC d  VT  VCE   IC
go = = = ISe 1+  ≅
r0 dVCE dVCE   VA   VA
 

B. Murmann EE214B Winter 2013-14 – Chapter 2 21

Intrinsic Gain

IC VA VA
gmro ≅ ⋅ = VT ≅ 26mV (at room temperature)
VT IC VT

In the EE214B technology, the SiGe npn device has VA = 90V, thus

90V
gmro ≅ = 3460
26mV

Much larger than the intrinsic gain of typical MOSFET devices

B. Murmann EE214B Winter 2013-14 – Chapter 2 22

 Outline – Model Extensions and Technology

Complete picture of BJT operating regions

Dependence of βF on operating conditions

Device capacitances and resistances

Technology
– Junction isolated
– Oxide isolated with polysilicon emitter
– Heterojunction bipolar (SiGe base)
– BiCMOS
– Complementary bipolar

B. Murmann EE214B Winter 2013-14 – Chapter 2 23

BJT Operating Regions

Discussed so far
BE = forward biased
CE = reverse biased

B. Murmann EE214B Winter 2013-14 – Chapter 2 24

 Carrier Concentrations in Saturation

Base-Collector junction is forward biased

np(WB), and therefore also IC, strongly depend on VBC, VCE

VCE(sat) is the voltage at which the devices enters saturation
– The difference between the two junction voltages, small ~0.05B0.3V

B. Murmann EE214B Winter 2013-14 – Chapter 2 25

Gummel Plot

A Gummel plot is a semi-log plot of IC and IB versus VBE (linear scale)

It reveals the regions for which high βF is maintained (region II below)

What happens in regions I and III?

B. Murmann EE214B Winter 2013-14 – Chapter 2 26

 βF Fall-Off

Region III (high current density)

– Injected electron charge in base region nears the level of doping
(“high level injection”)
– For this case, it can be shown that the injected carrier concentration
rises with a smaller exponent (cut in half) and therefore
1 VBE
2 VT
IC = ISe

Region I (low current density)

– There exists excess base current due to (unwanted) recombination in
the depletion layer of the base-emitter junction
– This current becomes significant at low current densities and sets a
minimum for IB

B. Murmann EE214B Winter 2013-14 – Chapter 2 27

Current Profile of a Forward Biased Diode Revisited

Extra current due to

recombination (small) Total current
Recombination

B. Murmann EE214B Winter 2013-14 – Chapter 2 28

 βF vs. IC and Temperature

≅ 7000 ppm / °C

B. Murmann EE214B Winter 2013-14 – Chapter 2 29

Junction Isolated npn Transistor

B. Murmann EE214B Winter 2013-14 – Chapter 2 30

 Device Capacitances and Resistances

Big mess!

First focus on intrinsic elements

B. Murmann EE214B Winter 2013-14 – Chapter 2 31

Charge Storage

In the intrinsic transistor, charge is stored in the junction capacitances,

Cje and Cjc = Cµ, and as minority carriers in the base and emitter

Both minority carrier charge injected into the base and into the emitter,
are proportional to exp(VBE/VT)
– But the charge in the base is much larger, as discussed previously

Base terminal must supply charge for neutrality

Voltage dependent charge
capacitance (Cb)

∆VBE causes change in injected charge

B. Murmann EE214B Winter 2013-14 – Chapter 2 32

 Base Charging Capacitance

∂Qe ∂Qe ∂IC

Cb ≜ = = τFgm
∂VBE ∂IC ∂VBE

∂Qe ∂ 1  qADnnp (0)

τF = =  np (0)WBqA  IC =
∂IC ∂IC  2  WB
∂  1 WB2  1 WB2
τF =  IC  =
∂IC  2 Dn  2 Dn

τF is called the base transit time (in forward direction)

Typical values for high-speed transistors are on the order of 1B100ps

B. Murmann EE214B Winter 2013-14 – Chapter 2 33

Junction Capacitance

C j0 2C j0
Cj = n
 VD 
1 − 
 ψ0 

B. Murmann EE214B Winter 2013-14 – Chapter 2 34

 Small-Signal Model with Intrinsic Capacitances

Cµ
B C

v1 rπ Cπ gmv1 ro
–
E

Cπ = Cb + C je = Cb + 2C je0
C jc0
Cµ = C jc = n
 VCB 
1 + 
 ψ 0c 

B. Murmann EE214B Winter 2013-14 – Chapter 2 35

Model with Additional Parasitics

Neglect

Range of numbers
re ~1-3Ω
rb ~ 50-500Ω Values at high end of these ranges may have large
impact on performance  Try to minimize through
rc ~ 20-500Ω
advanced processing & technology
CCS ~ 3-200fF

B. Murmann EE214B Winter 2013-14 – Chapter 2 36

 BJT in Advanced Technology

Oxide isolated

Self-aligned structure (base and emitter align automatically)

Very thin base (~100nm or less) through ion implantation

Reduced breakdown voltages compared to more traditional structures

B. Murmann EE214B Winter 2013-14 – Chapter 2 37

SiGe Heterojunction Bipolar Technology

A heterojunction is a pn junction formed with different materials for the n

and p regions

Germanium is added to the base of a silicon bipolar transistor to create a
heterojunction bipolar transistor (HBT)
– Base formed by growing a thin epitaxial layer of SiGe
– Results in a lower bandgap (and higher intrinsic carrier
concentration) in the base than emitter

In “band diagram speak” the bandgap mismatch increases the barrier to
the injection of holes (in an npn transistor) from the base into the emitter

One way to enumerate the benefits of a SiGe base is to look at the
current gain expression

B. Murmann EE214B Winter 2013-14 – Chapter 2 38

 HBT Current Gain

Intrinsic carrier concentration in the SiGe base (niB) is larger than

intrinsic carrier concentration in the Si emitter (niE)

qADnnp0 qADnnp0 2
qADnniB
DnNDLp 2
WB WB WBNA niB
βF = 2
≅ 2
= 2
= 2
⋅
1 np0 WBqA qADpniE qADpniE qADpniE DpNA WB niE
+
2 τb LpND LpND LpND
Added degree of
freedom for HBT

Base doping (NA) can be increased while maintaining same βF

− Can reduce base width without affecting rb
− Larger ro due to decrease in base width modulation

B. Murmann EE214B Winter 2013-14 – Chapter 2 39

Device Parameter Comparison

SiGe npn HBT
Transistor with 0.7µm2 = 0.22µm x 3.2µm
Emitter Area

300
2
90
3x smaller device
3.2x10-17A
1pA 5x bigger IS
2.0V
5.5V
3.3V
0.56ps 18x smaller τF
10ps
25Ω 16x smaller rb
60Ω
2.5Ω
6.26fF
0.8V
0.4
3.42fF
0.6V
0.33 Oxide isolation vs.
3.0fF
Junction isolation
0.6V
0.33

B. Murmann EE214B Winter 2013-14 – Chapter 2 40

 BiCMOS Technology

CMOS

Older BJTs used poly Si as “diffusion source” for

emitter doping. Advanced (state-of-the-art) BJTs
use epitaxial growth of both the SiGe base and
Si emitter regions

B. Murmann EE214B Winter 2013-14 – Chapter 2 41

Advanced Complementary Bipolar Technology

[Texas Instruments]

B. Murmann EE214B Winter 2013-14 – Chapter 2 42

 Cross Section

[Texas Instruments]

B. Murmann EE214B Winter 2013-14 – Chapter 2 43

Figures of Merit for BJTs

Product of current gain and Early voltage, β·VA

Product of transit frequency and breakdown voltage, fT·BVCEO

Maximum frequency of oscillation, fmax
– More in EE314A

Transit (or transition) frequency, fT
– Formally defined as the frequency for which the current gain of the
device falls to unity
– Important to keep in mind that the basic device model may fall apart
altogether at this frequency
• Lumped device models tend to be OK up to ~fT/5
– Therefore, fT should be viewed as an extrapolated parameter, or
simply as a proxy for device transconductance per capacitance

B. Murmann EE214B Winter 2013-14 – Chapter 2 44

 Transit Frequency Calculation (1)
(AC circuit; DC biasing not shown) Ignore for simplicity

గ ఓ

ଵ =  ௠ గ 1 − 
1 + గ (గ + ఓ ) ௜ ௢ ௠
=
௜ 1 + గ (గ + ఓ )
௢ = ௠
ଵ + ఓ
ଵ

௢ 1
Low frequencies: ≅ ௠ గ = ி for ≪ = ఉ
௜ గ గ + ఓ
௢ ௠ ௠
High frequencies: ≅ for ఉ ≪ ≪
௜
గ + ఓ ఓ

B. Murmann EE214B Winter 2013-14 – Chapter 2 45

Transit Frequency Calculation (2)

|io/ii| gm
(asymptote)
(
ω Cπ + Cµ )
≅ βF
Note that rπ “matters” only for
frequencies up to ωβ = ωT/βF

݃௠
‫ܥ‬ఓ

gm gm
1= ⇒ ωT =
(
ω T C π + Cµ ) Cπ + Cµ

1 C C je Cµ C je Cµ
τT = = b+ + = τF + +
ωT gm gm gm gm gm

B. Murmann EE214B Winter 2013-14 – Chapter 2 46

 fT versus IC plot

“peak fT”

Cje and Cµ High level

dominate injection, τF
increases

gm = IC/VT increases

The particular current value at which fT is maximized depends on the

parameters of a technology and the emitter area of the BJT

B. Murmann EE214B Winter 2013-14 – Chapter 2 47

EE214B Technology

Assumed to be similar to a 0.18-µm BiCMOS technology featuring a
high-performance SiGe npn device
– VCC = 2.5V (BJT), VDD=1.8V (MOS)

See e.g.
– Wada et al., BCTM 2002
– Joseph et al., BCTM 2001
– IBM 7HP documentation
• https://www-01.ibm.com/chips/techlib/techlib.nsf/products/BiCMOS_7HP)
NPN PMOS/NMOS Poly resistor

http://fuji.stanford.edu/events/spring01/slides/harameSlides.pdf

B. Murmann EE214B Winter 2013-14 – Chapter 2 48

 Cross Section of npn Device

B. Murmann EE214B Winter 2013-14 – Chapter 2 49

EE214B npn Unit Device

A technology typically comes with an optimized

layout for a unit device of a certain size

Great care is then taken to extract a Spice model
AE = 0.22µm x 3.2µm
for this particular layout using measured data

Spice model (/usr/class/ee214b/hspice/ee214_hspice.sp)
E
.model npn214 npn
+ level=1 tref=25 is=.032f bf=300 br=2 vaf=90
B + cje=6.26f vje=.8 mje=.4 cjc=3.42f vjc=.6 mjc=.33
+ re=2.5 rb=25 rc=60 tf=563f tr=10p

C + xtf=200 itf=80m ikf=12m ikr=10.5m nkf=0.9

Instantiation in a circuit netlist

* C B E
q1 n1 n2 n3 npn214

B. Murmann EE214B Winter 2013-14 – Chapter 2 50

 BJT Model Parameters

For more info consult the HSpice documentation under

/afs/ir.stanford.edu/class/ee/synopsys/B-2008.09-SP1/hspice/docs_help

PDF files:
home.pdf hspice_cmdref.pdf hspice_integ.pdf hspice_relnote.pdf hspice_sa.pdf
hspice_devmod.pdf hspice_mosmod.pdf hspice_rf.pdf hspice_si.pdf

B. Murmann EE214B Winter 2013-14 – Chapter 2 51

Adding Multiple Devices in Parallel

For the unit device, there exists a practical

upper bound for the collector current
– Due to the onset of high level injection

This means that the unit device can only
E E E
deliver a certain maximum gm

If more gm is needed, “m” unit devices can
B B B
be connected in parallel
C C C
Instantiation in a circuit netlist (m=3)
* C B E
q1 n1 n2 n3 npn214 3

B. Murmann EE214B Winter 2013-14 – Chapter 2 52

 npn Unit Device Characterization

* ee214b npn device characterization

* C B E
q1 c b 0 npn214
Vc c 0 1.25
ib 0 b 1u

.op
.dc ib dec 10 10f 100u
.probe ib(q1) ic(q1) ie(q1) 1x VCC/2
.probe gm = par('gm(q1)')
.probe go = par('g0(q1)')
.probe cpi = par('cap_be(q1)')
.probe cmu = par('cap_ibc(q1)')
.probe beta = par('beta(q1)')

.options dccap post brief

.inc '/usr/class/ee214b/hspice/ee214_hspice.sp'
.end

B. Murmann EE214B Winter 2013-14 – Chapter 2 53

DC Operating Point Output

**** bipolar junction transistors

element 0:q1
model 0:npn214
ib 999.9996n
ic 288.5105u
vbe 803.4402m
vce 1.2500
vbc -446.5598m
vs -1.2327
power 361.4415u
betad 288.5106
gm 10.2746m
rpi 26.8737k
rx 25.0000
ro 313.4350k
cpi 14.6086f
cmu 2.8621f
cbx 0.
ccs 0.
betaac 276.1163
ft 93.5999g

B. Murmann EE214B Winter 2013-14 – Chapter 2 54

 Gummel Plot

B. Murmann EE214B Winter 2013-14 – Chapter 2 55

Transit Frequency

150
fT [GHz]

100

50

0 -4 -3 -2
10 10 10
IC [A]

B. Murmann EE214B Winter 2013-14 – Chapter 2 56

 Intrinsic Gain

ee215 npn
4000

3500

3000

gm /go [GHz] 2500

2000

1500

1000

500

0 -8 -6 -4 -2
10 10 10 10
IC [A]

B. Murmann EE214B Winter 2013-14 – Chapter 2 57

gm/IC

Important to realize that gm will not be exactly equal to IC/VT at high currents

B. Murmann EE214B Winter 2013-14 – Chapter 2 58

 I-V Curves

NPN (1x, A =0.7µm2, I =0.2, 0.4, ..., 1µA NMOS 2/0.18, V =0.6, 0.8, ..., 1.4V
E B GS
300 800

700
250
600
200
500
I C [µA]

I D [µA]
150 400

300
100
200
50
100

0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5
V [V] V [V]
CE DS

B. Murmann EE214B Winter 2013-14 – Chapter 2 59

Passive Components (1)

Joseph et al., BCTM 2001

B. Murmann EE214B Winter 2013-14 – Chapter 2 60

 Passive Components (2)

Diffusion Resistor MIM Capacitor

B. Murmann EE214B Winter 2013-14 – Chapter 2 61

 Chapter 3
Elementary BJT Amplifier Stages

Boris Murmann
Stanford University
Winter 2013-14

Textbook Section: 8.5

Elementary Amplifier Configurations

MOS

Common Common Common

Source Gate Drain

BJT

Common Common Common

Emitter Base Collector

Transconductance Current Voltage

Stage Buffer Buffer

B. Murmann EE214B Winter 2013-14 – Chapter 3 2

 Widely Used Two-Transistor Circuits

MOS

Cascode Current Differential

Stage Mirror Pair

BJT

B. Murmann EE214B Winter 2013-14 – Chapter 3 3

Common-Emitter Stage

VCC
Vo IB
RL VCC
RS +
Q1 VO+vo
vi ~ –
VI
Vi Vi

DC input bias voltage (VI) biases Q1 in the forward active region

Typically, want VO ≅ VCC/2

Main differences to consider versus common-source stage (MOS)
– Bias point sensitivity
– Finite input resistance (due to rπ)
– Base resistance (rb) sometimes significant

B. Murmann EE214B Winter 2013-14 – Chapter 3 4

 Bias Point Sensitivity

IB IC = βFIB

RS + + R
VI VBE Vo L VCC
– –

Is e qVBE kT

VI − VBE(on) RL
IB ≅ VO = VCC − ICRL = VCC − βFIBRL = VCC − βF
RS
( VI − VBE(on) )
RS

The dependence on βF makes “direct voltage biasing” impractical

How to generate VI so as to control Vo?

Practical configurations are usually based on feedback, replica biasing,
ac coupling or differential pairs

B. Murmann EE214B Winter 2013-14 – Chapter 3 5

Simple Example

VCC = 3V

1kΩ

vO

vI

1kΩ 700Ω

B. Murmann EE214B Winter 2013-14 – Chapter 3 6

 VBE Approximation for First-Order Bias Calculations

2.5

2 10
0

1.5

I C [mA]
I C [mA]

0.5 10
-1

0
0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.6 0.65 0.7 0.75 0.8 0.85 0.9
VBE [V] VBE [V]

For the useful range of unit collector current between 0.162mA, VBE
changes by less than 100mV

We can therefore approximate VBE ≅ const. ≅ 0.8V for bias calculations

B. Murmann EE214B Winter 2013-14 – Chapter 3 7

Simple Example – Hand Analysis and Simulation

Neglecting IB, we have HSpice .op Result:

VB = VCC/2 = 1.5V element 0:q1
model 0:npn214

Assuming VBE = 0.8V, we ib 3.8005u
ic 987.3900u
know that VE = 0.7V VCC = 3V vbe 804.2664m
vce 1.9112

IC ≅ IE = 0.7V/700Ω = 1mA vbc -1.1069
vs -2.5458

gm = IC/VT = 38mS 1kΩ power 1.8902m
betad 259.8058
gm 32.9729m
vO rpi 6.7601k
VB IC rx 25.0000
vI ro 92.2106k
cpi 29.7574f
VE cmu 2.4504f
betaac 222.9016
ft 162.9361g
1kΩ 700Ω

B. Murmann EE214B Winter 2013-14 – Chapter 3 8

 Small-Signal Equivalent Circuit for CE Stage

Ri rb 1 Cµ 2
+ +
vi ~ v1 rπ Cπ gmv1 ro RL CL vo
– –

For hand analysis, we will usually neglect rc and re (from the BJT model)

If significant, rb can be included with Ri, i.e. RS = Ri + rb

Resulting low-frequency gain

 rπ 
A v0 = −  ⋅ gmRLtot RLtot = ro || RL
 RS + rπ 

=1 for MOS

B. Murmann EE214B Winter 2013-14 – Chapter 3 9

Frequency Response

Using nodal analysis, we find

 s
1 − 
v (s) z1 
A v (s) = o = A v0 
v i (s) 1 + b1s + b2s2

b1 = RS Cπ + Cµ (1 + gmRLtot ) + RLtot (CL + Cµ )

b2 = RS RLtot (CπCL + CπCµ + CLCµ )

gm
z1 = +
Cµ

z1 is a feedforward zero in the RHP that can typical be ignored

If Cπ >> Cµ, then
gm gm
z1 = + >> = ωT
Cµ C π + Cµ

B. Murmann EE214B Winter 2013-14 – Chapter 3 10

 Toolkit for Simplification (1)

We typically want a much lower entropy

result for design

The following options are listed in order of
simplicity (and accuracy)

Bandwidth estimate using the Miller
approximation
− Approximate the gain across Cµ as
frequency independent for the
frequency range of interest – must be
checked for validity
− A (slightly optimistic) estimate of the
circuit’s bandwidth is then:
1
ω3dB ≅
RS Cπ + Cµ (1 + gmRLtot )

B. Murmann EE214B Winter 2013-14 – Chapter 3 11

Toolkit for Simplification (2)

Open-circuit time constant (OCT) analysis

− The coefficient b1 can be found by summing all zero value time
constants in the circuit and the corresponding (conservative)
bandwidth estimate is
1 1
ω3dB ≅ =
b1 RS Cπ + Cµ (1 + gmRLtot ) + RLtot (CL + Cµ )
 

If we need to know the location of the non-dominant pole, neither Miller
nor OCT is useful

However, if we know that one of the poles is dominant, we can simplify
using the so-called dominant pole approximation
1 1 1
= ≅
 s  s s s s2
s s2
 1 − 1 −  1 − − + 1 − +
 p1  p2  p1 p2 p1p2 p1 p1p2
1 1 b
Given ⇒ p1 ≅ − , p2 ≅ − 1
1 + b1s + b2s2
b1 b2

B. Murmann EE214B Winter 2013-14 – Chapter 3 12

 Dominant Pole Approximation for the CE Stage

If a dominant pole condition exists, we can therefore write

1 1
p1 ≅ − =−
b1 RS Cπ + Cµ (1 + gmRLtot ) + RLtot (CL + Cµ )

b1 RS Cπ + Cµ (1 + gmRLtot ) + RLtot (CL + Cµ )

p2 ≅ − =−
b2 RS RLtot (CπCL + CπCµ + CLCµ )

If Cµ << Cπ, CL, then

RS Cπ + Cµ gmRLtot  + RLtotCL  1 g C 1 

p2 ≅ − = − + m⋅ µ+ 
RSRLtotCπCL  RLCL CL Cπ RSCπ 

B. Murmann EE214B Winter 2013-14 – Chapter 3 13

Emitter Degeneration

VCC

RL
RS VO+vo
Ro gm
Gm ≅
vi ~ 1 + gmRE
Ri
RE Ro ≅ ro (1 + gmRE )
VI

The degeneration resistor reduces the transconductance and increases

the output resistance of the device (same as in the MOS CS stage)

For the BJT version, RE helps increase the input resistance

B. Murmann EE214B Winter 2013-14 – Chapter 3 14

 Input Resistance Calculation

Can always do a nodal analysis

A more intuitive way to find Ri is via the Miller theorem

ve RE g R
K= ≅ = m E
vb 1
+ RE 1 + gmRE
gm

rπ rπ
Ri = ≅ = rπ (1 + gmRE )
1− K  gmRE 
1− 
 1 + gmRE 

The same “bootstrapping” effect applies to Cπ, we see Cπ/(1+gmRE)

looking into the input
− Assuming K = constant in the frequency range of interest

B. Murmann EE214B Winter 2013-14 – Chapter 3 15

Alternative “Trick” Calculation

Ri ≅ rπ + RE (1 + β ) = rπ + RE (1 + gmrπ ) ≅ rπ (1 + gmRE )

Tricks of this kind are useful for reasoning about low frequency behavior

A more detailed analysis is required when investigating frequency
dependence

B. Murmann EE214B Winter 2013-14 – Chapter 3 16

 Small-Signal Equivalent Circuit for Degenerated CE Stage

RS Cµ

+ +
vi ~ v1 rπ Cπ gmv1 ro RL vo
– –
+
vE RE
–

Deriving the transfer function of this circuit requires solving a 3x3 system
of equations

This is very messy, and so we will just look at an OCT-based bandwidth
estimate to gain some basic insight

B. Murmann EE214B Winter 2013-14 – Chapter 3 17

Useful Expressions

RC + RE
Ro ≅ ro (for β → ∞ )
1 + gmRE
R RC
RB RB + RE
R π ≅ rπ
Ro 1 + gmRE

Rµ = Rleft + Rright + GmRleftRright

R RE
Rleft ≅ RB rπ (1 + gmRE )
Rright ≅ RC
gm
Gm =
1 + gmRE

B. Murmann EE214B Winter 2013-14 – Chapter 3 18

 Bandwidth Estimate for Degenerated CE Stage (1)

RS Cµ

+ +
vi ~ v1 rπ Cπ gmv1 ro RC vo
– –
+
vE (neglect)
RE
–

Rµ = RS rπ (1 + gmRE ) + RC + Gm RS rπ (1 + gmRE )  RC

≅ RS + RC + GmRCRS = RS (1 + A v0 ) + RC

RS + RE RS + RE
R π ≅ rπ ≅
1 + gmRE 1 + gmRE

B. Murmann EE214B Winter 2013-14 – Chapter 3 19

Bandwidth Estimate for Degenerated CE Stage (2)

RE
1+ 1
R
τ = RS (1 + A v0 ) + RC  Cµ + 1 + g RS RSCπ ω−3dB ≅
τ
m E

Compare to the case of RE = 0

τ ≅ RS (1 + A v0 ) + RC  Cµ + RSCπ

Adding RE can help improve the bandwidth, provided that gm > 1/RS
− Note, however, that gm (and hence the power dissipation must be
increased) to maintain the same Av0

Furthermore, it is interesting to consider a special case where gmRE>>1

and the time constant due to Cµ is negligible

 R C  R 
τ ≅ 1 + S  π ω−3dB ≅ ωT /  1 + S  Near ωT for small RS
 RE  gm  RE 

B. Murmann EE214B Winter 2013-14 – Chapter 3 20

 Common-Collector Stage (Emitter Follower)

VCC

RS
Q1
vi ~
VO+vo
VI IB RL CL

Behavior is very similar to MOS common drain stage, except that

– We do not need to worry about backgate effect
– There is finite input resistance due to rπ
– The output resistance depends on RS (in addition to 1/gm)

B. Murmann EE214B Winter 2013-14 – Chapter 3 21

Input and Output Resistance

Input resistance (by inspection)

Ri ≅ rπ (1 + gmRL )

Output resistance (using push-through trick)

1 R 1  RS 
Ro ≅ + S ≅ 1 + 
gm β + 1 gm  rπ 

B. Murmann EE214B Winter 2013-14 – Chapter 3 22

 Low Frequency Voltage Gain

RS vb
vi
vo
Ri ≅ rπ (1 + gmRL ) RL

vo vb vo rπ (1 + gmRL ) gmRL
A v0 = = ≅
vi vi v b rπ (1 + gmRL ) + Rs 1 + gmRL
gmRL
≅ for rπ (1 + gmRL ) >> Rs
1 + gmRL
≅1 for gmRL >> 1 and rπ (1 + gmRL ) >> Rs

B. Murmann EE214B Winter 2013-14 – Chapter 3 23

Common-Base Stage

VCC
io iC β
RL Ai = A i0 = =
ii iE β + 1
VO+vo
io Ro
Neglecting rb, rc, re and rπ, we have

Ri Ro ≅ ro (1 + gmRS )
Ii + ii RS (large) 1  RL  1
Ri ≅ 1+ ≅
gm  ro  gm

Behavior is very similar to MOS common gate stage, except that

– We do not need to worry about backgate effect
– The DC current gain is not exactly unity, due to finite β

B. Murmann EE214B Winter 2013-14 – Chapter 3 24

 Basic BJT Current Mirror

IIN IOUT = IC2

VBE
VT  VCE2 
+ IS2e 1+ 
IC2  VA  IS2  VCE2 VCE1 
Q1 Q2 Vo = VCE2 = VBE
≅ 1 + − 
+ IC1  VCE1  IS1  VA VA 
VT
VBE – IS1e 1+ 
–  VA 

Error due to base current

IC1 IC2  I 
IIN = IC1 + IB1 + IB2 = IC1 + + ≅ IC2  1 + 2 C2  for IS1 = IS2
β β  β 

IOUT 1 2
≅ ≅ 1−
IIN  2 β
1 + β 
 

B. Murmann EE214B Winter 2013-14 – Chapter 3 25

BJT Current Mirror with “Beta Helper”

IIN VCC
IOUT
Q3
+ IC1 IC2 I
IE3 − IE3 = + ≅ 2 C2 assumin g IS1 = IS2
Q1 Q2 VOUT β β β

IE3 2IC2 2IC2  2 

IB3 = − ≅ IIN = IC1 + IB3 ≅ IC1 + ≅ IC2 1 + 
β + 1 β(β + 1) β(β + 1)  β(β + 1) 

IOUT 1 2
≅ ≅ 1−
IIN  2  β2
1+  2 
β +β
 

B. Murmann EE214B Winter 2013-14 – Chapter 3 26

 BJT Current Mirror with Degeneration

IIN IOUT

+ Neglecting base currents

Q1 Q2
VOUT VBE1 + IC1R1 = VBE2 + IC2R2
R1 R2
–

1   IC1   IS2    R1 IOUT R1

IC2 = IC1R1 + VT ln      ≅ IC1 ≅
R2   IC2   IS1    R2 IIN R2

Degeneration brings two benefits

– Increased output resistance
– Reduces sensitivity of mirror ratio to mismatches in IS

However, the minimum VOUT for which Q2 remains forward active is increased

B. Murmann EE214B Winter 2013-14 – Chapter 3 27

BJT Differential Pair

VCC

RC1
Differential Input Voltage
RC2
ܸ௜ௗ = ܸ௜ଵ − ܸ௜ଶ
Vo1 Vo2
IC1 IC2 Differential Collector Current
‫ܫ‬௖ௗ = ‫ܫ‬௖ଵ − ‫ܫ‬௖ଶ
Vi1 Q1 Q2 Vi2
Differential Output Voltage
ܸ௢ௗ = ܸ௢ଵ − ܸ௢ଶ
ITAIL RTAIL

VEE

The following large signal analysis neglects rb, rc, re, finite REE and
assumes that the circuit is perfectly symmetric

B. Murmann EE214B Winter 2013-14 – Chapter 3 28

 Large Signal Analysis

Vbe1 Vbe2
VT VT
Vi1 − Vbe1 + Vbe2 − Vi2 = 0 IC1 ≅ IS1 e IC2 ≅ IS2 e

Vbe1 − Vbe2 Vi1− Vi2 Vid

I VT VT VT
⇒ c1 = e =e =e
Ic2

1 αITAIL αITAIL
ITAIL = − (Ie1+ Ie2) = (Ic1+ Ic2) ⇒ Ic1 = V
Ic2 = V
α − id + id
VT VT
1+ e 1+ e

 
 1 1   Vid 
Icd = Ic1 − Ic2 = αFITAIL  Vid
− V  = αFITAIL tanh  2V 
 −
VT
+ id
  T
1 + e 1 + e VT 

 V 
Vod = IodRL = αITAILRL tanh  id 
 2VT 

B. Murmann EE214B Winter 2013-14 – Chapter 3 29

Plot of Transfer Characteristics

Linear region in Vod vs. Vid characteristic is narrow compared to MOS

– Recall that full steering in a MOS pair occurs for Vid = 2VOV

BJT differential pair is linear only for |Vid| < VT ≅ 26 mV

B. Murmann EE214B Winter 2013-14 – Chapter 3 30

 Emitter Degeneration

Can use emitter degeneration resistors to increase the range of input

voltage over which the transfer characteristic of the pair is linear

For large RE, linear range is approximately equal to ITAILRE

VCC

RC RC

Vo1 Vo2

Vi1 Q1 Q2 Vi2

RE RE

ITAIL

VEE

B. Murmann EE214B Winter 2013-14 – Chapter 3 31

Aside: Translinear Circuits

B. Murmann EE214B Winter 2013-14 – Chapter 3 32


“A translinear circuit is one having all inputs and outputs in the form of
currents and whose primary function arises from the exploitation of the
logarithmic behavior of forward-biased PN junctions arranged in pairs so
as to result in fundamentally exact, temperature independent
transformations in the amplitude domain”

Most basic example:
VBE1 = VBE 2

I  I 
VT ln  i  = VT ln  o 
 Is1   Is 2 
Ii I
= o
Is1 Is 2

Is 2
Io = Ii
Is1

B. Murmann EE214B Winter 2013-14 – Chapter 3 33

Square-Root Circuit

VBE1 + VBE 2 = VBE 3 + VBE 4

I   I  I  I 
VT ln  B  + VT ln  i  = VT ln  o  + VT ln  o 
 Is1   Is 2   Is 3   Is 4 
IB Ii I I
= o o
Is1 Is 2 Is 3 Is 4

Is 3 Is 4
Io = Ii IB
Is1 Is 2

B. Murmann EE214B Winter 2013-14 – Chapter 3 34

 Squaring Circuit

VBE1 + VBE 5 + VBE 2 = VBE 3 + VBE 4 + VBE 6

IB1 Ii Ii I I I
= B2 B2 o
Is1 Is 5 Is 2 Is 3 Is 4 Is 6

IB1 Is 3 Is 4 Is 6
Io = Ii2
IB2 2 Is1 Is 5 Is 2

Many more examples exist

It is possible, but often not practical, to play similar tricks with MOSFETs
– Key issues: offset voltages, deviation from idealized I-V law

B. Murmann EE214B Winter 2013-14 – Chapter 3 35

 Chapter 4
MOS Transistor Modeling

Boris Murmann
Stanford University
Winter 2013-14

Textbook Sections: 1.4, 1.5

Outline

Review of square-law model

Inspection of EE214B MOSFETs (0.18µm)

Analysis of relevant effects
– Weak inversion
– Short channel effects

B. Murmann EE214B Winter 2013-14 – Chapter 4 2

 Basic MOSFET Operation (NMOS)

How to calculate the drain current (ID) current as a function of VGS, VDS?

B. Murmann EE214B Winter 2013-14 – Chapter 4 3

Simplifying Assumptions

1) Current is controlled by the mobile charge in the channel

2) Gradual channel approximation - the vertical field sets channel charge, so
we can approximate the mobile charge through the voltage difference
between the gate and the channel
3) The carrier velocity is proportional to the lateral field (ν = µE). This is
equivalent to Ohm's law: velocity (current) is proportional to E-field
(voltage)

B. Murmann EE214B Winter 2013-14 – Chapter 4 4

 Derivation of Square-Law Characteristics

Qn (y) = Cox [ VGS − V(y) − Vt ]

ID = Qn ⋅ v ⋅ W

v = µ ⋅E

ID = Cox [ VGS − V(y) − Vt ] ⋅ µ ⋅ E ⋅ W

W VDS 
ID = µCox ( VGS − Vt ) −  ⋅ VDS
L  2 

B. Murmann EE214B Winter 2013-14 – Chapter 4 5

Drain Current Saturation and Channel Length Modulation

S D

VDS = 0
Qn (y) = Cox [ VGS − V(y) − Vt ]
n+ n+
G

Channel pinch-off occurs for

S D
VDS ≥ VGS–Vt and the drain
0 < VDS < VGS - VTn current saturates
n+ n+

G

The saturation current has
Qn(L) = 0
S D
some dependence on VDS due
to channel length modulation
VDS = VGS - VTn
n+ n+
G
Qn(L- L) = 0 1 W
S D
ID = µCox (VGS − Vt )2 (1 + λVds )
2 L
VDS > VGS - VTn
n+ n+

“Lambda Model”
L

B. Murmann EE214B Winter 2013-14 – Chapter 4 6

 Small-Signal Model

dID W 2I
gm = = µCox VOV (1 + λVDS ) = D VOV = VGS − Vt
dVGS L VOV
dID 1 W λID
go = = µCox VOV 2 ⋅ λ = ≅ λID
dVDS 2 L 1 + λVDS
dID gm γ
gmb = =
dVBS 2 2φ f + VSB

B. Murmann EE214B Winter 2013-14 – Chapter 4 7

Capacitances

Intrinsic

Cgg = Cgs + Cgb + Cgd Cdd = Cdb + Cgd

B. Murmann EE214B Winter 2013-14 – Chapter 4 8

 Capacitances

Text, p. 31

AD ⋅ CJ PD ⋅ CJSW
Cdb = MJ
+ MJSW
AD = WLdiff
 VDB   VDB 
 1 + PB   1 + PB  PD = W + 2Ldiff
   

B. Murmann EE214B Winter 2013-14 – Chapter 4 9

Well Capacitance (PMOS)

B. Murmann EE214B Winter 2013-14 – Chapter 4 10

 Example
0.18um
0.64um 0.64um

10/0.18

10um

0.5um 0.3um

Area = 11um x 3.4um = 37.4um2

* HSpice Netlist

* d g s b
mp1 0 in out out pmos214 L=0.18um W=10um
d1 0 out dwell 37.4p

B. Murmann EE214B Winter 2013-14 – Chapter 4 11

Gate Capacitance Summary

Subthreshold Triode Saturation

Cgs Col ½ WLCox+ Col 2/ WLCox + Col

3

Cgd Col ½ WLCox+Col Col

−1
 1 1 
Cgb  +  0 0
 C js WLCox 

Col = WC'ol
“Overlap Capacitance”

B. Murmann EE214B Winter 2013-14 – Chapter 4 12

 Aside: “Overlap” Capacitance of a 28nm MOSFET

Chipworks

For the most recent generation of MOS transistors, the overlap and
fringe capacitances from gate to drain/source are about as large as the
intrinsic gate capacitance!

B. Murmann EE214B Winter 2013-14 – Chapter 4 13

Capacitance Parameters for EE214B Technology

EE 214B Technology (0.18µm)

PARAMETER
NMOS PMOS

Cox 8.42 fF/µm2 8.42 fF/µm2

C’ol 0.491 fF/µm 0.657 fF/µm

CJ 0.965 fF/µm2 1.19 fF/µm2

CJSW 0.233 fF/µm 0.192 fF/µm
—
CJwell 0.2 fF/µm2
PB 0.8 V 0.8 V
MJ 0.38 0.40
MJSW 0.13 0.33
LDIF 0.64 µm 0.64 µm

B. Murmann EE214B Winter 2013-14 – Chapter 4 14

 What are µCox (“KP”) and λ (“LAMBDA”) for our Technology?

.MODEL nmos214 nmos

+acm = 3 hdif = 0.32e-6 LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ
+K1
= 1E-7
= 0.5916053
NCH
K2
= 2.3549E17
= 3.225139E-3
VTH0
K3
= 0.3618397
= 1E-3

The HSpice model for an NMOS
+K3B
+DVT0W
= 2.3938862
= 0
W0
DVT1W
= 1E-7
= 0
NLX
DVT2W
= 1.776268E-7
= 0
device in our technology is shown
+DVT0
+U0
= 1.3127368
= 256.74093
DVT1
UA
= 0.3876801
= -1.585658E-9
DVT2
UB
= 0.0238708
= 2.528203E-18
to the left
+UC = 5.182125E-11 VSAT = 1.003268E5 A0 = 1.981392
+AGS
+KETA
= 0.4347252
= -9.888408E-3
B0
A1
= 4.989266E-7
= 6.164533E-4
B1
A2
= 5E-6
= 0.9388917

This is a 110-parameter BSIM3v3
+RDSW
+WR
= 128.705483
= 1
PRWG
WINT
= 0.5
= 0
PRWB
LINT
= -0.2
= 1.617316E-8
model
+XL
+DWB
= 0
= 9.111767E-9
XW
VOFF
= -1E-8
= -0.0854824
DWG = -5.383413E-9
NFACTOR = 2.2420572
– More recent models may
+CIT
+CDSCB
= 0
= 0
CDSC
ETA0
= 2.4E-4
= 2.981159E-3
CDSCD
ETAB
= 0
= 9.289544E-6
require even more parameters
+DSUB = 0.0159753
+PDIBLC2 = 2.543351E-3
PCLM = 0.7245546
PDIBLCB = -0.1
PDIBLC1 = 0.1568183
DROUT = 0.7445011
(e.g. PSP, BSIM6)
+PSCBE1
+DELTA
= 8E10
= 0.01
PSCBE2
RSH
= 1.876443E-9
= 6.6
PVAG
MOBMOD
= 7.200284E-3
= 1
– KP and LAMBDA are nowhere
+PRT
+KT1L
= 0
= 0
UTE
KT2
= -1.5
= 0.022
KT1
UA1
= -0.11
= 4.31E-9
to be found
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL
+WWN
= 0
= 1
WLN
WWL
= 1
= 0
WW
LL
= 0
= 0

It turns out that the I-V
+LLN
+LWL
= 1
= 0
LW
CAPMOD
= 0
= 2
LWN
XPART
= 1
= 1
characteristics of a modern
+CGDO
+CJ
= 4.91E-10
= 9.652028E-4
CGSO
PB
= 4.91E-10
= 0.8
CGBO
MJ
= 1E-12
= 0.3836899
MOSFET cannot be accurately
+CJSW
+CJSWG
= 2.326465E-10
= 3.3E-10
PBSW
PBSWG
= 0.8
= 0.8
MJSW
MJSWG
= 0.1253131
= 0.1253131
described by the square law
+CF = 0 PVTH0 = -7.714081E-4 PRDSW = -2.5827257
+PK2 = 9.619963E-4 WKETA = -1.060423E-4 LKETA = -5.373522E-3
+PU0 = 4.5760891 PUA = 1.469028E-14 PUB = 1.783193E-23
+PVSAT = 1.19774E3 PETA0 = 9.968409E-5 PKETA = -2.51194E-3
+nlev = 3 kf = 0.5e-25

B. Murmann EE214B Winter 2013-14 – Chapter 4 15

Simulation (NMOS, 5/0.18µm, VDS=1.8V)

3.5 2

3 Square Law

2.5 1.5
SQRT(I D [mA])
ID [mA]

2
1
1.5

1
0.5
0.5

0 0
0 0.5 1 1.5 0 0.5 1 1.5
VGS [V] VGS [V]

Two observations
– The transistor does not abruptly turn off at some Vt
– The current is not perfectly quadratic in (VGS–Vt)

B. Murmann EE214B Winter 2013-14 – Chapter 4 16

 Additional Issues (1)

40

NMOS214
30 Square Law (2ID/VOV)
BJT (q/kT)
gm/ID [S/A]

20

10

0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VGS [V]

The square law fails miserably at predicting gm/ID for low VGS

B. Murmann EE214B Winter 2013-14 – Chapter 4 17

Additional Issues (2)

0.2 0.48

0.19 0.46
ID⋅L [mA⋅µm]

0.18 0.44
Vt [V]

0.17 0.42

0.16 0.4

0.15 0.38
0.2 0.4 0.6 0.8 1 0.2 0.4 0.6 0.8 1
L [µm] L [µm]

The current does not scale perfectly with 1/L (ID⋅L ≠ const.)

The threshold voltage of the device depends on the channel length

B. Murmann EE214B Winter 2013-14 – Chapter 4 18

 Currents on a Log Scale

0
10
NMOS214
Square Law
-2
ID, IC [mA] 10 NPN214
~90mV/decade

-4 ~60mV/decade
10

-6
10

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

VGS, VBE [V]

What is Vt, anyway? The device does not turn off at all, but really
approaches an exponential IV law for low VGS

What determines the current at low VGS?

B. Murmann EE214B Winter 2013-14 – Chapter 4 19

Definition of Vt

Vt is (roughly speaking) defined as the VGS at which the number of

electrons at the surface equals the number of doping atoms

Seems arbitrary, but makes sense in terms of surface charge control
– This is the point where the surface becomes inverted (no more holes
to fill) and the relationship between mobile charge and gate voltage
becomes linear, Qn ∝ Cox(VGS-Vt)
– Exactly what is assumed in the square law model

B. Murmann EE214B Winter 2013-14 – Chapter 4 20

 Weak Inversion

Before inversion occurs, the electrostatic field from the gate forward-
biases the source-side pn junction at the surface

Physics governed by the “gated diode” model

Potential at this point is higher than body potential  forward bias

Cox
Cjs

D.L. Pulfrey, Understanding Modern Transistors and Diodes,

Cambridge University Press, 2010.

B. Murmann EE214B Winter 2013-14 – Chapter 4 21

Resulting Diffusion Current

టೞ టೞ ି௏ವೄ

௣ 0 =
௣଴  ௏೅
௣  =
௣଴  ௏೅

௣ 0 −
௣ 
஽ = ௡

ഗೞ ೇ
ଵ ି ವೄ
஽ = ௅ ௡
௣଴  ೇ೅ (1 −  ೇ೅
)

The current grows exponentially with ψs

The current becomes independent of VDS for VDS > 3VT (~78mV)

B. Murmann EE214B Winter 2013-14 – Chapter 4 22

 Capacitive Divider

௦ ௢௫ 1
= =
ீௌ ௝௦ + ௢௫

n is called “subthreshold factor” or “nonideality factor”

n ≅ 1.45 for an NMOS device in the EE214B technology

After including this relationship between ψs and VGS and after a few
additional manipulations, the final expression for the drain current
becomes
ೇಸೄ షೇ೟ ೇ
ௐ ି ೇವೄ
஽ = ஽଴  ೙ೇ೅ (1 −  ೅ )
௅

where IDO depends on technology (ID0 ≅ 0.43µA for an NMOS device in

EE214B technology)

B. Murmann EE214B Winter 2013-14 – Chapter 4 23

Combining the Weak Inversion Expression and Square Law

0
10

NMOS214
-2 Weak Inversion
10
Square Law
ID [mA]

-4
10

-6
10

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

VGS [V]

Two remaining problems
– The weak inversion expression and square law are disconnected
– We still do not know what causes the discrepancies at high VGS

B. Murmann EE214B Winter 2013-14 – Chapter 4 24

 Gm/ID

30
NMOS214
25 Weak Inversion
Square Law
20
ID [mA]

15

10

0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VGS [V]

We now have a better idea now about the maximum possible gm/ID, but
this does not help in the transistor region between the two IV laws

B. Murmann EE214B Winter 2013-14 – Chapter 4 25

Moderate Inversion

In the transition region between weak and strong inversion, the drain
current consists of both drift and diffusion currents

One can show that the ratio of drift/diffusion current in moderate
inversion and beyond is approximately (VGS-Vt)/(kT/q)

This means that the square law equation (which assumes 100% drift
current) does not work unless the gate overdrive is several kT/q
– Recall that in EE214A, you used the square law model only for
VGS-Vt > 150mV ≅ 6 kT/q

Is there a simple expression that works for all three regions (weak,
moderate and strong inversion)?

The so-called EKV model was developed with this intent
– C. Enz and E. A. Vittoz, Charge-Based MOS Transistor Modeling -
The EKV Model for Low-Power and RF IC Design, Wiley, 2006

B. Murmann EE214B Winter 2013-14 – Chapter 4 26

 Basic EKV Expression in Saturation


஽ = 2
்ଶ ∙ ௢௫ ௦ଶ +
(  ௦ )

஽௥௜௙௧ ஽௜௙௙௨௦௜௢௡

ீௌ − ௧ =
் 2 ௦ − 1 + ln ௦

This is a parametric equation set that cannot be solved directly

Only three parameters: Vt, n, µCoxW/L

qs is the normalized source charge density and typically runs from 10-5
(weak inversion) to 10L100 (strong inversion)

It can be shown that the equation set approaches a square law
expression for qs >>1 and the weak inversion expression for qs <<1

B. Murmann EE214B Winter 2013-14 – Chapter 4 27

Comparison

0
10

-2
10
ID [mA]

-4
10

NMOS214
-6
10 Square Law
Basic EKV
0 0.5 1 1.5
VGS [V]

The basic EKV model provides a proper transition region

A more complex model is needed to iron out the remaining discrepancy at
large VGS (and to include the triode region, channel length modulation, etc.)

B. Murmann EE214B Winter 2013-14 – Chapter 4 28

 Short Channel Effects

The sub-square behavior at large VGS is primarily due to a number of

issues that fall under the category of “short channel effects”

Onset of velocity saturation due to high lateral field

Mobility degradation due to high vertical field

Strong VDS dependence of drain current and output resistance

Threshold voltage depends on channel length and width

Many more issues exist; we will once again only discuss the most
relevant subset

B. Murmann EE214B Winter 2013-14 – Chapter 4 29

Velocity Saturation (1)

In the derivation of the square law model, it is assumed that the carrier
velocity is proportional to the lateral E-field, v=µE

Unfortunately, the speed of carriers in silicon is limited (vscl ≅ 105 m/s)
– At very high fields (high voltage drop across the conductive part of
the channel), the carrier velocity saturates

(approximation)  ≅ µEc = vscl for E >> Ec

µE 
νd (E) ≅  v
E  = scl
1+ for E = Ec
Ec  2

B. Murmann EE214B Winter 2013-14 – Chapter 4 30

 Velocity Saturation (2)

It is important to distinguish the various regions in the above plot

– Low field, the square law equation still hold
– Moderate field, the square law becomes somewhat inaccurate
– Very high field across the conducting channel – the velocity saturates
completely and becomes essentially constant (vscl)

To get some feel for latter two cases, let's first estimate the E field using
simple physics

In saturation, for a transistor with VOV = 200mV, the lateral field across
the conducting part of the channel is

VOV 200mV V
E = e.g. = 1.11⋅ 106
L 0.18µm m

B. Murmann EE214B Winter 2013-14 – Chapter 4 31

Field Estimates

In our 0.18µm technology, we have for an NMOS device

m
105
v s = 6.7 ⋅ 106 V
Ec = scl ≅
µ cm2 m
150
Vs
Therefore
V
1.11⋅ 106
E m
= ≅ 0.16
Ec V
6.7 ⋅ 106
m

This means that for VOV on the order of 200mV, the carrier velocity is
somewhat reduced, but the impairment is relatively small

The situation changes when much larger VOV are applied, as the case in
digital circuits

B. Murmann EE214B Winter 2013-14 – Chapter 4 32

 Short Channel ID Equation

A simple equation that captures the moderate deviation from the long
channel drain current can be written as

1 W 2 1
ID ≅ µCox VOV ⋅
2 L  VOV 
1+ 
 EcL 

V
Minimum-length NMOS: EcL = 6.7 ⋅ 106 ⋅ 0.18µm = 1.2V
m
V
Minimum-length PMOS: EcL = 16.75 ⋅ 106 ⋅ 0.18µm = 3V
m

B. Murmann EE214B Winter 2013-14 – Chapter 4 33

Reality Check
2
NMOS214
Square Law
1.5 Square Law With Velocity Saturation
SQRT(I D [mA])

0.5

0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VGS [V]

This is definitely a step in a good direction, but we still see residual

discrepancies at high VGS and the curvature is also not quite correct

B. Murmann EE214B Winter 2013-14 – Chapter 4 34

 Additional Effect: Mobility Degradation due to Vertical Field

In MOS technology, the oxide thickness has been continuously scaled

down with feature size
– ~6.5nm in 0.35µm, ~4nm in 0.18µm, ~1.8nm in 90nm CMOS

As a result, the vertical electric field in the device has become quite
large and tries to pull the carriers closer to the "dirty" silicon surface
– Imperfections impede movement and thus mobility

This net effect is a bias dependent mobility degradation that can be
incorporated similar to velocity saturation

The following is a possible equation that captures both velocity
saturation and mobility degradation due to the vertical field

1 W 2 1
ID ≅ µCox VOV ⋅ 1 (see text, page 45)
2 L
(1 + [ θVOV ] )
m m

The parameters m and θ are “fudge factors” that allow us to fit this
expression to measured data

B. Murmann EE214B Winter 2013-14 – Chapter 4 35

Drain Induced Barrier Lowering (DIBL)

In the square law model, we attributed the ID-VDS dependence (and thus
finite intrinsic gain) primarily to channel length modulation

In a short channel device, it turns out that the intrinsic gain is strongly
affected by another effect called DIBL

In essence, the drain can be viewed as an additional gate that
modulates the inversion charge

CLM DIBL SCBE

SCBE = substrate
current induced body effect

(Typically irrelevant at low

supply voltages)

[BSIM3 manual]

B. Murmann EE214B Winter 2013-14 – Chapter 4 36

 “Short Channel Effect (SCE)”

DIBL

Vt reduces for shorter L

B. Murmann EE214B Winter 2013-14 – Chapter 4 37

“Reverse Short Channel Effect (RSCE)”

To reduce the width of the source/drain depletion regions, modern

processes use pocket implants (“halos”)

The average doping in the channel now increases for shorter L, which
results in higher Vt up to a point where the classic SCE effect takes over

0.42

0.415

0.41

0.405
RSCE
Vt [V]

0.4
SCE
0.395

0.39

0.385 [BSIM3 manual]

0.38
0.1 0.15 0.2 0.25 0.3
L [um]

B. Murmann EE214B Winter 2013-14 – Chapter 4 38

 Chapter 5
gm/ID-Based Design

Boris Murmann
Stanford University
Winter 2013-14

Summary on MOSFET Modeling

Modern MOSFETs are complicated!

The IV-behavior in saturation can be roughly categorized according to
the channel’s inversion level: weak, moderate and strong inversion

The current is due to diffusion in weak inversion and mostly due to drift
in strong inversion; the transition is smooth and complicated

The classic square law model is based on an ideal drift model, and
applies only near the onset of strong inversion
– And even then, the predictions are inaccurate unless short channel
effects are taken into account

The bottom line is that there is no modeling expression that is simple

enough for hand analysis and sufficiently accurate to match real world
device behavior

B. Murmann EE214B Winter 2013-14 – Chapter 5 2

 The Problem

Specifications

Square Law Hand Calculations

Circuit

BSIM or PSP Spice

Results

Since there is a disconnect between actual transistor behavior and the

simple square law model, any square-law driven design optimization will
be far off from Spice results

B. Murmann EE214B Winter 2013-14 – Chapter 5 3

Unfortunate Consequence

In absence of a simple set of equations for hand analysis, many

designers tend to converge toward a “spice monkey” design
methodology
– No hand calculations, iterate in spice until the circuit “somehow”
meets the specifications
– Typically results in sub-optimal designs, uninformed design
decisions, etc.

Our goal
– Maintain a systematic design
methodology in absence of a set of
compact MOSFET equations

Strategy
– Design using look-up tables or charts

[Courtesy Isaac Martinez]

B. Murmann EE214B Winter 2013-14 – Chapter 5 4

 The Solution

Use pre-computed spice data in hand calculations

B. Murmann EE214B Winter 2013-14 – Chapter 5 5

Starting Point: Technology Characterization via DC Sweep

* /usr/class/ee214b/hspice/techchar.sp

.inc '/usr/class/ee214b/hspice/ee214_hspice.sp'
.inc 'techchar_params.sp'
.param ds = 0.9
.param gs = 0.9

vdsn vdn 0 dc 'ds'

vgsn vgn 0 dc 'gs'
vbsn vbn 0 dc '-subvol'
W/L
mn vdn vgn 0 vbn nmos214 L='length' W='width'

.options dccap post brief accurate nomod

.dc gs 0 'gsmax' 'gsstep' ds 0 'dsmax' 'dsstep' VGS
.probe n_id = par('i(mn)')
.probe n_vt = par('vth(mn)')
.probe n_gm = par('gmo(mn)') -VSB VDS
.probe n_gmb = par('gmbso(mn)')
.probe n_gds = par('gdso(mn)')
.probe n_cgg = par('cggbo(mn)')
.probe n_cgs = par('-cgsbo(mn)')
.probe n_cgd = par('-cgdbo(mn)')
.probe n_cgb = par('cbgbo(mn)')
.probe n_cdd = par('cddbo(mn)')
.probe n_css = par('-cbsbo(mn)-cgsbo(mn)')

B. Murmann EE214B Winter 2013-14 – Chapter 5 6

 Matlab Wrapper
% /usr/class/ee214b/hspice/techchar.m

% HSpice toolbox
addpath('/usr/class/ee214b/matlab/hspice_toolbox')

% Parameters for HSpice runs

VGS_step = 25e-3; VDS_step = 25e-3; VS_step = 0.1;
VGS_max = 1.8; VDS_max = 1.8; VS_max = 1;
VGS = 0:VGS_step:VGS_max; VDS = 0:VDS_step:VDS_max; VS = 0:VS_step:VS_max;
W = 5; L = [(0.18:0.02:0.5) (0.6:0.1:1.0)];

% HSpice simulation loop

for i = 1:length(L)
for j = 1:length(VS)
% write out circuit parameters and run hspice
fid = fopen('techchar_params.sp', 'w');
fprintf(fid,'*** simulation parameters **** %s\n', datestr(now));
fprintf(fid,'.param width = %d\n', W*1e-6);
fprintf(fid,'.param length = %d\n', L(i)*1e-6);
fprintf(fid,'.param subvol = %d\n', VS(j));
fprintf(fid,'.param gsstep = %d\n', VGS_step);
fprintf(fid,'.param dsstep = %d\n', VDS_step);
fprintf(fid,'.param gsmax = %d\n', VGS_max);
fprintf(fid,'.param dsmax = %d\n', VDS_max);
fclose(fid);

system('/usr/class/ee/synopsys/hspice/F-2011.09-SP2/hspice/bin/hspice techchar.sp >!...

techchar.out');
end
end

B. Murmann EE214B Winter 2013-14 – Chapter 5 7

Simulation Data in Matlab

% data stored in /usr/class/ee214b/matlab
>> load 180nch.mat;

>> nch

nch = Four-dimensional arrays

ID: [4-D double]
VT: [4-D double]
GM: [4-D double]
GMB: [4-D double]
஽ , ீௌ , ஽ௌ , ௌ 
GDS: [4-D double]
CGG: [4-D double]
CGS: [4-D double] ௧ , ீௌ , ஽ௌ , ௌ 
CGD: [4-D double]
CGB: [4-D double]
CDD: [4-D double]
௠ , ீௌ , ஽ௌ , ௌ 
CSS: [4-D double]
VGS:
VDS:
[73x1 double]
[73x1 double]
…
VS: [11x1 double]
L: [22x1 double]
W: 5

>> size(nch.ID)

ans =
22 73 73 11

B. Murmann EE214B Winter 2013-14 – Chapter 5 8

 Lookup Function (For Convenience)

>> lookup(nch, 'ID', 'VGS', 0.5, 'VDS', 0.5)

ans =
8.4181e-006

>> help lookup

The function "lookup" extracts a desired subset from the 4-dimensional

simulation data. The function interpolates when the requested points lie off
the simulation grid.

There are three basic usage modes:

(1) Simple lookup of parameters at given (L, VGS, VDS, VS)
(2) Lookup of arbitrary ratios of parameters, e.g. GM_ID, GM_CGG at given
(L, VGS, VDS, VS)
(3) Cross-lookup of one ratio against another, e.g. GM_CGG for some GM_ID

In usage scenarios (1) and (2) the input parameters (L, VGS, VDS, VS) can be
listed in any order and default to the following values when not specified:

L = min(data.L); (minimum length used in simulation)

VGS = data.VGS; (VGS vector used during simulation)
VDS = max(data.VDS)/2; (VDD/2)
VS = 0;

B. Murmann EE214B Winter 2013-14 – Chapter 5 9

Key Question

How can we use all this data for systematic design?

Many options exist

– And you can invent your own, if you like

Method taught in EE214B

– Look at the transistor in terms of width-independent figures of merit
that are intimately linked to design specification (rather than some
physical modeling parameters that do not directly relate to circuit
specs)
– Think about the design tradeoffs in terms of the MOSFET’s inversion
level, using gm/ID as a proxy

B. Murmann EE214B Winter 2013-14 – Chapter 5 10

 Figures of Merit for Design

Square Law

Transconductance efficiency
– Want large gm, for as little current
gm 2
=
as possible ID VOV

Transit frequency gm 3 µVOV

≅
– Want large gm, without large Cgg Cgg 2 L2

Intrinsic gain gm 2
– Want large gm, but no go ≅
go λVOV

B. Murmann EE214B Winter 2013-14 – Chapter 5 11

Design Tradeoff: gm/ID and fT

40

fT
30 Moderate Inversion
gm/ID [S/A], f T [GHz]

gm/ID
20
Weak Inversion Strong Inversion

10

0
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]

Weak inversion: Large gm/ID (>20 S/A), but small fT

Strong inversion: Small gm/ID (<10 S/A), but large fT

B. Murmann EE214B Winter 2013-14 – Chapter 5 12

 Product of gm/ID and fT

250

200
gm/ID⋅f T [S/A⋅GHz]
150 Moderate Inversion

100

50
Weak Inversion Strong Inversion

0
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VOV [V]

Interestingly, the product of gm/ID and fT peaks in moderate inversion

Operating the transistor in moderate inversion is optimal when we value
speed and power efficiency equally
– Not always the case

B. Murmann EE214B Winter 2013-14 – Chapter 5 13

Design in a Nutshell

ID

gm/ID

Choose the inversion level according to the proper tradeoff between

speed (fT) and efficiency (gm/ID) for the given circuit

The inversion level is fully determined by the gate overdrive VOV
– But, VOV is not a very interesting parameter outside the square law
framework; not much can be computed from VOV

B. Murmann EE214B Winter 2013-14 – Chapter 5 14

 Eliminating VOV

The inversion level is also fully defined once we pick gm/ID, so there is no
need to know VOV

ID 40

30

f T [GHz]
gm/ID 20

10

fT 0
5 10 15 20 25
gm/ID [S/A]

B. Murmann EE214B Winter 2013-14 – Chapter 5 15

gm/ID-centric Technology Characterization

Tabulate the following parameters for a reasonable range of gm/ID and

channel lengths
– Transit frequency (fT)
– Intrinsic gain (gm/go)

Also tabulate relative estimates of extrinsic capacitances
– Cgd/Cgg and Cdd/Cgg

Note that all of these parameters are (to first order) independent of
device width

In order to compute device widths, we need one more table that links
gm/ID and current density ID/W

B. Murmann EE214B Winter 2013-14 – Chapter 5 16

 Transit Frequency Chart

L=0.18um

L=0.5um

B. Murmann EE214B Winter 2013-14 – Chapter 5 17

Intrinsic Gain Chart

L=0.5um

L=0.18um

B. Murmann EE214B Winter 2013-14 – Chapter 5 18

 Current Density Chart

L=0.18um

L=0.5um

B. Murmann EE214B Winter 2013-14 – Chapter 5 19

VDS Dependence

VDS dependence
is relatively weak

Typically OK to
work with data
generated for
VDD/2

B. Murmann EE214B Winter 2013-14 – Chapter 5 20

 Extrinsic Capacitances (1)

NMOS, L=0.18um
1
Cdd/Cgg
Cgd/Cgg
0.8
Again, usually OK
to work with
0.60
estimates taken at
0.6
VDD/2

0.4
0.24
0.2

0
0 0.5 1 1.5
VDS [V]

B. Murmann EE214B Winter 2013-14 – Chapter 5 21

Extrinsic Capacitances (2)

NMOS, gm /I D=10S/A, VDS=0.9V

0.8
Cgd/Cgg
0.7
Cdd/Cgg
0.6

0.5

0.4

0.3

0.2

0.1

0
0.2 0.25 0.3 0.35 0.4 0.45 0.5
L [µm]

B. Murmann EE214B Winter 2013-14 – Chapter 5 22

 Extrinsic Capacitances (3)

PMOS, gm/I D=10S/A, VDS=0.9V

0.8
Cgd/Cgg
0.7
Cdd/Cgg
0.6

0.5

0.4

0.3

0.2

0.1

0
0.2 0.25 0.3 0.35 0.4 0.45 0.5
L [µm]

B. Murmann EE214B Winter 2013-14 – Chapter 5 23

Generic Design Flow

1) Determine gm (from design objectives)

2) Pick L

Short channel  high fT (high speed)

Long channel  high intrinsic gain
3) Pick gm/ID (or fT)

Large gm/ID  low power, large signal swing (low VDSsat)

Small gm/ID  high fT (high speed)
4) Determine ID (from gm and gm/ID)
5) Determine W (from ID/W)

Many other possibilities exist (depending on circuit specifics, design

constraints and objectives)

B. Murmann EE214B Winter 2013-14 – Chapter 5 24

 How about VDsat?

VDsat tells us how much VGS=0.9V

voltage we need across the 0.6
transistor to operate in VDsat

ID [mA]
VGS=0.8V
saturation 0.4

– “High gain region” VGS=0.7V

0.2

0

It is important to note that 0 0.5 1 1.5
VDsat is not crisply defined VDS [V]
in modern devices 40
– Gradual increase of
gm/gds with VDS 30

gm/gds
20

10

0
0 0.5 1 1.5
VDS [V]

B. Murmann EE214B Winter 2013-14 – Chapter 5 25

Relationship Between VDsat and gm/ID

It turns out that 2/(gm/ID) is a reasonable first-order estimate for VDsat

Square Law Weak Inversion

Need about
VGS − Vt  V
− DS  3VT for
ID = K ( VGS − Vt )
2
ID = ID0 e nVT  1 − e VT 
  saturation
gm = 2K ( VGS − Vt )  
VGS − Vt  V
− DS 
2 I nVT  1 − e VT 
= ( VGS − Vt ) = VDSat gm = D0 e
( gm / ID ) nVT  
 
∴Consistent with the classical 2
= 2nVT ≅ 3VT
first-order relationship ( gm / ID )
∴Corresponds well with the
required minimum VDS

B. Murmann EE214B Winter 2013-14 – Chapter 5 26

 Reality Check

0.6

ID [mA]
0.4

0.2 Computed
2/(gm/ID)
0 values
0 0.5 1
VDS [V]
40

30 The SPICE model data

gm/gds

confirms that 2/(gm/ID) is a

20
good estimate for the
10 minimum reasonable VDS

0
0 0.5 1
VDS [V]

B. Murmann EE214B Winter 2013-14 – Chapter 5 27

Basic Design Example

Given specifications and objectives

– 0.18µm technology
– Low frequency gain = -4
– RL=1k, CL=50fF, Rs=10kΩ
– Maximize bandwidth while
keeping ITAIL ≤ 600µA
• Implies L=Lmin=0.18µm
– Determine device width
– Estimate dominant and non-
dominant pole

B. Murmann EE214B Winter 2013-14 – Chapter 5 28

 Small-Signal Half-Circuit Model

Calculate gm and gm/ID

4 gm 4mS S
A v 0 ≅ gmRL = 4 ⇒ gm = = 4mS = = 13.3
1kΩ ID 300µA A

B. Murmann EE214B Winter 2013-14 – Chapter 5 29

Why can we Neglect ro?

A v0 = gm (RL || ro )
−1
 1 1
= gm  + 
 RL ro 
1 1 1
= +
A v0 gmRL gmro

1 1 1
= +
4 gmRL gmro

Even at L=Lmin= 0.18µm, we have gmro > 30

ro is negligible in this design problem

B. Murmann EE214B Winter 2013-14 – Chapter 5 30

 Zero and Pole Expressions

gm
High frequency zero ωz = >> ωT
(negligible) Cgd

Denominator coefficients b1 = Rs Cgs + Cgd (1 + A v0 )  + RL (CL + Cgd )

b2 = Rs RL (CgsCL + CgsCgd + CLCgd )

(Cdb can be added to CL if significant))

1
Dominant pole ωp1 ≅
b1

b1
Nondominant pole ωp2 ≅
b2

B. Murmann EE214B Winter 2013-14 – Chapter 5 31

Determine Cgg via fT Look-up

L=0.18um
16.9 GHz

B. Murmann EE214B Winter 2013-14 – Chapter 5 32

 Find Capacitances and Plug in

 

܏܏ = = . 
 .


܏‫܌‬

܏‫= ܌‬
= .  ∙ .  = . 

܏܏ ܏܏

‫܌܌‬

‫= ܌܌‬
= .  ∙ .  = . 

܏܏ ܏܏

‫ ܌܌
= ܊܌‬−
܏‫  = ܌‬. 

܏‫ ܏܏
= ܛ‬−
܏‫ = ܌‬. 

‫ܘ‬૚ ≅   ‫ܘ‬૛ ≅ . 



B. Murmann EE214B Winter 2013-14 – Chapter 5 33

Device Sizing

16.1 A/m L=0.18um

B. Murmann EE214B Winter 2013-14 – Chapter 5 34

 A Note on Current Density

Designing with current density charts in a normalized, width-independent

space works because
– Current density and gm/ID are independent of W
• ID/W ~ W/W
• gm/ID ~ W/W
– There is a one-to-one mapping from gm/ID to current density

−2
gm 2 ID 1 1 2 1  1 gm 
Square law: = = µCox VOV = µCox  
ID VOV W 2 L L  2 ID 
gm ID   g 
General case: = f ( VOV ) = g ( VOV ) = g  f −1  m  
ID W  
  ID  

B. Murmann EE214B Winter 2013-14 – Chapter 5 35

Matlab Design Script

% gm/ID design example
clear all; close all;
load 180nch.mat;

% Specs
Av0 = 4; RL = 1e3; CL = 50e-15; Rs = 10e3; ITAIL = 600e-6;

% Component calculations
gm = Av0/RL;
gm_id = gm/(ITAIL/2);
wT = lookup(nch, 'GM_CGG', 'GM_ID', gm_id);
cgd_cgg = lookup(nch, 'CGD_CGG', 'GM_ID', gm_id);
cdd_cgg = lookup(nch, 'CDD_CGG', 'GM_ID', gm_id);
cgg = gm/wT;
cgd = cgd_cgg*cgg;
cdd = cdd_cgg*cgg;
cdb = cdd - cgd;
cgs = cgg - cgd;

% pole calculations
b1 = Rs*(cgs + cgd*(1+Av0))+RL*(CL+cgd);
b2 = Rs*RL*(cgs*CL + cgs*cgd + CL*cgd);
fp1 = 1/2/pi/b1
fp2 = 1/2/pi*b1/b2

% device sizing
id_w = lookup(nch, 'ID_W', 'GM_ID', gm_id);
w = ITAIL/2 / id_w

B. Murmann EE214B Winter 2013-14 – Chapter 5 36

 Circuit For Spice Verification

ID 300µA
Device width W= = = 18.6µm
ID 16.1A / m
W

Simulation circuit

50fF 1kΩ 50fF

+ vod -
+vid/2
18.6/0.18
10kΩ

-vid/2
600 A
1V

B. Murmann EE214B Winter 2013-14 – Chapter 5 37

Circuit Netlist
* gm/id design example

* ee214 device models

.include /usr/class/ee214b/hspice/ee214_hspice.sp

vdd vdd 0 1.8

vic vic 0 1
vid vid 0 ac 1
x1 vid vic vip vim balun
x2 vod voc vop vom balun
rdum vod 0 1gig
it t 0 600u

m1 vop vgp t 0 nmos214 w=18.6u l=0.18u

m2 vom vgm t 0 nmos214 w=18.6u l=0.18u
rsp vip vgp 10k
rsm vim vgm 10k
rlp vop vdd 1k
rlm vom vdd 1k
clp vop 0 50f
clm vom 0 50f

.op
.ac dec 100 1e6 1000e9

.pz v(vod) vid

.option post brief accurate

.end

B. Murmann EE214B Winter 2013-14 – Chapter 5 38

 Aside: Ideal Balun

xfmr .subckt balun vdm vcm vp vm

e1 vp vcm transformer vdm 0 2
e2 vcm vm transformer vdm 0 2

xfmr
= .ends balun

Useful for separating CM and DM signal components

Bi-directional, preserves port impedance

Uses ideal, inductorless transformers that work down to DC

Not available in all simulators

B. Murmann EE214B Winter 2013-14 – Chapter 5 39

Simulated DC Operating Point

element 0:m1 0:m2

model 0:nmos214 0:nmos214
region Saturati Saturati
id 300.0000u 300.0000u
vgs 682.4474m 682.4474m Good agreement!
vds 1.1824 1.1824
vbs -317.5526m -317.5526m
vth 564.5037m 564.5037m
vdsat 109.0968m 109.0968m
vod 117.9437m 117.9437m
beta 37.2597m 37.2597m
Design values
gam eff 583.8490m 583.8490m
gm 4.0718m 4.0718m gm = 4 mS
gds 100.9678u 100.9678u
gmb 887.2111u 887.2111u
cdtot 20.8290f 20.8290f
cgtot 37.4805f 37.4805f Cdd = 22.6 fF
cstot 42.2382f 42.2382f Cgg = 37.8 fF
cbtot 31.5173f 31.5173f
cgs 26.7862f 26.7862f
Cgd = 9.0 fF
cgd 8.9672f 8.9672f

B. Murmann EE214B Winter 2013-14 – Chapter 5 40

 HSpice .OP Capacitance Output Variables

HSpice (.OP) Corresponding Small Signal

Model Elements

cdtot 20.8290f cdtot ≡ Cgd + Cdb

cgtot 37.4805f cgtot ≡ Cgs + Cgd + Cgb
cstot 42.2382f cstot ≡ Cgs + Csb
cbtot 31.5173f cbtot ≡ Cgb + Csb+ Cdb
cgs 26.7862f cgs ≡ Cgs
cgd 8.9672f
cgd ≡ Cgd

B. Murmann EE214B Winter 2013-14 – Chapter 5 41

Simulated AC Response

20
214 MHz
0 11.4 dB (3.7)
Magnitude [dB]

-20
5.0 GHz

-40

-60

-80 6 8 10 12
10 10 10 10
Frequency [Hz]

Calculated values: |Av0|=12 dB (4.0), fp1 = 200 MHz, fp2= 5.8 GHz

B. Murmann EE214B Winter 2013-14 – Chapter 5 42

 Plotting HSpice Results in Matlab

clear all;
close all;
addpath('/usr/class/ee214b/matlab/hspice_toolbox');

h = loadsig('gm_id_example1.ac0');
lssig(h)

f = evalsig(h,'HERTZ');
vod = evalsig(h,'vod');
magdb = 20*log10(abs(vod));
av0 = abs(vod(1))
f3dB = interp1(magdb, f, magdb(1)-3, 'spline')

figure(1);
semilogx(f, magdb, 'linewidth', 3);
xlabel('Frequency [Hz]');
ylabel('Magnitude [dB]');
axis([1e6 1e12 -80 20]);
grid;

B. Murmann EE214B Winter 2013-14 – Chapter 5 43

Using .pz Analysis

Netlist statement
.pz v(vod) vid

Output
***************************************************
input = 0:vid output = v(vod)

poles (rad/sec) poles ( hertz)

real imag real imag
-1.35289g 0. -215.319x 0.
-31.6307g 0. -5.03418g 0.

zeros (rad/sec) zeros ( hertz)

real imag real imag
445.734g 0. 70.9407g 0

B. Murmann EE214B Winter 2013-14 – Chapter 5 44

 Observations

The design is essentially right on target!

– Typical discrepancies are no more than 10-20%, due to VDS
dependencies, finite output resistance, etc.

We accomplished this by using pre-computed spice data in the design
process

Even if discrepancies are more significant, there’s always the possibility
to track down the root causes
– Hand calculations are based on parameters that also exist in Spice,
e.g. gm/ID, fT, etc.
– Different from square law calculations using µCox, VOV, etc.
• Based on artificial parameters that do not exist or have no
significance in the spice model

B. Murmann EE214B Winter 2013-14 – Chapter 5 45

Comparison

B. Murmann EE214B Winter 2013-14 – Chapter 5 46

 References

F. Silveira et al. "A gm/ID based methodology for the design of CMOS
analog circuits and its application to the synthesis of a silicon-on-
insulator micropower OTA," IEEE J. Solid-State Circuits, Sep. 1996, pp.
1314-1319.

D. Foty, M. Bucher, D. Binkley, "Re-interpreting the MOS transistor via
the inversion coefficient and the continuum of gms/Id," Proc. Int. Conf. on
Electronics, Circuits and Systems, pp. 1179-1182, Sep. 2002.

B. E. Boser, "Analog Circuit Design with Submicron Transistors," IEEE
SSCS Meeting, Santa Clara Valley, May 19, 2005,
http://www.ewh.ieee.org/r6/scv/ssc/May1905.htm

P. Jespers, The gm/ID Methodology, a sizing tool for low-voltage analog
CMOS Circuits, Springer, 2010.

T. Konishi, K. Inazu, J.G. Lee, M. Natsu, S. Masui, and B. Murmann,
“Optimization of High-Speed and Low-Power Operational
Transconductance Amplifier Using gm/ID Lookup Table Methodology,”
IEICE Trans. Electronics, Vol. E94-C, No.3, Mar. 2011.

B. Murmann EE214B Winter 2013-14 – Chapter 5 47

 Chapter 6
Electronic Noise

Boris Murmann
Stanford University
Winter 2013-14

Textbook Sections: 9.1, 9.2, 9.3, 9.4

Outline

Noise in components
– Resistors
– MOSFETs
– BJTs

Noise analysis in circuits
– Output and input referred noise with ideal voltage drive
– Total integrated noise
– Output and input referred noise with finite source resistance
– Equivalent voltage and current generators for arbitrary source
resistance

B. Murmann EE214B Winter 2013-14 – Chapter 6 2

 Types of Noise

"Man made noise” or interference noise

– Signal coupling
– Substrate coupling
– Finite power supply rejection
– Solutions
• Fully differential circuits
• Layout techniques

"Electronic noise" or "device noise" (focus of this discussion)
– Fundamental
• E.g. "thermal noise" caused by random motion of carriers
– Technology related
• "Flicker noise" caused by material defects and "roughness"

B. Murmann EE214B Winter 2013-14 – Chapter 6 3

Significance of Electronic Noise (1)

Signal-to-Noise Ratio

2
Psignal Vsignal
SNR = ∝ 2
Pnoise Vnoise

B. Murmann EE214B Winter 2013-14 – Chapter 6 4

 Significance of Electronic Noise (2)

The "fidelity" of electronic systems is often determined by their SNR

– Examples
• Audio systems
• Imagers, cameras
• Wireless and wireline transceivers

Electronic noise directly trades with power dissipation and speed

Noise has become increasingly important in modern technologies with
reduced supply voltages
– SNR ~ Vsignal2/Vnoise2 ~ (αVDD)2/Vnoise2

Topics
− How to model noise of circuit components
− How to calculate/simulate the noise performance of a complete circuit
• In which circuits and applications does thermal noise matter?

B. Murmann EE214B Winter 2013-14 – Chapter 6 5

Ideal Resistor

i(t)

1V/1kΩ

Constant current, independent of time

Non-physical
– In a physical resistor, carriers "randomly" collide with lattice atoms,
giving rise to small current variations over time

B. Murmann EE214B Winter 2013-14 – Chapter 6 6

 Physical Resistor

i(t)

1V/1kΩ

"Thermal Noise" or "Johnson Noise"

– J.B. Johnson, "Thermal Agitation of Electricity in Conductors," Phys.
Rev., pp. 97-109, July 1928

Can model random current component using a noise current source in(t)

B. Murmann EE214B Winter 2013-14 – Chapter 6 7

Example Voltage Noise Waveform

Text, p. 364

B. Murmann EE214B Winter 2013-14 – Chapter 6 8

 Properties of Thermal Noise

Present in any conductor

Independent of DC current flow

Instantaneous noise value is unpredictable since it is a result of a large
number of random, superimposed collisions with relaxation time
constant τ0 ≅ 0.17ps
– Consequences:
• Gaussian amplitude distribution
• Knowing in(t) does not help predict in(t+∆t), unless ∆t is on the
order of 0.17ps (cannot sample signals this fast)
• The power generated by thermal noise is spread up to very high
frequencies (1/τ0 ≅ 6,000Grad/s)

The only predictable property of thermal noise is its average power!

B. Murmann EE214B Winter 2013-14 – Chapter 6 9

Average Power

For a deterministic current signal with period T, the average power is

T/2
1
Pav = ∫
T − T/2
i2 ( t ) ⋅ R ⋅ dt

This definition can be extended to random signals

Assuming a real, stationary and ergodic random process, we can write
T/2
1
∫ in ( t ) ⋅ R ⋅ dt
2
Pn = lim
T →∞ T
− T /2

For notational convenience, we typically drop R in the above expression

and work with "mean square" currents (or voltages)

T/2
1
in2 = lim ∫ in ( t ) ⋅ dt
2
T →∞ T
− T/2

B. Murmann EE214B Winter 2013-14 – Chapter 6 10

 Thermal Noise Spectrum

The so-called power spectral density (PSD) shows how much power a
signal caries at a particular frequency

In the case of thermal noise, the power is spread uniformly up to very
high frequencies (about 10% drop at 2,000GHz)

PSD(f)

n0

The total average noise power Pn in a particular frequency band is found

by integrating the PSD
f2
Pn = ∫ PSD ( f ) ⋅ df
f1

B. Murmann EE214B Winter 2013-14 – Chapter 6 11

Thermal Noise Power

Nyquist showed that the noise PSD of a resistor is

PSD ( f ) = n0 = 4 ⋅ kT

k is the Boltzmann constant and T is the absolute temperature

4kT = 1.66·10-20 Joules at room temperature

The total average noise power of a resistor in a certain frequency band
is therefore
f2
Pn = ∫ 4kT ⋅ df = 4kT ⋅ ( f2 − f1 ) = 4kT ⋅ ∆f
f1

B. Murmann EE214B Winter 2013-14 – Chapter 6 12

 Equivalent Noise Generators

We can model the noise using either an equivalent voltage or current

generator

Pn 1
v n2 = Pn ⋅ R = 4kT ⋅ R ⋅ ∆f in2 = = 4kT ⋅ ⋅ ∆f
R R

For R = 1kΩ: For R = 1kΩ:

vn2 V2 in2 A2
= 16 ⋅ 10−18 = 16 ⋅ 10−24
∆f Hz ∆f Hz

vn2 in2
= 4nV / Hz = 4pA / Hz
∆f ∆f

∆f = 1MHz ⇒ vn2 = 4µV ∆f = 1MHz ⇒ in2 = 4nA

B. Murmann EE214B Winter 2013-14 – Chapter 6 13

Two Resistors in Series

2
(
v n2 = vn1 − vn2 ) 2
= vn1 2
+ vn2 − 2 ⋅ v n1 ⋅ vn2

Since vn1(t) and vn2(t) are statistically independent, we have

vn2 = vn1
2 2
+ vn2 = 4 ⋅ kT ⋅ (R1 + R2 ) ⋅ ∆f

Always remember to add independent noise sources using mean

squared quantities
– Never add RMS values!

B. Murmann EE214B Winter 2013-14 – Chapter 6 14

 Derivation of Resistor Noise PSD (1)

V Volume of N = n·A⋅L electrons

A = cross section
L = length
n = electron density
vi = velocity of individual e- in x-direction

∑

 

[C. Enz, EPFL]
∙ ∙∙


PSD of V is equal to Fourier transform 

      ೔
of autocorrelation function

Model for autocorrelation ೔  ೔ 0  | |/ బ

τ0 is the relaxation time (mean time
2τ
between collisions)
೔  ೔ 0 ∙ ≅ ೔ 0 ∙ 2τ
1  2τ 

B. Murmann EE214B Winter 2013-14 – Chapter 6 15

Derivation of Resistor Noise PSD (2)

Equipartition theorem: every energy 1  

storage element has an average noise 
 = 
 = ೔ (0) =
2 2 
of kT/2

 
Intermediate result for the PSD of V
 =  ∙ 2


Resistance expression = = =
    
=
   
Carrier mobility =


Resulting two-sided PSD

 = 2
(positive and negative frequencies)

Single sided PSD

 = 4

B. Murmann EE214B Winter 2013-14 – Chapter 6 16

 MOSFET Thermal Noise (1)

The noise of a MOSFET operating in the triode region is approximately

equal to that of a resistor

In the saturation region, the thermal noise of a MOSFET can be
modeled using a drain current source with spectral density

i2d = 4kT ⋅ γ ⋅ gm ⋅ ∆f

For an idealized long channel MOSFET, it can be shown that γ=2/3

For the past 10-15 years, researchers have been debating the value of γ
in short channels

Preliminary (wrong) results had suggested that in short channels γ can
be as high as 5 due to “hot carrier” effects

B. Murmann EE214B Winter 2013-14 – Chapter 6 17

MOSFET Thermal Noise (2)

[Scholten, 2003]

At moderate gate bias in strong inversion, the γ values for short-channel

MOSFETS are slightly larger than 2/3
– A. J. Scholten et al., "Noise modeling for RF CMOS circuit simulation," IEEE
Trans. Electron Devices, pp. 618-632, Mar. 2003.
– R. P. Jindal, "Compact Noise Models for MOSFETs," IEEE Trans. Electron
Devices, pp. 2051-2061, Sep. 2006.

B. Murmann EE214B Winter 2013-14 – Chapter 6 18

 MOSFET Thermal Noise (3)

Measured γ
relative to 2/3

G.D.J. Smit, A.J. Scholten, R.M.T. Pijper, R. van Langevelde, L.F. Tiemeijer, and
D.B.M. Klaassen, "Experimental Demonstration and Modeling of Excess RF
Noise in Sub-100-nm CMOS Technologies," IEEE Electron Device Letters,
vol.31, no.8, pp. 884-886, Aug. 2010.

B. Murmann EE214B Winter 2013-14 – Chapter 6 19

Thermal Noise in EE214B MOSFET Devices

γ ≅ 0.85
γ ≅ 0.7

Parameter γ depends on biasing conditions, but is roughly constant within

a reasonable range of gm/ID used for analog design

The EE214B HSpice models are inaccurate in the weak inversion region

B. Murmann EE214B Winter 2013-14 – Chapter 6 20

 Spice Simulation (1)

* EE214B MOS device noise simulation

vd dd 0 0.9
vm dd d 0
vg g 0 dc 0.7 ac 1 0.9V
mn1 d g 0 0 nmos214 L=0.18u W=10u dd
h1 c 0 ccvs vm 1 c
0V
d
.op Current Controlled
.ac dec 100 10k 1gig Voltage Source
1V/A
.noise v(c) vg

.options post brief

.inc ‘/usr/class/ee214b/hspice/ee214_hspice.sp'
.end

B. Murmann EE214B Winter 2013-14 – Chapter 6 21

Spice Simulation (2)

(gm=3.14mS)

B. Murmann EE214B Winter 2013-14 – Chapter 6 22

 1/f Noise

Also called "flicker noise" or "pink noise"

– Caused by traps near Si/SiO2 interface that randomly capture and
release carriers, and also by mobility fluctuations
– Occurs in virtually any device, but is most pronounced in MOSFETS

Several (empirical) expressions exist to model flicker noise
– The following expression is used in the EE214B HSpice models

2
2 K f gm ∆f
i1/ f =
Cox W ⋅ L f

For other models, see HSpice manual or

– D. Xie et al., "SPICE Models for Flicker Noise in n-MOSFETs from
Subthreshold to Strong Inversion," IEEE Trans. CAD, Nov. 2000

Kf is strongly dependent on technology; numbers for EE214B:
– Kf,NMOS = 0.5·10-25 V2F
– Kf,PMOS = 0.25·10-25 V2F

B. Murmann EE214B Winter 2013-14 – Chapter 6 23

1/f Noise Corner Frequency

By definition, the frequency at which the flicker noise density equals the
thermal noise density
2
K f gm ∆f
= 4kTγ ⋅ gm ⋅ ∆f
Cox W ⋅ L fco

Kf 1 gm Kf 1 1  gm   ID 
⇒ fco = =  
4kTγ Cox W ⋅ L 4kTγ Cox L  ID   W 

For a given gm/ID the only way to achieve lower fco is to use longer
channel devices
− In the above expression, both 1/L and ID/W are reduced for
increasing L

Example
– EE214B NMOS, L = 0.18µm, gm/ID = 12 S/A , ⇒ID/W = 20 A/m
⇒fco = 560 kHz

In newer technologies, fco can be on the order of 10 MHz

B. Murmann EE214B Winter 2013-14 – Chapter 6 24

 1/f Noise Contribution (1)

Just as with white noise, the total 1/f noise contribution is found by
integrating its power spectral density

f2 2
K f gm ∆f
∫ Cox W ⋅ L f
2
i1/ f,tot =
f
1

2
K f gm  f  K gm2
f 
= ln  2  = f 2.3log  2 
Cox W ⋅ L  f1  Cox W ⋅ L  f1 

The integrated flicker noise depends on the number of frequency

decades
– The frequency range from 1Hz R10Hz contains the same amount
of flicker noise as 1GHz R10GHz
– Note that this is very different from thermal noise

So, does flicker noise matter?
– Let’s look at the total noise integral (flicker and thermal noise)

B. Murmann EE214B Winter 2013-14 – Chapter 6 25

1/f Noise Contribution (2)

In the example shown

on the left, the noise
spectrum is integrated
from 100Hz to 10GHz

The contribution of
the flicker noise is
relatively small, even
though its PSD
dominates at low
frequencies

For circuits with very
large bandwidth
(beyond the 1/f
corner), flicker noise
is insignificant

B. Murmann EE214B Winter 2013-14 – Chapter 6 26

 Lower Integration Limit

Does the flicker noise PSD go to infinity for f → 0?

– See e.g. E. Milotti, "1/f noise: a pedagogical review," available at
http://arxiv.org/abs/physics/0204033

Detailed analysis that considers the 1/f noise as a non-stationary
process shows that the 1/f PSD holds up only to frequencies down to
1/Tob, where Tob is the observation time

Example
– Say we are sensing a signal for a very long time (down to a very low
frequency), e.g. 1 year ≅ 32 Msec, 1/year ≅ 0.03 µHz
– Number of frequency decades in 1/year to 100Hz ≅ 10
– For the example on the previous slide, this means that the integration
band changes from 8 to 8+10=18 decades
– sqrt(18/8) = 1.5 → Only 50% more flicker noise!

B. Murmann EE214B Winter 2013-14 – Chapter 6 27

MOS Model with Noise Generator

Noiseless!
(merely a modeling
resistor that lets us
account for finite
i2d 2
K f gm 1 dID/dVDS)
= 4kT ⋅ γ ⋅ gm ⋅ +
∆f Cox W ⋅ L f

B. Murmann EE214B Winter 2013-14 – Chapter 6 28

 Other MOSFET Noise Sources

Gate noise
– "Shot noise" from gate leakage current
– Noise due to finite resistance of the gate material
– Channel-induced gate noise (coupling via Cgs)
• Relevant only at very high frequencies
• See EE314A

Bulk noise

Source barrier noise in very short channels
– Shot noise from carriers injected across source barrier
– R. Navid, C. Jungemann, T. H. Lee and R. W. Dutton, “High-frequency noise
in nanoscale metal oxide semiconductor field effect transistors,” Journal of
Applied Physics, vol. 101(12) , pp. 101-108, June 15, 2007.
– J. Jeon, J. Lee, J. Kim, C. H. Park, H. Lee, H. Oh, H.-K. Kang, B.-G. Park,
and H. Shin, “The first observation of shot noise characteristics in 10-nm
scale MOSFETs,” in Proc. Symp. VLSI Technol., 2009, pp. 48-49.

B. Murmann EE214B Winter 2013-14 – Chapter 6 29

Shot Noise in a PN Junction

Shot noise is generally associated with the flow of a DC current

In a forward biased diode, shot noise occurs due to randomness in the
carrier transitions across the PN junction (energy barrier)

The power spectral density of this noise is white up to very high
frequencies

The noise can be included in the small-signal model as shown below

i2 = 2qID ⋅ ∆f

Constant
(“white”)
PSD

B. Murmann EE214B Winter 2013-14 – Chapter 6 30

 Shot Noise in a Bipolar Transistor

In a bipolar transistor, the flow of DC current into the base and collector
causes shot noise

The noise can be modeled via equivalent current generators

ic2 = 2qIC ∆f = 2kTgm ∆f

ic2
g 1
ib2 = 2qIB ∆f = 2kT m ∆f = 2kT ∆f ib2
β rπ

The base and collector noise currents are statistically independent as

they arise from separate physical mechanisms
– This will be important in the context of circuit noise calculations

B. Murmann EE214B Winter 2013-14 – Chapter 6 31

BJT Small Signal Model with Noise Generators

Thermal noise due to physical rb:

Collector shot noise: Typically negligible

Base noise components:

B. Murmann EE214B Winter 2013-14 – Chapter 6 32

 Noise in Circuits (1)

Most circuits have more than one relevant noise source

In order to quantify the net effect of all noise sources, we must refer the
noise sources to a single "interesting" port of the circuit
– Usually the output or input

In the following discussion, we will first consider only circuits with a
perfect voltage drive, i.e. no source resistance RS
– Inclusion of finite RS will be discussed later

B. Murmann EE214B Winter 2013-14 – Chapter 6 33

Noise in Circuits (2)

Output referred noise Input referred noise

– Refer noise to output via – Represent total noise via a
individual noise transfer fictitious input source that
functions captures all circuit-internal
– Physical concept, exactly noise sources
what one would measure in – Useful for direct comparison
the lab with input signal

B. Murmann EE214B Winter 2013-14 – Chapter 6 34

 Circuit Example

For simplicity, let’s neglect

– Source impedance
– All capacitances
– Burst and flicker noise
– ro, rb, and rµ

B. Murmann EE214B Winter 2013-14 – Chapter 6 35

Output Referred Noise PSD

2  1 
v out =  4kT ∆f + 2qIC ∆f  ⋅ R2
 R 

(
= 2kT∆f 2R + gmR2 )
 2 
= 2kTgm∆f ⋅ R2  + 1
 gmR 

Shot noise due to base current is absorbed by the input source and does
not contribute to noise at the output

For large gain (gmR), the collector shot noise dominates

B. Murmann EE214B Winter 2013-14 – Chapter 6 36

 Input Referred Noise PSD

From the previous calculation, we know that

2  2 
v out = 2kTgm∆f ⋅ R2  + 1
 gmR 

Since
v out = A v vin

2
v out = A 2v vin
2
where A v = gmR

We can write

 2 
2kTgm∆f ⋅ R2  + 1
2
vin =  gmR  = 2kT 1 ∆f  2 + 1
 
( gmR )2 gm  gmR 

Larger gm translates into lower input

referred voltage noise

B. Murmann EE214B Winter 2013-14 – Chapter 6 37

Spice Simulation

*** EE214B BJT noise example

*** biasing
ib vcc vb 100u gm=3.67mS, R=10k, Av=36.7
q1 vb vb 0 npn214
c1 vb 0 1

*** main circuit

v1 vcc 0 2.5
vi vi vb ac 1
rl vcc vo 10k
q2 vo vi 0 npn214

.op
.ac dec 100 100 10e9
.noise v(vo) vi
.options post brief
.inc ‘ee214_hspice.sp'
.end

B. Murmann EE214B Winter 2013-14 – Chapter 6 38

 Output Referred Noise PSD with Load Capacitance

2
2  1  1
v out =  4kT ∆f + 2qIC ∆f  ⋅ R ||
 R  jω C
2
 1  1
=  4kT ∆f + 2qIC ∆f  ⋅ R2
 R  1 + jω RC
2
 2  1
= 2kTgm∆f ⋅ R2  + 1 ⋅
 gmR  1 + jω RC

Same calculation as before, except that now the noise current drops into
the parallel combination of R and C

Output PSD is shaped by squared magnitude of first order response

B. Murmann EE214B Winter 2013-14 – Chapter 6 39

Input Referred Noise PSD with Load Capacitance

Same calculation as before, except that the voltage gain is now

frequency dependent

2 2
2 v out (ω) 2 1
vin (ω) = where A v ( jω ) = A v (0)
A v ( jω )
2 1 + jω RC

2
 2  1
2kTgm∆f ⋅ R2  + 1 ⋅
=  gmR  1 + jω RC
2
1
A 2v ( 0 )
1 + jω RC

Input referred noise is frequency independent, because the output noise

and gain have the same frequency roll-off

2 1  2 
∴ v in = 2kT ∆f  + 1
gm  gmR 

B. Murmann EE214B Winter 2013-14 – Chapter 6 40

 Spice Simulation

*** EE214B BJT noise example

*** biasing
ib vcc vb 100u
q1 vb vb 0 npn214
gm=3.67mS, R=10k, Av=36.7, C=10pF
c1 vb 0 1

*** main circuit

v1 vcc 0 2.5
vi vi vb ac 1
rl vcc vo 10k
Cl vo 0 10p
q2 vo vi 0 npn214

.op
.ac dec 100 100 10e9
.noise v(vo) vi
.options post brief
.inc 'ee214_hspice.sp'
.end

B. Murmann EE214B Winter 2013-14 – Chapter 6 41

Signal-to-Noise Ratio

Assuming a sinusoidal signal, we can compute the SNR at the output of

the circuit using
1 2
Psignal v̂ out
SNR = =f 2
Pnoise 2 2
v
∫ ∆outf ⋅ df
f 1

Over which bandwidth should we integrate the noise?

Two interesting cases
– The output is measured or observed by a system with finite
bandwidth (e.g. human ear, or another circuit with finite bandwidth)
• Use frequency range of that system as integration limits
• Applies on a case by case basis
– Total integrated noise
• Integrate noise from zero to “infinite” frequency

B. Murmann EE214B Winter 2013-14 – Chapter 6 42

 A Closer Look at The Circuit’s Noise Integral

The noise integral converges

for upper integration limits that
lie beyond the circuit’s pole
frequency

The total integrated noise (from
“0” to “infinity”) is a reasonable
metric to use
– For convenience in
comparing circuits without
making bandwidth
assumptions
– In a circuit where the output
is observed without any
significant band limiting
• E.g. in a sampling circuit
• See EE315A,B

B. Murmann EE214B Winter 2013-14 – Chapter 6 43

Aside: A Cool Trick

1/f tangent

To find out at which frequency
most of the noise rolls in, drop
a 1/f tangent in the log-log PSD
plot (from the top)

The frequency range where the
tangent touches the PSD is the
strongest contributor to the
integrated noise

See text (page 377) for more
info

B. Murmann EE214B Winter 2013-14 – Chapter 6 44

 Total Integrated Noise Calculation

Let us first consider only the noise from the resistor

∞ 2
1
2
v out,tot = ∫ 4kTR ⋅ df
0
1 + j2 π f ⋅ RC

∞
df du
= 4kTR ∫ 2
; ∫ 1 + u2 = tan
−1
u
0 1+ ( 2πfRC )
1
= 4kTR ⋅
4RC
kT
=
C

Interesting result
– The total integrated noise at the output depends only on C (even
though R is generating the noise)

B. Murmann EE214B Winter 2013-14 – Chapter 6 45

Effect of Varying R

Increasing R increases
the noise power spectral
density, but also
decreases the
bandwidth
– R drops out in the
end result

For C=1pF (example to
the right), the total
integrated noise is
approximately 64µVrms

B. Murmann EE214B Winter 2013-14 – Chapter 6 46

 Alternative Derivation

The equipartition theorem says that each degree of freedom (or energy
state) of a system in thermal equilibrium holds an average energy of
kT/2

In our circuit, the quadratic degree of freedom is the energy stored on
the capacitor

1 1
Cv out 2 = kT
2 2
kT
v out 2 =
C

B. Murmann EE214B Winter 2013-14 – Chapter 6 47

Equivalent Noise Bandwidth

The equivalent noise bandwidth is

2 kT 
v out,tot =  defined as the bandwidth of a
C
 brick-wall filter that results in the
2  π same total noise power as the
v out,tot ≜ 4kTR ⋅ fENBW  fENBW = f0
2 filter in question

1 
For a simple RC filter, the
f0 = 
2πRC  equivalent noise bandwidth is π/2
times its 3-dB corner frequency

fENBW
Text, p. 374

B. Murmann EE214B Winter 2013-14 – Chapter 6 48

 Total Integrated Noise Calculation for the Complete Circuit

∞ 2
1
∫( )
2
v out,tot = 4kTR + 2kTgmR2 ⋅ df
0
1 + j2πf ⋅ RC

Was 4kTR in previous analysis

2 kT 4kTR + 2kTgmR2
v out,tot = ⋅
C 4kTR
kT  1 
=  1 + gmR 
C 2 

Taking the BJT’s collector shot noise into account, the total integrated
noise becomes a multiple of kT/C

B. Murmann EE214B Winter 2013-14 – Chapter 6 49

Example SNR Calculation

Assumptions
– Output carries a sinusoid with 1V peak amplitude
– We observe the output without significant band limiting and thus use
the total integrated noise in the SNR expression

1 2
v̂ out
Psignal 2 0.5V 2 0.5V 2
SNR = = = = = 8.59 ⋅ 106
Pnoise kT  1  kT  1  2
1+ g R 1 + 3.67mS ⋅ 10kΩ  ( 763µV )
C  2 m  10pF  2 

(
SNR [ dB] = 10log 8.59 ⋅ 106 = 69.3dB )

Typical system requirements
– Audio: SNR ≅ 100dB
– Video: SNR ≅ 60dB
– Gigabit Ethernet Transceiver: SNR ≅ 35dB

B. Murmann EE214B Winter 2013-14 – Chapter 6 50

 Noise/Power Tradeoff

Assuming that we're already using the maximum available signal swing,
improving the SNR by 6dB means
– Increase C by 4x
– Decrease R by 4x to maintain bandwidth
– Increase gm by 4x to preserve gain
– Increase collector current by 4x

Bottom line
– Improving the SNR in a noise limited circuit by 6dB ("1bit")
QUADRUPLES power dissipation !

B. Murmann EE214B Winter 2013-14 – Chapter 6 51

MDS and DR

Minimum detectable signal (MDS)

– Quantifies the signal level in a circuit that yields SNR=1, i.e. noise
power = signal power

Dynamic range (DR) is defined as

Psignal,max
DR =
MDS

If the noise level in the circuit is independent of the signal level (which is
often, but not always the case), it follows that the DR is equal to the
"peak SNR," i.e. the SNR with the maximum signal applied

B. Murmann EE214B Winter 2013-14 – Chapter 6 52

 Does Thermal Noise Always Matter?

Let’s look at the SNR of an RC circuit with a 1-V sinusoid applied,

considering the total integrated noise (kT/C)

SNR [dB] C [pF]

20 0.00000083
Hard to make such small capacitorsF
40 0.000083
60 0.0083 Designer will be concerned about thermal
80 0.83 noise; component sizes often set by SNR
100 83
120 8300 A difficult battle with thermal noise F
140 830000

Rules of thumb
– Up to SNR ~ 30-40dB, integrated circuits are usually not limited by
thermal noise
– Achieving SNR >100dB is extremely difficult
• Must usually rely on external components, or reduce bandwidth
and remove noise by a succeeding filter
• See e.g. oversampling ADCs in EE315B

B. Murmann EE214B Winter 2013-14 – Chapter 6 53

Example Revisited: More on Input Referred Noise

In our analysis, we showed that the circuit’s noise can be lumped into a
single input referred voltage noise generator

It is important to remember that this result was based on the assumption
of ideal voltage drive

To see why this matters, consider driving the circuit with a current
source  The circuit would appear noiseless at the output!

2 1  2 
v in = 2kT ∆f  + 1
gm  gmR 

B. Murmann EE214B Winter 2013-14 – Chapter 6 54

 How to Properly Deal with Input Referred Noise

Option 1: Best for 99% of what we do in this class

– Compute the input source referred noise for the given (fixed) source
type (voltage or current) and take the given (fixed) source resistance
into account
– The recommended procedure is the same as before
• Refer all noise sources to the output
• Divide by the transfer function from the source to the output

Option 2: What if we do not know the details of the driving network?
– This case occurs only in very specific cases
– Examples
• You are trying to design/sell a general purpose OpAmp
• You are trying to benchmark a transistor outside a specific circuit
– This case requires the use of both input referred current and voltage
generators

B. Murmann EE214B Winter 2013-14 – Chapter 6 55

Example with Finite RS

Neglect rπ, ro and Cµ

for simplicity

v out gmR
H(s) = =−
vs 1 + sRsCπ

2
v out 2  1 
∆f
( )
= 4kTRS + 2qIBRS2 H(s) +  4kT + 2qIC  ⋅ R2
 R 

B. Murmann EE214B Winter 2013-14 – Chapter 6 56

 Source Referred Noise PSD

2
v out 2  1 
∆f
( )
= 4kTRS + 2qIBRS2 H(s) +  4kT + 2qIC  ⋅ R2
 R 
2
v out  1  2
v s2  4kT R + 2qIC  ⋅ R
= ∆f 2 = 4kTRS + 2qIBRS2 +  
∆f H(s) H(s)
2

For low frequencies (|H(s)| ≅ gmR) we obtain

v 2s  1 
= 4kTRS + 2qIBRS2 +  4kT + 2qIC  ⋅ R2
∆f  R 

v 2s  g R2 R 1 
= 4kT  RS + m S + +
∆f  2β ( gmR )2 2gm 


Note that this equation has a minimum for a specific value of gm (and thus IC)

B. Murmann EE214B Winter 2013-14 – Chapter 6 57

Additional Examples

vo g R io gm io g R
Av = = m Gm = = Ai = = m
vi 1 + gmR vi 1 + gmR ii 1 + gmR

Neglecting finite ro, backgate effect and flicker noise for simplicity

B. Murmann EE214B Winter 2013-14 – Chapter 6 58

 Source Follower

2
 
 1  i2d + ir2 2
(
v o2 = i2d + ir2 ) ⋅  = 2 ⋅ Av
 gm + 1  gm
 R
Often negligible

i2d ir2 1  1 
vi2 = 2
+ 2
= 4kT ∆f  γ + 
gm gm gm  gmR 

The noise in a resistively loaded source follower is typically dominated

by the contribution from the transistor

The input referred noise voltage can be approximated by the drain
current noise reflected through the device’s transconductance

B. Murmann EE214B Winter 2013-14 – Chapter 6 59

Degenerated Common Source Stage

gm
io = id + ( ir − id )
1
gm +
R
gmR 1
= ir + id
1 + gmR 1 + gmR

Gm
= ir GmR + id
gm

 i2  i2d 1
io2  d 2 2 2
= 2 + ir R ⋅ Gm vi2 = + ir2R2 = 4kTγ ∆f + 4kTR∆f
 gm  2
gm gm
 

The input referred voltage noise consists of drain current noise, reflected
through gm, plus the resistor’s voltage noise

B. Murmann EE214B Winter 2013-14 – Chapter 6 60

 Common Gate Stage

gmR 1
io = ir + id
1 + gmR 1 + gmR

Ai
= ir A i + id
gmR

Often negligible
 i2  i2d 1  γ 
io2 =  2 d 2 + ir2  ⋅ A i2 ii2 = + ir2 = 4kT ∆f  1 + 
 gmR  2 2
gmR R  gmR 
 

The input referred current noise from the transistor is often negligible (at
low frequencies)

The noise tends to be dominated by the devices providing the source
and drain bias currents (resistors or current sources)

B. Murmann EE214B Winter 2013-14 – Chapter 6 61

Common Gate Stage at High Frequencies

2
1
+ jω C
1 R
ii2 = 4kT ∆f + 4kTγgm ∆f 2
R gm
2
1  ωC 
≅ 4kT ∆f + 4kTγgm ∆f  
R  gm 

The input referred current noise from the transistor can be significant at
high frequencies (near the cutoff frequency of the current transfer)

B. Murmann EE214B Winter 2013-14 – Chapter 6 62

 General Purpose OpAmp

B. Murmann EE214B Winter 2013-14 – Chapter 6 63

Using Equivalent Voltage and Current Noise Generators

Short-circuit both inputs and equate output noise

– This yields vi2

Open-circuit both inputs and equate output noise
– This yields ii2

This representation is valid for “any” source impedance

Must consider correlation between equivalent voltage and current
generator, but often times only one of the two generators matters in the
target application

If both generators matter (and they are correlated), it is usually best
to avoid working with input referred noise representations

B. Murmann EE214B Winter 2013-14 – Chapter 6 64

 Examples

We will illustrate this method for the purpose of carrying out a general
noise performance characterization (and comparison) of MOSFETs and
BJTs

The procedure can be applied in the same way to any other device or
circuit

B. Murmann EE214B Winter 2013-14 – Chapter 6 65

BJT Input Voltage Noise (1)

To find input referred voltage generator, short the input of both circuit
models and equate output noise

Neglecting Cµ, rc and re for simplicity

2
io1 ≅ ic2 + gm (
2 2 2
ib ⋅ rb + vb2 )

2 2 2
io2 ≅ gm vi

2 2 ic2
io1 = io2 ⇒ vi2 ≅ vb2 + 2
+ ib2 ⋅ rb2
gm

B. Murmann EE214B Winter 2013-14 – Chapter 6 66

 BJT Input Voltage Noise (2)

The PSD of the BJT input voltage noise generator is therefore

vi2 2qI
≅ 4kTrb + 2C + 2qIBrb2
∆f gm

2qIC  gm 2 2
rb
≅ 4kTrb + 1 + 
2
gm  β 

2qIC
≅ 4kTrb + 2
gm

 1 
≅ 4kT  rb + 
 2gm 

B. Murmann EE214B Winter 2013-14 – Chapter 6 67

BJT Input Current Noise (1)

To find input referred current generator, open circuit the input of both
circuit models and equate output noise

2 2
io1 = ic2 + gm
2 2
⋅ ib ⋅ z π

2 2 2 2
io2 = gm ⋅ ii ⋅ z π

2 2 ic2
io1 = io2 ⇒ ii2 = ib2 + 2
2
gm zπ

B. Murmann EE214B Winter 2013-14 – Chapter 6 68

 BJT Input Current Noise (2)
1
rπ ⋅
ii2 2qIC jω C π rπ β ( jω )
= 2qIB + where z π = = =
∆f 2
gm zπ
2
rπ +
1 1 + jω rπCπ gm
jω C π

2qIC
= 2qIB + 2
β ( jω )

   
2
 1+  ω  
  ωβ   ω
= 2qIB  1 +    where ωβ =
1
≅− T
 β0  rπCπ β0
 
 
 

The term due to IC is negligible at low frequencies, but becomes
comparable to the base current contribution at
ωT
ωb = ωβ β0 ≅
β0

B. Murmann EE214B Winter 2013-14 – Chapter 6 69

Typical Plot of BJT Input Noise Current PSD

Neglect (for BJT)

B. Murmann EE214B Winter 2013-14 – Chapter 6 70

 MOS Input Voltage Noise

2
io1 = ic2

2 2 2
io2 = gm vi

ic2 vi2 1 Kf 1
vi2 = 2
= 4kTγ +
gm ∆f gm WLCox f

B. Murmann EE214B Winter 2013-14 – Chapter 6 71

MOS Input Current Noise

2
2 1 ω 
io1 = ic2 2
+ gm ⋅ i2g ⋅ ≅ ic2 + ig2 ⋅ T 
ω2Cgs
2
 ω 

2
2 ω 
io2 ≅ ii2 ⋅ T 
 ω 

2 2
 ω  2 ii2  f   2
K f gm 1
ii2 = ig2 +  ic ≅ 2qIG +    4kTγgm + 
ω ∆f f WLCox f 
 T   T  

B. Murmann EE214B Winter 2013-14 – Chapter 6 72

 BJT versus MOS (1)

Noiseless
Transistor

Consider low source impedance  voltage noise will dominate

 v2   1   v2  1 Kf 1
 i  ≅ 4kT  rb +   i  ≅ 4kTγ +
 ∆f   2gm   ∆f  gm WLCox f
BJT MOS

BJT is usually superior

– Need less gm for approximately same noise
– gm/I is higher, making it easier to achieve low noise at a given current
budget

B. Murmann EE214B Winter 2013-14 – Chapter 6 73

BJT versus MOS (2)

Consider high source impedance  current noise will dominate

 i2     i2  2
 f  
IC  K g2 1
 i  ≅ 2q  IB +  i ≅ 2qIG +    4kTγgm + f m 
  f 
 ∆f  β ( jω )  ∆f
2
 MOS  fT   WLCox
BJT 

MOS is usually superior

– Gate leakage current (IG) is typically much smaller than BJT base
current
• Unless the gate oxide becomes very thin, as e.g. in a 45-nm
CMOS process that does not use high-k gate dielectrics

B. Murmann EE214B Winter 2013-14 – Chapter 6 74

 Additional Topics in Noise Analysis

Later in this course: Effect of noise in feedback circuits

Covered in EE314A
– RF-centric metrics
• Noise figure
• Receiver sensitivity
– Phase noise in oscillators

Covered in EE315A,B
– Noise in filters and switched capacitor circuits

Other
– Cyclostationary noise
• Noise in circuits that are driven by a periodic waveform that
modulates the power spectral densities
• E.g. mixers

B. Murmann EE214B Winter 2013-14 – Chapter 6 75

 Chapter 7
Feedback: Introduction

Boris Murmann
Stanford University
Winter 2013-14

Textbook Sections: 5.1, 5.2, 5.3, 5.4

Discrete Feedback Circuits Using General Purpose OpAmps

B. Murmann EE214B Winter 2013-14 – Chapter 7 2

 Properties of General Purpose OpAmps

Low integration density, up to a few OpAmps per package

– Typically no more than a few hundred transistors

Often fabricated in old or exotic fabrication processes
– Purely bipolar process, JFETs, etc.

Common denominator design (rather than optimized for one specific
application)
– Input stage often designed for wide common mode range
– Output stage often designed for heavy loads
– Internally compensated for unity gain stability

Typical structure

Text, p. 243

B. Murmann EE214B Winter 2013-14 – Chapter 7 3

“Mainstream” Integrated Feedback Amplifiers in CMOS SoCs

Example:
Switched Capacitor Gain Stage

S. Abdollahi-Alibeik et al., “A 65nm dual-Band 3-Stream

802.11n MiMo WLAN SoC," ISSCC 2011 Text, p. 594

Example:
Two-Stage Operational
Transconductance Amplifier
(OTA) Text, p. 243

B. Murmann EE214B Winter 2013-14 – Chapter 7 4

 Properties of Integrated Feedback Amplifiers

Optimized for one specific task
– Input stage may not need to handle wide common mode input range
– Output may need to drive only moderate capacitive loads
• Output buffer usually not needed
– Stability must be ensured only for the given feedback network
• The amplifier is not necessarily unity gain stable
– Noise level is adjusted to meet specific target (no overdesign)
OpAmp

OTA
B. Murmann EE214B Winter 2013-14 – Chapter 7 5

Special Purpose Feedback Circuits

Example: TIA

C. Knochenhauer et al., “40 Gbit/s transimpedance amplifier with high linearity range in 0.13 µm SiGe
BiCMOS, Electronics Letters, May 12, 2012.

B. Murmann EE214B Winter 2013-14 – Chapter 7 6

 Special Purpose Feedback Amplifiers

Wide variety of applications

– Voltage regulators
– Transimpedance amplifiers for optical communications
– Transimpedance amplifiers for instrumentation of physics
experiments
– RF power amplifiers (e.g. Cartesian feedback)
– Audio power amplifiers
– 0

Sometimes integrated within a larger SoC, sometimes not
– Depending on whether the goals are compatible with fine line CMOS
(or BiCMOS, if available)

B. Murmann EE214B Winter 2013-14 – Chapter 7 7

Feedback Circuits in EE214B

We will use the transimpedance amplifier example as a driver to

advance your understanding of feedback circuits
– Frequency compensation and strategic pole placement
– Noise analysis in feedback circuits
– Two-port feedback circuit analysis
• An alternative to the return ratio method that you learned in
EE214A

After developing the key tools using the TIA example, we will look into
other examples and further generalizations to broaden your
understanding

EE315A will then continue on this track by looking at “mainstream” OTA
design for filters and sensor interfaces

B. Murmann EE214B Winter 2013-14 – Chapter 7 8

 Review: Idealized Negative Feedback System

+ Sε
Si Σ a So
–
Sfb
f

Assumptions for an ideal feedback system

1. No loading effects
2. Unilateral transmission in both the forward amplifier
and feedback network

So = a ⋅ Sε
Sfb = f ⋅ So ⇒ So = (Si − Sfb ) = a(Si − f ⋅ So )
Sε = Si − Sfb

B. Murmann EE214B Winter 2013-14 – Chapter 7 9

So a
Closed-Loop Gain: = A=
Si 1 + af 1 T
⇒ A=
S f 1+ T
Loop Gain: T = af = fb
Sε

If T >> 1, then
1
A≅ (Also, note that if T << 1, then A ≅ a)
f

For large loop gain, the feedback acts to minimize the error signal
(Sε), thus forcing Sfb to track Si

 a   af 
Sε = Si − f ⋅ So = Si − f ⋅   Si =  1− ⋅S
 1+ af   1+ af  i

Sε T 1 Sfb S  T
∴ = 1− = and = a⋅f ε  =
Si 1+ T 1+ T Si  Si  1+ T

B. Murmann EE214B Winter 2013-14 – Chapter 7 10

 Forward Gain Desensitization

The feedback network is typically a precision passive network with an

insensitive, well-defined transfer function f. The forward amplifier gain is
generally large, but not well controlled.
Feedback acts to reduce not only the gain, but also the fractional gain error
by the factor 1+T

dA d  a  1 d  1 
=   = +a 
da da  1+ af  1+ af da  1+ af 
(1+ af) − af 1 1
= 2
= 2
=
(1+ af) (1+ af) (1+ T)2
For a change δa in a
dA δa
δa = δa =
da (1+ T)2
δA δa  1+ T   1  δa
∴ = =
A (1+ T)2  a   1+ T  a

B. Murmann EE214B Winter 2013-14 – Chapter 7 11

Closed-Loop Impedances

To illustrate the influence of feedback on the input and output impedances of an

amplifier, consider the following voltage-in, voltage-out example
– Include finite input and output impedances in a simple model for the forward
amplifier
– Assume that the feedback network has ideal input and output impedances so
as not to load the forward amplifier

io

vε avε

B. Murmann EE214B Winter 2013-14 – Chapter 7 12

 Input Impedance Output Impedance

vi vo
Zi = Zo =
ii io = 0 io
vi =0

With io = 0 With vi = 0
v o = av ε v ε + fv o = v i = 0
v i = v ε + fv o = (1+ af)v ε v o − av ε 1
= (1+ T)v ε
io =
zo
=
zo
( )
1+ af v o

vε 1 1  1
ii = = v (1+ T)v o
zi  1+ T  i
=
zi zo

vi vo z
Zi = = z i (1 + T) Zo = = o
ii io 1+ T

B. Murmann EE214B Winter 2013-14 – Chapter 7 13

Blackman’s Impedance Formula

1 + T(port shorted)
Zport = Zport ( gain set to zero ) ⋅
1 + T(port open)

A very convenient tool for finding the port impedances of feedback

circuits by inspection

It is common that one of the two loop gains (shorted or open) is zero
– Thus, depending on the configuration, feedback tends to decrease or
increase the port impedance by the loop gain

B. Murmann EE214B Winter 2013-14 – Chapter 7 14

 Negative Feedback and Bandwidth

a0
Example : a(s) =
s
1−
p1

Closed-loop transfer function

a(s) a0 1 1 T0 1
A(s) = = ⋅ = ⋅
1 + a(s)f 1 + a0 f 1 − s f 1 + T0 1 − s

 
p1 (1 + a0 f ) A0 p1 (1 + T0 )

Bandwidth increases by (1+T0)!

– But gain is reduced by the same factor

Product of gain and bandwidth remains constant

B. Murmann EE214B Winter 2013-14 – Chapter 7 15

20 log10 a0
20 log10 |a(jω)|

20 log10 (1+T0)

20 log10 |A(jω)|
20 log10 A0

|p1|
ω3dB = (1+T0)|p1|

Note that at the closed-loop 3-dB frequency ω3dB, we have

a0 f
a( jω3dB ) = A 0 T( jω3dB ) = a( jω3dB ) ⋅ f = A 0 f = ≅1
1 + a0 f

Thus, for a single pole system, the closed-loop 3-dB frequency

corresponds to the unity gain frequency (gain-bandwidth
product) of the of the loop
B. Murmann EE214B Winter 2013-14 – Chapter 7 16
 |T(jω)|
Asymptote 1/jωu

G2

G1

ωu=G1BW1=G2BW2

1 ω
BW1 BW2

The DC loop gain is irrelevant for computing the bandwidth of a

feedback amplifier; all that matters is the loop’s unity gain frequency

Consequently, we will often model the dominant pole of the loop
response using an integrator approximation (for convenience)
ωu
1 T(s) 1 s =1 1 ⇒ω ≅ω
A(s) = ≅ 3dB u
f 1 + T(s) f ω f 1+ s
1+ u
s ωu
B. Murmann EE214B Winter 2013-14 – Chapter 7 17

Instability

At a frequency where the phase shift around the loop of a feedback

amplifier reaches ±180o the feedback becomes positive. In that case,
if the loop gain is greater than unity, the circuit is unstable.

For a “single-pole” forward path amplifier stability is assured because

the maximum phase shift is 90o. However, if a(s), or in general T(s),
has multiple poles, the amount of loop gain that can be used is
constrained.

The stability of a feedback amplifier can be assessed from:

– Nyquist diagram (polar plot of loop gain with frequency as a parameter)

– Bode plot (plot of loop gain and phase as functions of frequency)

– Locus of poles (root locus) of A(s) in the s-plane

B. Murmann EE214B Winter 2013-14 – Chapter 7 18

 Bode Stability Criterion

A feedback system is unstable when |T(jω)| > 1 at the frequency where

Phase[T(jω)] = -180°

Phase margin
– Defined at the frequency where |T(jω)| =1  ω0

PM = 180° + Phase  T ( jω0 ) 

Gain margin
– Defined at the frequency where Phase[T(jω)] = -180°  ω180

1
GM =
T ( jω180 )

B. Murmann EE214B Winter 2013-14 – Chapter 7 19

Example

20 log10 A0
Gain Margin

ω0 | p2 |

Phase Margin

B. Murmann EE214B Winter 2013-14 – Chapter 7 20

 Practical Phase Margins

Practical circuits typically use phase margins greater 45°

– For continuous time amplifiers, a common target is ~60°
• More later
– For switched capacitor circuits, a phase margin of ~75° is desirable
• See EE315A

In order to see the need for phase margin >45°, investigate the closed-
loop behavior at ω = ωu

1
T( jωu ) = a( jωu ) ⋅ f = 1 ⇒ a( jωu ) = (assuming f is real)
f

a( jωu )
A( jωu ) =
1 + a( jωu ) a( jωu )
a( jωu ) a( jωu )
= jφ[a( jωu )]
=
1+ e 1 + e j(PM−180° )

B. Murmann EE214B Winter 2013-14 – Chapter 7 21

PM = 45o
a( jωu ) a( jωu )
A( jωu ) = − j135°
=
1+ e 1 − 0.7 − 0.7j

a( jωu ) 1.3
∴ A( jωu ) = = ≅ 1.3A 0 “Peaking”
0.76 f

a( jωu ) a( jωu )
PM = 60o A( jωu ) = =
1+ e − j120°
1 − 0.5 − 0.87j
1
∴ A( jωu ) = a( jωu ) = ≅ A0 “Flat”
f

PM = 90o a( jωu ) a( jωu )

A( jωu ) = − j90°
=
1+ e 1− j
a( jωu ) 0.7
∴ A( jωu ) = = ≅ 0.7A 0 “Drooping”
1.4 f

B. Murmann EE214B Winter 2013-14 – Chapter 7 22

 Typical Closed-Loop Response for Various Phase Margins

|A|/A0 ω/ω u

(These curves are based on a two-pole loop response)

B. Murmann EE214 Winter 2010-11 – Chapter 5 23

Frequency Compensation

Frequency compensation refers to the means by which the frequency

response of the loop gain is altered to ensure stability and adequate
phase margin

Frequency compensation can be categorized into three groups
– Internal compensation = alter the frequency response of a(s)
– External compensation = alter the frequency response of f(s)
– Or alter both!

Consequently, there exist many different options for frequency
compensation, and it is often not immediately obviously which one is
ideal for the design problem at hand
– We will explore various options “just in time” as we work our way
through practically relevant feedback amplifier circuits
– Then generalize in Chapter 10

B. Murmann EE214B Winter 2013-14 – Chapter 7 24

 Feedback and Noise

To first order, feedback has no impact on noise performance

– The amplifier's input referred noise can be simply pushed outside the
loop

To second order, we will see that feedback will in most cases slightly
increase the noise
– For example, there may be additional noise contributed by resistors
in the feedback network

Again, we will explore these subtleties using concrete examples

B. Murmann EE214B Winter 2013-14 – Chapter 7 25

Summary – Effect of Negative Feedback

↑ (1+T)
Bandwidth Approximately equal to unity gain
frequency of loop gain
↓ (1+T)
Gain Defined primarily by the
feedback network ~1/f

Port Impedances ↑ or ↓ (1+T) (typically)

Noise Moderate increase

B. Murmann EE214B Winter 2013-14 – Chapter 7 26

 Chapter 8
Feedback: TIA Example

Boris Murmann
Stanford University
Winter 2013-14

Textbook Sections: 5.4, 9.4.4

Motivating Example: TIA for High-Speed Optical Networks

Transimpedance gain 1800 Ω

Bandwidth 34 GHz
Input noise 25
/ 
Maximum input 1.3 mApp
Diode capacitance 200 fF
Technology 0.13 µm SiGe BiCMOS

C. Knochenhauer et al., “40 Gbit/s transimpedance amplifier with high linearity range in 0.13 µm SiGe
BiCMOS, Electronics Letters, May 12, 2012.

B. Murmann EE214B Winter 2013-14 – Chapter 8 2

 Overview

We will use the high-speed TIA example as a driver to establish a

number of useful design and analysis techniques
– “Project-based learning”

The idea is to start from the beginning and understand all (or most)
steps that a designer would go through to arrive at the circuit shown on
the previous slide

B. Murmann EE214B Winter 2013-14 – Chapter 8 3

Where does the Noise Specification come from?

Let’s consider a very simple example

Assuming two-level signaling (“NRZ”), we need
SNR > 16.9dB for a bit error rate (BER) of 10-12
– This follows from the “Q-function” (see any
course on communication systems)

In the given design, the rms noise is
approximately

  25


 ∙  ∙ 
 ∙ 34  ∙  5.8 

2 2 

The smallest signal we can receive while maintaining the given BER is

.

∙ 10   40.6 


This number then defines the minimum optical input power, maximum
length of the fiber, etc., typically in compliance with a certain standard

B. Murmann EE214B Winter 2013-14 – Chapter 8 4

 Why use a TIA and not just a Resistor?

మ
  
= 4 =

 

1
 = = 442
2

Assuming that transimpedance gain is fixed, both noise and f3dB are
fixed and beyond our control
– The noise happens to be much better than needed
– The bandwidth happens to be much worse than needed

This circuit lacks degrees of freedom that let us adjust gain, bandwidth
and noise independently (within some reasonable range)

B. Murmann EE214B Winter 2013-14 – Chapter 8 5

How about using a CB (or CG) Configuration?

 
 = ≅
2( + + ) 2

To get the bandwidth we want, chose

gm ≅ 43mS (1/gm = 23Ω), IC = 1.1mA



= 4 + 2 =
1 19

Δ  

Good news
– We are now meeting the gain, bandwidth and noise specification

Bad news
– The circuit has very small signal headroom: VR =1.1mA·1800Ω ≅ 2V
– The circuit cannot handle the maximum signal of 1.3mApp
– Any capacitance we connect to the output will kill the bandwidth
– Whatever we can do to try and fix these issues will drive us outside
the noise specification?
B. Murmann EE214B Winter 2013-14 – Chapter 8 6
 Commonly used Feedback TIAs

Feedback TIAs incorporate additional degrees of freedom that mitigate

theses issues

Over the years, the architectures shown below have evolved as
commonly used solutions (in both MOS and Bipolar technologies)

CS CD
Sung Min Park and Hoi-Jun Yoo,
"1.25-Gb/s regulated cascode
CMOS transimpedance amplifier
for Gigabit Ethernet applications,"
IEEE J. Solid-State Circuits, pp.
112-121, Jan. 2004

CG “Regulated Cascode”

B. Murmann EE214B Winter 2013-14 – Chapter 8 7

Optimality

None of these (or other) options are known to be “globally” optimum

Which one of these circuits performs best depends on the given
specifications and the target technology
– Welcome to analog design!

In the following discussion we will explore the CS architecture in more

detail and develop know-how that is generally useful for feedback
amplifier design

B. Murmann EE214B Winter 2013-14 – Chapter 8 8

 Starting Point: 1-Transistor CS TIA

(For simplicity, neglect ro and all capacitances)

Attractive property
– Both Rin and Rout are low, e.g. ~1/gm, for RD >> RF (prove this)

B. Murmann EE214B Winter 2013-14 – Chapter 8 9

What are “a” and “f”?

Not obvious at all

The transistor is definitely part of “a”

The resistor implements “f”, but also affects “a”

B. Murmann EE214B Winter 2013-14 – Chapter 8 10

 Analysis Methods

If all we wanted is an expression for the closed-loop gain, we can

abandon the “af” feedback model and simply analyze the circuit from first
principles (KCL, KVL)
– However, this yields no information about loop gain (which we need
for stability analysis)

There are two ways to map the circuit into a feedback block diagram

Return ratio analysis (see EE214A)
– “Asymptotic” method, does not attempt to break the circuit into pieces
– Find loop gain by injecting a test signal at the controlled source
– Find ideal closed-loop gain by setting the controlled source to infinity
– Proposed by Hendrik Bode

Two-port analysis (See Gray, Hurst, Lewis & Meyer, Chapter 8)
– “Massage” the circuit until we can squeeze it into the standard “af”
block diagram
– Proposed by Harold Black

B. Murmann EE214B Winter 2013-14 – Chapter 8 11

Nodal Analysis Result for the Closed-Loop Gain

 − 
− 

0= 1
 1− 
=  
 −   
= −
+   +
1
1+ 
 

0= 

For large gmRD and gmRF, the transresistance approaches -RF

Whichever analysis method we use (return ratio or two-port), the
obtained closed loop gain expression should match this result
– The above expression is therefore a useful reference point

B. Murmann EE214B Winter 2013-14 – Chapter 8 12

 Return Ratio Analysis

Step 1: Find the loop gain


   − 

=− =  

  
=− =−

Step 2: Find the ideal closed-loop gain

 = −i R  = 
v
= −
i 
೘ →

Step 3: Find the feedforward term

 = i r =  = 

v
i 
೘ 

B. Murmann EE214B Winter 2013-14 – Chapter 8 13

Computing the Closed-Loop Gain using Return Ratio

Parameters

1
   

1− 
 =   
1+ 1+ 1 +  
1 +  

+ = − + = −
1
1+ 


The result for the closed loop gain (A) matches the nodal analysis
expression perfectly

B. Murmann EE214B Winter 2013-14 – Chapter 8 14

 Similarity

+
If d=0 (no feedforward), the

sin Σ a sout return ratio model is identical
–
to the classical “af” model

→
f 1
A

 → TA =


The return ratio model can

therefore be viewed as an
extension that can capture
T feedforward
– There exist circuits where
feedforward is relevant (see
e.g. EE315A), but in the
majority of cases it is not

B. Murmann EE214B Winter 2013-14 – Chapter 8 15

Two-Port Modeling Approach (1)

The two-port modeling approach insists on the “af” two-box model and
looks to identify an idealized “f” block such that
– The feedback block does not load (or alter) the forward gain
– The feedback signal sums perfectly with the input (as in the “af” model)

Key to achieving the latter is the controlled source y12, which subtracts
from the input; the other elements in the block are needed for equivalence

B. Murmann EE214B Winter 2013-14 – Chapter 8 16

 Two-Port Modeling Approach (2)

We want the two networks below to be equivalent

 =   +  
 =   +  

This requires

 
 =   = 
1 1
     
= =−
మ  భ 

 
 =   = 
1 1
     
=− =
మ  భ 

B. Murmann EE214B Winter 2013-14 – Chapter 8 17

Two-Port Modeling Approach (3)

Final step
– Absorb all elements other than the ideal feedback source into the “a” block

B. Murmann EE214B Winter 2013-14 – Chapter 8 18

 Identification of “a” and “f”

a
RD
vo iε
+
RF ii a vo
v1 –
ii RF ifb
-v1/RF

f
-vo/RF vo

f
 = ೚ ∙ భ = −  −  =−
   ూ ీ 1

R
భ ೐ ಷ ూ ీ

1
1  1− 
 =  =  − =
1 R R  
 R + R  1+
= −
1
 

1+

B. Murmann EE214B Winter 2013-14 – Chapter 8 19

Interpretation

The obtained closed-loop gain matches the result from KCL and return
ratio analysis perfectly

However, the loop gain T that we obtained from the two-port model does
not match the return ratio result

This is to be expected, because the two-port model lumped the
feedforward effect into the forward path of the loop; but it is in reality not
part of the loop (see closed-loop return ratio model)
– The return ratio result is the “golden standard” for the purpose of loop
stability analysis

So then, why bother with the two-port model?
– It turns out that the two-port model is proper as long as feedforward
is insignificant
• In any practical circuit this is consistent with our design intent –
we want to build a circuit whose forward gain depends mostly on
the amplifier, not on an unwanted path
– The two-port model is “nice,” since everything we know about “af”
two-box models can be directly applied

B. Murmann EE214B Winter 2013-14 – Chapter 8 20

Neglecting Feedforward – Final Version of the Two-Port Model

Assuming RF >> RD

 = −  −  ≅ − 

 ూ ీ
R
ూ ీ
ಷ

 =  ≅  

The loop gain is now consistent with the

prediction from the return ratio analysis

B. Murmann EE214B Winter 2013-14 – Chapter 8 21

Generalization

The approach illustrated in the previous example can be generalized to

cover arbitrary feedback configurations

The example we considered had a voltage output and a current input
– We call this voltage-to-current feedback (“shunt-shunt” configuration)

There are three more possible configurations
– Current-to-voltage feedback (“series-series” configuration)
– Voltage-to-voltage feedback (“series-shunt” configuration)
– Current-to-current feedback ( “shunt-series” configuration)

For all four configurations, the same analysis steps apply
– Identify input and output variables and feedback configuration
– Find feedback function “f”
– Add loading impedances to input and output port of “a”
– Compute “a” (and its frequency dependence, noise)
– Perform calculations using ideal “af” feedback equations

B. Murmann EE214B Winter 2013-14 – Chapter 8 22

 Current-to-Voltage Feedback Model

absorb
in “a”

B. Murmann EE214B Winter 2013-14 – Chapter 8 23

Voltage-to-Voltage Feedback Model

absorb
in “a”

B. Murmann EE214B Winter 2013-14 – Chapter 8 24

 Current-to-Current Feedback Model

absorb
in “a”

B. Murmann EE214B Winter 2013-14 – Chapter 8 25

Port Impendaces

Negative feedback connected in series always increases the port

impedance by (1+T)

Negative feedback connected in shunt always reduces the port
impedance by (1+T)

This is straightforward to show this by analyzing the four two-port
models using KCL/KVL (see feedback intro slides for the case of
voltage-to-voltage feedback) or using Blackman’s impedance formula

B. Murmann EE214B Winter 2013-14 – Chapter 8 26

 Continuing our Design

Consider now a slightly more sophisticated CS TIA with a source-

follower output stage
– For now, ignore all capacitances, except CD

Use this circuit as an example to walk though a complete set of
calculations
– Find “a” and “f”
– Compute input and output resistances
– Compute closed-loop bandwidth
RD
– Compute input source referred noise
M2

vo
M1

ii CD

RF

B. Murmann EE214B Winter 2013-14 – Chapter 8 27

Two-Port Model

Assume RF >> 1/g’m = 1/(gm+gmb)

=−
1


  = −  

1
 1 +  

 ∙


 =   =  
 ≅  



B. Murmann EE214B Winter 2013-14 – Chapter 8 28

 Input and Output Resistance

Assume RF >> 1/g’m = 1/(gm+gmb)

 1 
  =
1 +   

≅
 ≅  

 =
1 1 1 1
 1 +    

 ≅ 

B. Murmann EE214B Winter 2013-14 – Chapter 8 29

Closed-Loop Bandwidth


  = −  

1
 1 +  

 ∙


 =   =  
 ≅  



, = (1 +  ) ,

≅  

1 1
 
  

, =

The closed-loop bandwidth increases (relative to the bandwidth of a(s))

consistent with the reduction in Rin

B. Murmann EE214B Winter 2013-14 – Chapter 8 30

 Noise Analysis

All we need to compute is the input referred current noise of “a”,

including the effect of CD, RF, etc.

The input referred current noise of the amplifier directly refers back to
the input current source

Note that “f” is noiseless in the employed two-port model
– The noise from RF is captured in “a”

B. Murmann EE214B Winter 2013-14 – Chapter 8 31

Noise Analysis of “a”

4
1


∆

4! ∆

4! ∆

4
1
4
1

∆

∆

All noise sources, except the noise of M1 and RF at the input are
negligible in practice

We already saw in our CE noise example that the RD noise is negligible
as long as gmRD is large
– All other noise sources are irrelevant by the same argument

B. Murmann EE214B Winter 2013-14 – Chapter 8 32

 Noise Analysis of “a”

4! ∆

4
1

∆

4!
1

∆

4
1

∆

B. Murmann EE214B Winter 2013-14 – Chapter 8 33

Noise Analysis of “a”


4 4! + " 

1 1 1
  
∆ ∆

 
  ≅ 4∆ +!
1

 

At low frequencies, the noise is usually dominated by RF

At high frequencies, extra noise from M1 rolls in
– This noise can be minimized by increasing gm1  larger device
and/or more current and capacitance added to the input node

B. Murmann EE214B Winter 2013-14 – Chapter 8 34

 Inclusion of Cgs

 =  ≅ 

4!  
1
4
1

∆

∆


+  
+ 
 
  ≅ 4∆
 
+! ≅ 4∆ +!
1 1
   

This expression is minimized for Cgs = CD, in which case we have


  ≅ 4∆
1


+ 4!

B. Murmann EE214B Winter 2013-14 – Chapter 8 35

We can now solve for the frequency where the noise of M1 takes over

= 4!
1



!
 

! =2

In a practical design, this frequency must be somewhat below the

circuit’s bandwidth (or else we will ruin the noise performance)

For a given CD and process ωT, this limits how much transimpedance
gain (RF) or bandwidth we can extract from the amplifier

Example:
fT = 150 GHz, CD = 200 fF, RF = 220 Ω, γ = 1
⇒ fco = 46 GHz

B. Murmann EE214B Winter 2013-14 – Chapter 8 36

 Continuing our Design

RD

M2

vo
M1

ii CD

RF

B. Murmann EE214B Winter 2013-14 – Chapter 8 37

Relevant Device Capacitances

Cgd2

RD
Cgd1 Cdb1
M2
Csb2

M1 Cgs2
vo
Cgs1
ii
CD
RF

Problem: Miller multiplication of Cgd1

B. Murmann EE214B Winter 2013-14 – Chapter 8 38

 Circuit with Cascode Input Stage

Cgd2
RD
Cgd3 Cdb3
M2
Csb2
Cgs2
Cgs3
Cgd1
Cdb1+Csb3
M1 vo
Cgs1
ii
CD
RF

B. Murmann EE214B Winter 2013-14 – Chapter 8 39

Model of Forward Amplifier a(s)

 =  +  + 1 −  

RD

 = −
1
M2  
C2

 = −
C4 1


M3

 =  + # + # " = #" 



 = −

C3
 = 
+  + 2


M1 vo

" = −
"
ii C1 RF RF

B. Murmann EE214B Winter 2013-14 – Chapter 8 40

 Prototype Circuit

IB IB IB
 = 1$
M2
 = 1Ω
RD vo
M3 
= 2Ω

W/5 IB 
= 200%

&& * = 0.18 $
M1

ii CD RF

&&  /
= 10'/ 
/( = 29.3/$ && ( = 34 $

B. Murmann EE214B Winter 2013-14 – Chapter 8 41

Operating Point

element 0:m1 0:m2 0:m3

model 0:nmos214 0:nmos214 0:nmos214
region Saturati Saturati Saturati
id 996.5217u 1.0000m 996.5217u
vgs 689.4266m 812.8655m 726.8479m
vds 290.6305m 1.1106 1.2117
vbs 0 -689.42m -290.63m
vth 491.3958m 649.1707m 557.9840m
vdsat 147.8615m 143.2316m 138.8442m
vod 198.0308m 163.6948m 168.8639m
gm 9.3602m 10.1505m 10.1110m
gds 487.0970u 281.1118u 268.4636u
gmb 2.2263m 2.0191m 2.2033m
cdtot 43.6454f 37.1183f 37.8625f
cgtot 69.8437f 68.8173f 69.2204f
cstot 81.7366f 74.9554f 78.1306f
cbtot 66.9125f 52.9684f 57.4258f
cgs 49.7990f 49.9630f 49.8352f
cgd 16.5154f 16.3953f 16.3916f

B. Murmann EE214B Winter 2013-14 – Chapter 8 42

 Pole Calculations

Cgs := 49fF Cgd := 16fF Cdb := 20fF Csb := 25fF CD := 200fF

g m := 10mS g mb := 2.2mS Rf := 1kΩ RD := 2kΩ

gm
A v2 := = 0.758 T0 := g m⋅ RD⋅ A v2 = 15.152
1
g m + g mb +
Rf

1 1
C1 := CD + Cgs + 2⋅ Cgd = 281⋅ fF fp1 := ⋅ = 566.388MHz
⋅
2⋅ π Rf ⋅ C1
Relevant
1 1
( )
C2 := 2Cgd + 1 − A v2 ⋅ Cgs + Cdb = 63.879fF
⋅ fp2 := ⋅
2⋅ π RD⋅ C2
= 1.246⋅ GHz

1 g m + g mb Somewhat
C3 := Cgs + Csb + Cdb = 94⋅ fF fp3 := ⋅ = 20.656GHz
⋅
2⋅ π C3 relevant

1 g m + g mb Irrelevant
C4 := Csb = 25⋅ fF fp4 := ⋅ = 77.668GHz
⋅
2⋅ π C4

B. Murmann EE214B Winter 2013-14 – Chapter 8 43

Issue: Phase Margin


566MHz   =
15.1  
1+ 1+
1.24GHz $ $

 
≅
 ≅ $ $
$ $
 ≅ 3.2+

20.6GHz

  
, = 180° − -. − -. − -.
$ $ $
, = 180° − 80° − 69° − 12 = 19°

B. Murmann EE214B Winter 2013-14 – Chapter 8 44

 Loop Gain Simulation

20 *** LSTB analysis ***

Magnitude [dB]
gain_margin(dB) =
0 8.711791
-20
phase_margin(deg) =
-40 20.96923
-60
phase_margin_freq(Hz) =
-80 8 10
2.7774433E+09
10 10
Frequency [Hz] gain_margin_freq(Hz) =
4.6721000E+09
0
Phase [degrees]

loop_gain_at_min_freq(dB) =
-100 23.16820

-200
See appendix for
-300 setup of LSTB
analysis in HSpice
8 10
10 10
Frequency [Hz]

B. Murmann EE214B Winter 2013-14 – Chapter 8 45

Closed-Loop Response

f 3dB = 4.54 GHz

80

60
Magnitude [dB]

40

20

0 7 8 9 10 11
10 10 10 10 10
Frequency [Hz]

Lots of peaking, as expected

B. Murmann EE214B Winter 2013-14 – Chapter 8 46

 Derivation of Closed-Loop Transfer Function


  =
 
1+ 1+
$ $

1   1 
  =
1
1+   1 + 
= ∙
+ 
$ + $ 1
(1 +  ) (1 +  )
1+
$ $ $ $


  =
 
1+ /+ 
 

(1 +  )
(1 +  ) /=
$ $
 = $ $ ≅ 
$ + $

B. Murmann EE214B Winter 2013-14 – Chapter 8 47

Q=0.5
5 Q=1/sqrt(2)
Q=1
0 Q=2
Magnitude [dB]

-5

-10

-15

-20 -2 -1 0 1
10 10 10 10
ω /ω 0

H  = |H  = " |=/
1
  
1+ /+ 
 

B. Murmann EE214B Winter 2013-14 – Chapter 8 48

 Closed-Loop Poles

The closed-loop poles are the roots of the denominator polynomial

 
10 0 0
Location in the s-plane
/
 for Q > 0.5


s1 jω

12 / 6 0.5 ,  4 1 5 " 4/ 4 1


2/

Complex Conjugate Poles σ

12 / 3 0.5 ,  4 1 5 1 4 4/


2/ Text, p. 164

Real Poles
s2

B. Murmann EE214B Winter 2013-14 – Chapter 8 49

Q=2

|H(s)|

Imag(s)/ω0
Re(s)/ω0

s-plane
s = σ + jω

B. Murmann EE214B Winter 2013-14 – Chapter 8 50

 Q = 1/√2

|H(s)|

Imag(s)/ω0
Re(s)/ω0

s-plane
s = σ + jω

B. Murmann EE214B Winter 2013-14 – Chapter 8 51

Q = 0.5

|H(s)|

Imag(s)/ω0
Re(s)/ω0

s-plane
s = σ + jω

B. Murmann EE214B Winter 2013-14 – Chapter 8 52

 Relationship Between Phase Margin and Q

ωu/ω p2

ωu/ω p2

Text, p. 219

B. Murmann EE214B Winter 2013-14 – Chapter 8 53

Aside: Step Response

“underdamped”
Q > 0.5

Q=0.5

Q < 0.5
“overdamped”
Text, p. 164

Ringing for Q > 0.5

The case of Q = 0.5 is called maximally damped response (fastest
settling without any overshoot)

B. Murmann EE214B Winter 2013-14 – Chapter 8 54

 What Should We Design For?

A typical goal in wideband amplifier design is to achieve the maximum

possible bandwidth without any peaking in the frequency response

For a second-order system the corresponding solution is Q = 1/√2
– Closed-loop poles have equal real and imaginary parts
– The closed loop bandwidth is equal to ω0
– The phase margin is approximately 63 degrees (prove this)

This response is called Maximally Flat Magnitude (MFM) or Butterworth
response
jω

ω0
45º
σ

B. Murmann EE214B Winter 2013-14 – Chapter 8 55

How to Achieve a MFM Response?

Our current design is quite far away from a MFM response

(1 +  ) 1 + 15.2 566 ∙ 1.24+

/=
$ $
566 + 1.24+
= = 1.9
$ + $

Getting the phase margin we need for an MFM response would require
that one of the poles occurs beyond the unity gain frequency of the loop

One (non-preferred) solution that

ωp1
achieves this is narrowbanding
ωp2 – Reduce ωp1 (e.g. by increasing
C1) until unity crossover occurs
before ωp2

Key issue: substantial loss in
bandwidth, as seen by the
reduction in ωu

B. Murmann EE214B Winter 2013-14 – Chapter 8 56

 Better Idea: Feedback (or “Phantom”) Zero Compensation

Leave the poles of a(s) untouched and introduce a left half plane zero in f(s),
close to the unity gain frequency of the loop

Top first order, the phase margin will be 45 degrees (instead of 0 degrees)
when the zero is placed at the unity gain frequency of the loop

Two questions
– How can we realize the zero?
– How exactly should we position it to get a maximally flat response?

B. Murmann EE214B Winter 2013-14 – Chapter 8 57

Introducing a Zero in the Feedback Network

 =   +  
 =   +  

 
 =  +   =  + 
1 1
     
= =−
మ  భ 

 
 =  +   =  + 
1 1
     
=− =
మ  భ 

  =  = − 1 +   =−

1 1
  

B. Murmann EE214B Winter 2013-14 – Chapter 8 58

 Modified Model of Forward Amplifier a(s)

RD

M2
C2
M3 C4

 = −
1
 ( + )
C3


vo
M1 

" = −
ii C1 RF CF RF CF (" + )

CF moves two of the poles to lower frequencies.

However, we will see that CF is typically very small, and thus the shift is
usually not all that significant

B. Murmann EE214B Winter 2013-14 – Chapter 8 59

Derivation of the new Closed-Loop Transfer Function


 1 + 
  =   =  1 +
 
&

1+ 1+ &
$ $

  1 
  =
1 1
() 1 +    1 +   
= ∙
1+ /+ 
 

 = (1 +  ) $ $ ≅  Unchanged

1 $ + $ 
/
= + New degree of freedom
 &

B. Murmann EE214B Winter 2013-14 – Chapter 8 60

 Positioning the Zero

1 $ + $ 
/
= + = 2
 &

 
= ≅
2 −
&
$ + $ 2


For our design:

& =
3.27+
566 + 1.24+
= 3.8+
2 − 3.27+

 = = 42%
1
28& 

B. Murmann EE214B Winter 2013-14 – Chapter 8 61

Closed-Loop Response with CF = 42fF

f 3dB = 3.91 GHz

70 ********pole/zero analysis
poles ( hertz)
60 real imag
-1.66988g 2.73938g
50
Magnitude [dB]

-1.66988g -2.73938g
-10.7624g 0.
40 -20.3840g 0.
-23.3910g 0.
30
zeros ( hertz)
20 real imag
15.5276g 0.
10
-20.1601g -12.6203g
-20.1601g 12.6203g
0 7 8 9 10 11
10 10 10 10 10 -23.3910g 0.
Frequency [Hz]

We still see some minor peaking

This is due to the fact that we have neglected higher frequency poles
and the extra loading in the forward amplifier due to CF

B. Murmann EE214B Winter 2013-14 – Chapter 8 62

 Closed-Loop Response with CF Tweaked to 55fF

f 3dB = 3.54 GHz

70 ********pole/zero analysis
poles ( hertz)
60 real imag
-2.23916g -2.62969g
50 -2.23916g 2.62969g
Magnitude [dB]

-8.09147g 0.
40 -20.3512g 0.
-23.3910g 0.
30
zeros (rad/sec)
20 zeros ( hertz)
real imag
10 14.0106g 0.
-18.6215g -11.4893g
0 7 8 9 10 11
-18.6215g 11.4893g
10 10 10 10 10 -23.3910g 0.
Frequency [Hz]

The poles are still not exactly angled at 45 degrees, but this is OK
– A high frequency pole (not analyzed) helps reduce any residual peaking

B. Murmann EE214B Winter 2013-14 – Chapter 8 63

Loop Gain Simulation

20 *** LSTB analysis ***

Magnitude [dB]

gain_margin(dB) =
0 24.02825
-20
phase_margin(deg) =
-40 55.81567
-60
phase_margin_freq(Hz) =
-80 8 10
3.1666851E+09
10 10
Frequency [Hz] gain_margin_freq(Hz) =
1.9178802E+10
0
Phase [degrees]

loop_gain_at_min_freq(dB) =
-100 23.16766

-200 Phase margin somewhat

smaller than expected
-300
(again, due to high frequency
8 10 poles that we did not
10 10
Frequency [Hz] consider)

B. Murmann EE214B Winter 2013-14 – Chapter 8 64

 APPENDIX

Loop Gain Simulation

B. Murmann EE214B Winter 2013-14 – Chapter 8 65

References

H.W. Bode, Network Analysis and Feedback Amplifier Design, Van

Nostrand, New York, 1945.

R.D. Middlebrook, "Measurement of Loop Gain in Feedback Systems,"
Int. J. Electronics, Vol. 38, No.4, .pp. 485-512, 1975.

S. Rosenstark, "Loop Gain Measurement in Feedback Amplifiers," Int. J.
Electronics, Vol. 57, No.3., pp. 415-421, 1984.

P.J. Hurst, "Exact Simulation of Feedback Circuit Parameters," Trans.
on Circuits and Systems, pp.1382-1389, Nov. 1991.

P.J. Hurst, S.H. Lewis, "Simulation of Return Ratio in Fully Differential
Feedback Circuits," Proc. CICC 1994, pp.29-32.

M. Tian, V. Visvanathan, J. Hantgan, K. Kundert, "Striving for small-
signal stability," IEEE Circuits and Devices Magazine, pp. 31-41,
January 2001.

F. Wiedmann, “Loop Gain Simulation,”
https://sites.google.com/site/frankwiedmann/loopgain

B. Murmann EE214B Winter 2013-14 – Chapter 8 66

 Circuit Example

What is the loop gain in this circuit?

B. Murmann EE214B Winter 2013-14 – Chapter 8 67

Return Ratio Analysis

ir
T ( s) = −
it

Hand analysis, for example using the return ratio method, is

straightforward

How can we simulate T(jω) in Spice?
– Using "real" transistor models

B. Murmann EE214B Winter 2013-14 – Chapter 8 68

 Spice MOSFET AC Simulation Model

[HSpice manual]

Nodes of the controlled source are not accesible!

– Cannot break loop at gm generator

B. Murmann EE214B Winter 2013-14 – Chapter 8 69

Popular (but Non-Preferred) Simulation Approach

vr
T ( jω ) ≅ −
vt

Inaccurate

Hard to estimate mock load

May get different results for
different breakpoints

Ideally, we'd like to avoid all of
the above issues

Solution: Middlebrook method

B. Murmann EE214B Winter 2013-14 – Chapter 8 70

 Problem Generalization

Middlebrook argued that any single loop feedback circuit can be

partitioned as shown below

Hence, there is always some "nonideal" breakpoint between
impedances
– How can we use this breakpoint to find the loop gain?

available breakpoint

Z1 ⋅ Z2
T(s) = gm
Z1 + Z2

B. Murmann EE214B Winter 2013-14 – Chapter 8 71

Double Injection Trick

vy Z2
− ≡ Tv = gm ⋅ Z2 +
vx Z1
Solving yields:

1 1 1
True Loop T = g ⋅ Z1Z2 = +
Gain: m
Z1 + Z 2 1 + T 1 + Tv 1 + Ti

Tv Ti − 1
iy T =
Z1 Tv + Ti + 2
≡ Ti = gm ⋅ Z1 +
ix Z2

No “DC“ break in the loop, all loading effects included!

Measure Tv and Ti separately, then calculate actual T

B. Murmann EE214B Winter 2013-14 – Chapter 8 72

 Implementation in Circuit Simulators

The Middlebrook method (or a variant thereof) is implemented in most

modern circuit simulators such as HSpice and Spectre
– LSTB analysis in HSpice
– STB analysis in Spectre

For details, refer to HSpice manual
– /usr/class/ee/synopsys/hspice/F-2011.09
SP2/hspice/docs_help>/hspice_aasa.pdf

Important note
– In class and in all major textbooks, the loop phase is defined as zero
for negative feedback
– Unfortunately, LSTB and STB analyses report the phase 180
degrees shifted
• Easy to fix; don’t get confused by this?

B. Murmann EE214B Winter 2013-14 – Chapter 8 73

LSTB Syntax

Loop Stability Analysis Usage

.LSTB mode=[single|diff|comm]
+ vsource=[vlstb|vlstbp,vlstbn]
Examples
Single-mode loop analysis on loop indicated by vx voltage source:
.LSTB mode=single vsource=vx
Differential-mode loop analysis on loops indicated by vp and vn voltage
sources:
.LSTB mode=diff vsource=vp,vn
Common-mode loop analysis on loops indicated by vp and vn voltage
sources:
.LSTB mode=comm vsource=vp,vn

B. Murmann EE214B Winter 2013-14 – Chapter 8 74

 LSTB Simulation Setup for TIA Example

IB IB IB

M2

RD vo
M3

W/5 IB

M1

ii CD RF vx

.ac dec 100 10e6 100e9

.lstb mode=single vsource=vx
.probe ac lstb(db) lstb(p)

B. Murmann EE214B Winter 2013-14 – Chapter 8 75

How About Multiple Feedback Loops?

Any practical feedback circuit has multiple feedback loops

– Fully differential circuits have CM/DM loops (see EE315A)
– Local device feedback through Cgd, Rsource
– ...

Solutions
– Decompose fully differential circuit into CM/DM loops
– If a local feedback loop can be modeled as a combination of a stable
controlled source and passive impedances, the multi-loop circuit
reduces to a single loop [Hurst 94]
– If there is a common breakpoint that breaks all feedback loops
simultaneosly, stability can be checked by finding the return ratio at
the single breakpoint [Hurst 94]

B. Murmann EE214B Winter 2013-14 – Chapter 8 76

 Example

[Hurst, 1994]

B. Murmann EE214B Winter 2013-14 – Chapter 8 77

Last Resort: General Nyquist Criterion

[Bode 45]:

“If a circuit is stable when all its tubes have their

nominal gains, the total number of clockwise and
counterclockwise encirclements of the critical
point must be equal to each other in the series of
Nyquist diagrams for the individual tubes
obtained by beginning with all tubes dead and
restoring the tubes successively in any order to
their nominal gains“

[You may want to take a controls class if you are

interested in this...]

B. Murmann EE214B Winter 2013-14 – Chapter 8 78

 Another Useful Quote

[Bode 45]:

“... thus the circuit may sing when the

tubes begin to lose their gain because of
age, and it may also sing, instead of
behaving as it should, when the gain
increases from zero as power is supplied
to the circuit...“

Always run one or more transient analyses for a

"true" stability check!

B. Murmann EE214B Winter 2013-14 – Chapter 8 79

 Chapter 9
Feedback: Cherry-Hooper Example

Boris Murmann
Stanford University
Winter 2013-14

Broadband Amplifier Design with Local Feedback

Rein & Moller, JSSC 8/1996

In a cascade of amplifier stages, the interaction (loading) between adjacent

stages can be minimized by alternating local series and shunt feedback circuits.

B. Murmann EE214B Winter 2013-14 – Chapter 9 2

 Advantages & Disadvantages of Local Feedback Cascades

Advantages
• No instability
• Lower gain sensitivity to component and device parameter
variations than amplifiers without local feedback

Disadvantages
• Higher gain sensitivity (less loop gain) than amplifiers with
multi-stage feedback
• Bandwidth obtainable is typically slightly less than that
possible in amplifiers with multi-stage feedback

B. Murmann EE214B Winter 2013-14 – Chapter 9 3

Application Example (1)

Poulton, ISSCC 2003

B. Murmann EE214B Winter 2013-14 – Chapter 9 4

 Application Example (2)

Poulton, ISSCC 2003

B. Murmann EE214B Winter 2013-14 – Chapter 9 5

Application Example (3)

Poulton, ISSCC 2003

BW ~ 6 GHz

B. Murmann EE214B Winter 2013-14 – Chapter 9 6

 Cherry-Hooper Amplifier

RF
For gmRE >>1

ܴி
RE ‫ܣ‬௩଴ ≅
ܴா
Shunt F/B
Stage “ratiometric”
Series F/B
Stage

E. Cherry and D. Hooper, Proc. IEE, Feb. 1963

B. Murmann EE214B Winter 2013-14 – Chapter 9 7

Series Feedback Stage

Small-signal equivalent circuit:

RS Cµ io

+
vi ~ v1 rπ Cπ gmv1 ZL
–
+
vE RE
–

Include transistor rb in RS

Neglect rµ, ro, re, and rc

Assume that ZL ≈ 0; then there is no Milller effect and Cµ is just a

(small) capacitance to ground which often has negligible impact.

B. Murmann EE214B Winter 2013-14 – Chapter 9 8

 Define
1
Yπ = + sCπ
rπ
Then
v i − (v1 + vE )
= v1Yπ
RS
vE
v1Yπ + gmv1 =
RE

Substituting for vE in the first of these two equations

v i − v1 1+ (gm + Yπ ) RE  = v1YπRS

v1 1
∴ =
v i 1+ (gm + Yπ ) RE + YπRS

B. Murmann EE214B Winter 2013-14 – Chapter 9 9

Since io = –gmv1

io gm
=−
vi 1+ gmRE + (RS + RE )Yπ
 
 
 gm   1 
= −  
 1+ gmRE   R + RE   1 
 1+  S  + sC π

  1+ gmRE   rπ  
 
 
 gm   1 
= −  
 1+ gmRE   R + RE   1   RS + RE  
 1+  S   1+ g R  + sC π 
  rπ  m E  1+ gmRE  

B. Murmann EE214B Winter 2013-14 – Chapter 9 10

 Usually,

 RS + RE   1  gm (RS + RE )  1 
 r   1+ g R  = β0   << 1
 π  m E  1+ gmRE 

Then
io  1 
≅ −gmeq  
vi  1− s p1 

where
gm
gmeq =
1+ gmRE

 1+ gmRE   1 
p1 = −    
 C π   RE + RS 

B. Murmann EE214B Winter 2013-14 – Chapter 9 11

If gmRE >> 1
1
gmeq ≅
RE

and

gm  RE   Cπ + Cµ  RE   RE 
p1 ≅ −   = − ωT    ≅ − ωT  
Cπ  RE + RS   Cπ  RE + RS   RE + RS 

Note that this result corresponds to the dominant time constant

found via ZVTC analysis in chapter 3.

Thus, for RE >> RS, p1 → – ωT. In some cases, the bandwidth

may then be actually limited by Cµ (which was neglected in this
analysis).

B. Murmann EE214B Winter 2013-14 – Chapter 9 12

 Emitter Peaking

The bandwidth of the series feedback stage can be increased by

introducing an “emitter peaking” capacitor in shunt with RE.

io

RS
+ Q1
vi ~ Not a large bypass
– capacitor
RE CE

To analyze this circuit, substitute ZE for RE in the preceding

analysis, where
1 RE
ZE = =
YE 1+ sRECE

B. Murmann EE214B Winter 2013-14 – Chapter 9 13

Cπ
Then, defining τE = RECE and assuming τT ≅
gm

io gm
=−
vi 1
1 + gmZE + (RS + ZE )( + sCπ )
rπ
gm
=−
RS  RE   1 
1+ + sCπRS +    gm + + sCπ 
rπ  1 + sτE   rπ 
gm
≅−
R  g R  C 
1 + S + sCπRS +  m E  1 + s π 
rπ  1 + sτE  gm 

1
sin ce gm >>
rπ

B. Murmann EE214B Winter 2013-14 – Chapter 9 14

 io gm
∴ ≅−
vi RS  1+ sτT 
1+ + sC πRS + gmRE  
rπ  1+ sτE 

If CE is chosen so that
τE = τT

and it is true that

RS gmRS
gmRE >> =
rπ β0

Then
 
 
io  gm   1 
≅ − 
vi  1+ gmRE    RS  
 1+ sC π  
  1+ gmRE  

B. Murmann EE214B Winter 2013-14 – Chapter 9 15

The result is a single-pole response with

1+ gmRE R 
p1 = − ≅ −ω T  E 
RS C π  RS 

In this case, if RE > RS, then |p1| > ωT (!)

The bottom line is that this stage has no significant bandwidth

limitations; the frequency response of the overall Cherry-
Hooper amplifier will mostly depend on the second stage.

B. Murmann EE214B Winter 2013-14 – Chapter 9 16

 Shunt Feedback Stage

Small-signal equivalent circuit

CF

RF

+ +
ii v1 rπ Cπ gmv1 RL CL vo
– –

Include transistor Cµ in CF
Neglect RS or include it in rπ
Neglect rb, rc, re, and rµ
Include ro and Ccs in RL and CL

B. Murmann EE214B Winter 2013-14 – Chapter 9 17

Analysis (1)

We can analyze this circuit from first principles using KCL and then simplify
to get to a low-entropy result. However, it is much faster to look the circuit
using a two-port feedback approach, and use our understanding from
chapter 8.

଴ 

 =   = ଴ 1 +
  ௭
1+ 1+
௣ଵ ௣ଶ

଴
 = ଴ = (1 + ଴ )௣ଵ ௣ଶ ≅ ௨
 ଶ
1+
+ ଶ
଴ ଴

1 ௨
For a maximally flat response (Q=0.707), set: ௭ = ≅
ி ி 2

B. Murmann EE214B Winter 2013-14 – Chapter 9 18

 Analysis (2)

Model of a(s):

+ +
ii v1 gmv1 vo
– –
rπ||RF Cπ||CF RL||RF CL||CF

௢ 1 1

଴ = = −ி ௠ (௅ ||ி ) ௣ଵ = ௣ଶ =
௜ R ୊ Cగ (௅ | ி ௅

௠ 1 1
௨ ≅ ଴ ௣ଵ ௣ଶ = ∙ ≅ ் ∙
௅ R ୊ Cగ R ୊ ௅

B. Murmann EE214B Winter 2013-14 – Chapter 9 19

Analysis (3)

Now, assuming that CF is properly set to yield a MFM response, the

bandwidth of the overall Cherry-Hooper amplifier is

1
ଷௗ஻ = ଴ ≅ ௨ ≅ ் ∙
R ୊ ௅

Further insight can be gained from this result by considering the input
capacitance of the overall Cherry-Hooper amplifier

గ 1 ௅
௜௡ ≅ = = k = “fanout”
௠ ா  ் ா 

1 ்
ଷௗ஻ ≅ ் ∙ =
  ௩଴
R୊
 ் ா

B. Murmann EE214B Winter 2013-14 – Chapter 9 20

 Chapter 10
Feedback: Root Locus and
Frequency Compensation

Boris Murmann
Stanford University
Winter 2013-14

Reference: Gray, Hurst, Lewis & Meyer, Chapter 9

Textbook Section: 6.2

Root Locus

As we have seen from our analysis of first- and second-order feedback

systems, applying feedback around an amplifier moves the open-loop
poles to a new location

Example: 1st order feedback system
jω

s-plane

x x σ
(1+T0)p1 p1

A so-called “root locus” plot shows the movement of the poles in the s-
plane as we vary the low-frequency loop gain T0

Root locus plots are most commonly used in control theory, but can
provide valuable intuition for the design of amplifiers and other electronic
circuits

B. Murmann EE214B Winter 2013-14 – Chapter 10 2

 Second-Order System

1
H  =
଴
 ଶ   > 0.5 ଵ,ଶ = − 1 ±
4ଶ − 1
1+
+ ଶ 2
଴
଴

଴
  ≤ 0.5 ଵ,ଶ =− 1 ± 1 − 4ଶ
2

଴ = (1 + ଴ )
௣ଵ
௣ଶ
jω
(1 + ଴ )
௣ଵ
௣ଶ
= s-plane

௣ଵ +
௣ଶ
p2 p1
σ

 = 0.5

଴
௣ଵ +
௣ଶ
=− =−
2 2

B. Murmann EE214B Winter 2013-14 – Chapter 10 3

Third Order System

Consider a feedback network consisting of a forward amplifier with three

identical poles, and a feedback network with a constant transfer function f
a0
3
 s
1 − 
a(s) =
a0
A(s) =
a(s)
=  p1  =
a0
T0 = a0 f
 s
3
1 + a(s)f a  s
3
1+ a 0
f
1 −   s
3
 1 −  + T0
 p1   1 −   p1 
 p 1

The poles of A(s) are therefore the solution to

3 3
 s  s
 1 −  + T0 = 0  1 −  = −T0
 p1   p1 

B. Murmann EE214B Winter 2013-14 – Chapter 10 4

  s  s  s
 1 −  = 3 −T0 = − 3 T0 or  1 −  = 3 T0 e j60° or  1 −  = 3 T0 e − j60°
 p1   p1   p1 

(
s1 = p1 1 + 3 T0 )
s2 = p (1 −
1
3 T0 e j60° )
s3 = p (1 −
1
3 T0 e − j60° )

0 = 1 − Re ( 3 T0 e j60° )
0 = 1 − 3 T0 cos(60°)
⇒ T0 = 8

Conclusion: An amplifier with three identical poles is unstable unless we

limit the low-frequency loop gain to less than eight

B. Murmann EE214B Winter 2013-14 – Chapter 10 5

Generalization

The poles of A(s) are the roots of 1 + T(s) = 0.

In general,

1+ a1s + a 2s2 + ⋅⋅⋅ Na (s)

a(s) = a0 2
= a0
1+ b1s + b 2s + ⋅⋅⋅ Da (s)

and
1+ c1s + c 2s2 + ⋅⋅⋅ Nf (s)
f(s) = f0 2
= f0
1+ d1s + d2s + ⋅⋅⋅ D f (s)

Thus,
a0 Na (s)D f (s)
A(s) =
Da (s)D f (s) + T0 Na (s)Nf (s)

where T0 = a0f0.

B. Murmann EE214B Winter 2013-14 – Chapter 10 6

 The zeros of A(s) are the zeros of a(s) and the poles of f(s).

The poles of A(s) are the roots of

Da (s) D f (s) + T0 Na (s)Nf (s) = 0

As T0 increases from 0 to ∞, the poles of A(s) move in the

s-plane from the poles of a(s) to the zeros of f(s).

a0 Na (s)D f (s)
T0=0 A(s) =
Da (s)D f (s) + T0 Na (s)Nf (s)

a0 Na (s)D f (s)
T0→∞ A(s) =
Da (s)D f (s) + T0 Na (s)Nf (s)

B. Murmann EE214B Winter 2013-14 – Chapter 10 7

We can establish general root-locus construction rules using

Na (s) ⋅Nf (s) Na (s) ⋅Nf (s)

1+ T(s) = 1+ T0 ⋅ =0 T0 ⋅ = −1
Da (s) ⋅D f (s) Da (s) ⋅D f (s)

(1− s z a1)(1− s z a2 ) ⋅⋅⋅(1− s z f1)(1− s z f 2 ) ⋅ ⋅⋅

T0 ⋅ = −1
(1− s pa1)(1− s pa2 ) ⋅ ⋅⋅(1− s p f1)(1− s p f 2 ) ⋅⋅⋅

where
za1,za2 ,... = zeros of a(s)
zeros of T(s)
zf1,zf 2 ,... = zeros of f(s)
pa1,pa2 ,... = poles of a(s)
poles of T(s)
p f1,pf 2 ,... = poles of f(s)

B. Murmann EE214B Winter 2013-14 – Chapter 10 8

 The above equation can be rewritten as

 (−pa1)(−pa2 ) ⋅⋅⋅ (−p f1)(−p f 2 ) ⋅⋅⋅ 

T0 ⋅  
 (−za1)(−z a2 ) ⋅⋅⋅ (−z f1)(−z f 2 ) ⋅⋅⋅ 
(s − za1)(s − za2 ) ⋅⋅⋅ (s − zf1)(s − zf 2 ) ⋅⋅⋅
×  = −1
(s − pa1)(s − pa2 ) ⋅⋅⋅ (s − pf1)(s − pf 2 ) ⋅⋅⋅

Expect all poles of T(s) to be in the left half plane (LHP).

If all zeros of T(s) are in the LHP, or if there are an even

number of zeros in the RHP, then the first bracketed term in
the above equation is positive, in which case

 p p ⋅ ⋅⋅ p f1 p f 2 ⋅⋅⋅ 
T0 ⋅  a1 a2 
 z a1 z a2 ⋅ ⋅⋅ z f1 z f 2 ⋅⋅⋅ 
(s − za1)(s − za2 ) ⋅⋅⋅ (s − zf1)(s − zf 2 ) ⋅⋅⋅
×  = −1
(s − pa1)(s − pa2 ) ⋅⋅⋅ (s − p f1)(s − pf 2 ) ⋅⋅⋅

B. Murmann EE214B Winter 2013-14 – Chapter 10 9

Values of s satisfying the above equation are the poles of A(s).

These values simultaneously fulfill both a phase condition and
a magnitude condition, and these conditions define the points
of the root locus.

Phase Condition

 ∠(s − z a1) + ∠(s − z a2 ) + ⋅⋅ ⋅ + ∠(s − z f1) + ∠(s − z f 2 ) + ⋅⋅⋅

−  ∠(s − pa1) + ∠(s − pa2 ) + ⋅⋅⋅ + ∠(s − p f1) + ∠(s − p f 2 ) + ⋅⋅ ⋅
= (2n − 1)π

Magnitude Condition

 p p ⋅⋅⋅ p f1 p f 2 ⋅⋅⋅   s − z a1 s − z a2 ⋅⋅⋅ s − z f1 s − z f 2 ⋅⋅⋅ 

T0 ⋅  a1 a2  ⋅  = +1
 z a1 z a2 ⋅⋅⋅ z f1 z f 2 ⋅⋅⋅   s − pa1 s − pa2 ⋅⋅⋅ s − p f1 s − p f 2 ⋅⋅⋅ 

B. Murmann EE214B Winter 2013-14 – Chapter 10 10

 For the case where there are an odd number of zeros in the RHP,
the magnitude condition remains the same as above, but the
phase condition is changed. Specifically,

 p p ⋅⋅⋅ p f1 p f 2 ⋅⋅⋅   s − z a1 s − z a2 ⋅⋅⋅ s − z f1 s − z f 2 ⋅⋅⋅ 

T0 ⋅  a1 a2  ⋅  = +1
 z a1 z a2 ⋅⋅⋅ z f1 z f 2 ⋅⋅⋅   s − pa1 s − pa2 ⋅⋅⋅ s − p f1 s − p f 2 ⋅⋅⋅ 

and

 ∠(s − z a1) + ∠(s − z a2 ) + ⋅⋅ ⋅ + ∠(s − z f1) + ∠(s − z f 2 ) + ⋅⋅⋅

−  ∠(s − pa1) + ∠(s − pa2 ) + ⋅⋅⋅ + ∠(s − p f1) + ∠(s − p f 2 ) + ⋅ ⋅⋅
= 2nπ

B. Murmann EE214B Winter 2013-14 – Chapter 10 11

The rules for constructing the root locus are based on the phase
condition. The magnitude condition determines where, for a
given T0, the poles of A(s) actually lie on along the locus.

To determine if a point X in the s-plane lies on the root locus, draw

vectors from the poles and zeros of T(s) to the point X. The
angles of these vectors are then used to check the phase
condition.

B. Murmann EE214B Winter 2013-14 – Chapter 10 12

 Root-Locus Construction Rules

Rule 1: Branches of the root locus start at the poles of T(s), where T0 = 0, and
terminate on the zeros of T(s), where T0 = ∞. If T(s) has more poles
than zeros, some branches terminate at infinity.

Rule 2: If T(s) has all its zeros in the LHP or if T(s) has an even number of
RHP zeros, the locus is situated along the real axis wherever there is
an odd number of poles and zeros of T(s) to the right. If T(s) has an
odd number of RHP zeros, the locus is situated along the real axis
wherever there is an even number of poles and zeros of T(s) to the
right.

Rule 3: All segments of the locus on the real axis between pairs of poles, or
pairs of zeros, must branch out from the real axis.

Rule 4: The locus is symmetric with respect to the real axis because complex
roots occur only in conjugate pairs.

B. Murmann EE214B Winter 2013-14 – Chapter 10 13

Rule 5: Branches leaving the real axis do so at right angles to it.

Rule 6: Branches break away from the real axis at points where
the vector sum of reciprocals of distances to the poles of
T(s) equals the vector sum of reciprocals of distances to
the zeros of T(s).

Rule 7: Branches that terminate at infinity do so asymptotically to

straight lines with angles to the real axis of
(2n –1)π/(Np – Nz),
where Np = # of poles of T(s) and Nz = # of zeros of T(s).

Rule 8: The asymptotes of the branches terminating at infinity all

intersect the real axis at a single point given by

σa =
[ ] [
Σ poles of T(s) − Σ zeros of T(s) ]
Np − Nz

B. Murmann EE214B Winter 2013-14 – Chapter 10 14

 Example: Root Locus for Narrowbanding Compensation

T0

Problem statement
– For the given low-frequency loop gain T0 and high-frequency pole
ωp2, find the proper value of ωp1 that gives a maximally flat magnitude
response for the closed-loop amplifier

B. Murmann EE214B Winter 2013-14 – Chapter 10 15

From rules 1 and 2, we know that

the root locus includes the real axis
between p1 and p2

According to rule 6, the breakaway
point from the axis follows from
1 1
௜  0
௜  ଵ ௜  ଵ
ଵ  ଶ
௜ 
2

Rules 7 and 8 indicate that the
asymptotes lie at 90 degrees to the
real axis and meet the axis at σi

B. Murmann EE214B Winter 2013-14 – Chapter 10 16


To find the point where the poles lie
at an angle of 45 degrees, we invoke
the magnitude condition

ଵ ଶ
଴ 1

 ଵ |
 ଶ |

If we approximate |p1| << |p2|, then

ଶ
௜ ௜ ≅
2
|ଶ |

 ଵ  |
 ଶ | ≅ 2
2
ଵ ଶ 1 |ଶ |
଴ 1 ଵ 
ଶ ଶ 2 ଴
2
1 ௣ଶ
௣ଵ 
2 ଴

B. Murmann EE214B Winter 2013-14 – Chapter 10 17

Example: Root Locus for Feedback Zero Compensation

T0

Problem statement
– For the given low-frequency loop gain and poles of a(s), find the
proper position of the feedback zero that gives a maximally flat
response

B. Murmann EE214B Winter 2013-14 – Chapter 10 18

 zF

From rules 1 and 2, we know that the root locus lies between p1 and p2
and also to the left of zF

Applying rule 6 gives two breakpoints, one between p1 and p2, and one
where the poles return to the real axis after circling around z

In general, the locus tends to bend toward zeros as if attracted and
tends to bend away from poles as if repelled

B. Murmann EE214B Winter 2013-14 – Chapter 10 19

If zF is remote from p1 and p2, then

p1 + p 2
σi =
jω 2

If |zF| >> |σi|, and assuming 45 degree

ω0 angles, we have
σi
ω0 = 2 zF
zF p2 σ
45º p1

The magnitude condition then gives

2
s1 − p1 s2 − p2 ω02 2 zF
T0 = = =
p1 p2 p1 p2 p1 p2

1
ωz = T0ωp1ωp2
2

B. Murmann EE214B Winter 2013-14 – Chapter 10 20

 Root Locus With a Third Pole

The above-computed results can be affected by a high-frequency third

pole, mandating a certain amount of “tweaking”

B. Murmann EE214B Winter 2013-14 – Chapter 10 21

“Phantom Zero”

Feedback zero compensation is also called “phantom zero”

compensation since the feedback zero affects the root locus, but does
not appear as a zero of the overall amplifier

The zero in the root locus plot is contributed by f(s) and is not a zero of
the overall feedback amplifier
– Recall that the zeros of the overall feedback amplifier are the zeros
of basic amplifier a(s) and the poles of feedback network f(s)

If the zero in T(s) was contributed by a(s), it would also appear as a zero
in the overall amplifier

A(s) with a A(s) with a

zero in f(s) zero in a(s)

B. Murmann EE214B Winter 2013-14 – Chapter 10 22

 Root Locus Example in Matlab

s = tf('s');
p1=-1; p2=-2; p3=-4;
T = 1 / [(1-s/p1)*(1-s/p2)*(1-/p3)]
rlocus(T)
Root Locus
10

2
Imaginary Axis

-2

-4

-6

-8

-10
-14 -12 -10 -8 -6 -4 -2 0 2 4
Real Axis

B. Murmann EE214B Winter 2013-14 – Chapter 10 23

Adding a Zero
s = tf('s');
z=-5; p1=-1; p2=-2; p3=-4;
T = (1-s/z) / [(1-s/p1)*(1-s/p2)*(1-s/p3)]
rlocus(T)
Root Locus
15

10

5 This example
visualizes how
Imaginary Axis

0
introducing a zero in
T(s) can be used to
-5
stabilize a feedback
amplifier with three
poles.
-10

-15
-6 -5 -4 -3 -2 -1 0 1
Real Axis

B. Murmann EE214B Winter 2013-14 – Chapter 10 24

 Minor Issue with Root Locus Plots for Circuit Design

In a root locus plot, it is implicitly assumed that we can change T0

without affecting the poles of the amplifier

This is almost never true for practical circuits
– Example: Changing the DC gain of a common source stage by
increasing its drain resistance also changes its output pole; the gain-
bandwidth product remains constant

In principle, we could fix this issue by re-parameterizing the root locus
plot using circuit parameters
– Example: Plot the root locus as a function of drain resistance (rather
than T0)

However, this is not needed, since all we want from the root locus is
– Gain qualitative insight on the general movement of poles, eye-ball
ways to stabilize the amplifier, etc.
– Gain quantitative insight for one single point in the diagram, e.g. find
the conditions for an MFM response
• This works irrespective of the above-raised issue

B. Murmann EE214B Winter 2013-14 – Chapter 10 25

Overview: Frequency Compensation Techniques

So far, we have seen two methods for frequency compensation

– Narrowbanding
– Feedback zero compensation

We will now broaden the picture by inspecting a few additional

techniques that find their use in practice
– Miller compensation
– Ahuja compensation
– Nested Miller compensation
– Feedforward compensation

Many more techniques exist

B. Murmann EE214B Winter 2013-14 – Chapter 10 26

 Building Blocks

Transconductor
-gm (e.g. CS or CE stage, differential pair)

gm Current Buffer
(CG or CB stage)
1/gm

1/gm
Voltage Buffer
Av 1
(CD or CC stage)

B. Murmann EE214B Winter 2013-14 – Chapter 10 27

Re-cap: Narrowbanding Compensation

T0

Idea
– Make one of the loop poles dominant, leave other poles unchanged

B. Murmann EE214B Winter 2013-14 – Chapter 10 28

 Re-cap: Feedback Zero Compensation

T0

Leave amplifier poles unchanged and introduce a zero in the feedback

network

B. Murmann EE214B Winter 2013-14 – Chapter 10 29

Benchmarking

In order to compare the merit of various compensation techniques, it

makes sense to inspect the loop’s unity gain frequency before and after
the compensation is applied

Rationale: The maximum bandwidth we can possibly expect from a
feedback amplifier is the unity gain frequency of the loop
– Regardless of the order of the feedback system, the closed-loop
response departs from 1/f as |T(s)| crosses unity



≫ 1

=  

1 + 
(
)
≅
≅ 

≪ 1

B. Murmann EE214B Winter 2013-14 – Chapter 10 30

 Loop Gain Pole Product (LP Product)

Consider a loop transfer function with n “dominant” poles that occur

before the unity crossover

଴

=

T଴
=
1− 1− … 1−
s୬
1 + ⋯+ p p …p
ଵ ଶ ௡ ଵ ଶ ୬

௨ ≅ ଴ |pଵ ||pଶ | … |p୬ | = 

೙ ೙

The product of the low frequency loop gain and all dominant poles is
called the loop gain pole product (LP product)
– Nordholt, Design of High-Performance Negative-Feedback
Amplifiers, 1983

Note that in a first-order system, the LP product is simply the gain-
bandwidth product

B. Murmann EE214B Winter 2013-14 – Chapter 10 31

Efficiency of Feedback Zero Compensation

଴
T0 T0

ଶ
≅
௣ଵ ௣ଶ

௨ ≅ ଴ ௣ଵ ௣ଶ ௨ ≅ ଴ ௣ଵ ௣ଶ

To first order, since we do not change the poles, the LP product and ωu
are (approximately) unchanged
– Feedback zero compensation is therefore bandwidth efficient, since
we do not need to sacrifice bandwidth to stabilize the circuit

To second order, and LP product will change slightly due to loading from
the capacitance added in the feedback network

B. Murmann EE214B Winter 2013-14 – Chapter 10 32

 Efficiency of Narrowbanding

T0
௨ ≅ ଴ ௣ଵ ௣ଶ

௨ᇱ ≅ ଴ ௣ଵ ≅ ௣ଶ
1
2

The crossover and bandwidth is limited to some fraction of ωp2

At first glance, this makes narrowbanding appear to be inefficient

However, provided that ωp2 is close to the transit frequency of the
process technology, this compensation approach is acceptable and hard
to surpass in terms of absolute achievable closed-loop speed

B. Murmann EE214B Winter 2013-14 – Chapter 10 33

Example: Single Gain Stage with Current Buffer

Consider the amplifier a(s) shown below

– Cgs introduces a non-dominant pole at high frequencies ωp2 = ωT
– CL is adjusted until the circuit achieves the desired phase margin

This type of narrowbanding is called “load compensation,” since stability is
ensured by properly sizing the load capacitance CL

-gm gm
Cgs CL
1/gm

B. Murmann EE214B Winter 2013-14 – Chapter 10 34

 Example Realizations

Folded Cascode OTA

Telescopic OTA

(Common mode
feedback circuits not
shown – see EE315A)

B. Murmann EE214B Winter 2013-14 – Chapter 10 35

Two-Stage OTA

The two-stage amplifier shown below has two comparable poles

– Assuming that there is no additional significant pole from the
feedback network

If the feedback network is resistive, we may be able to compensate the
amplifier by introducing a feedback zero

What can we do if the feedback is capacitive?

Narrowbanding is not a good idea, since both poles are at low
frequencies

B. Murmann EE214B Winter 2013-14 – Chapter 10 36

 Miller Compensation

Cc

gm1 -gm2
C1 R1 C2 R2

Purposely connect a capacitor across the second transconductor

Two interesting things happen
– Low frequency input capacitance of second stage becomes large –
moves the first pole to a lower frequency
– Qualitatively speaking, at high frequencies, Cc turns the second
stage into a “diode connected device” – low impedance, i.e. large ωp2

B. Murmann EE214B Winter 2013-14 – Chapter 10 37

From the general CS/CE stage analysis of handout 4 we have (after

proper variable substitution)

1
p1 ≅ −
R1 C1 + Cc (1 + gm2R2 ) + R2 (C2 + Cc )
gm2
z=+
CC
R1 C1 + Cc (1 + gmR2 ) + R2 (C2 + Cc )
p2 ≅ − RHP zero
R1 R2 (C1C2 + C1Cc + C2Cc )

We can approximate further as shown below

 C1C2 
gm2Cc 1  C C   C + C2 
1
ωp1 ≅ ωp2 ≅ ≅  1 + 2  1 + 1 
gm2R2 R1CC C1C2 + Cc (C1 + C2 ) ωp2  gm2 gm2   Cc 
 
 

B. Murmann EE214B Winter 2013-14 – Chapter 10 38

 “Pole Splitting”

Increasing Cc reduces ωp1, and increases ωp2

− A very nice “knob” for adjusting the phase margin of the circuit

c c

B. Murmann EE214B Winter 2013-14 – Chapter 10 39

Intuitive Derivation of Pole Split Using a Two-Port Model for

the Inner Loop

a(s):
-gm2
C1+Cc R1 C2+Cc R2

Mag ( jω ) gm2R2R1
a(s) a(s) = −
(1 + sR1 [C1 + Cc ]) (1 + sR2 [C2 + Cc ])
1
f(s) = −sCf
f(s)
ω

Miller compensation is “reasonably” bandwidth efficient

There is a somewhat significant bandwidth loss because the LP product
of the original poles is reduced due to loading from Cc
B. Murmann EE214B Winter 2013-14 – Chapter 10 40
 RHP Zero

Unfortunately, the right half plane zero due to Cc can destroy the PM

RHP LHP

ωz −ωz

ω ω
1− j → − 90
1+ j → + 90

ωz ωz
Phase Phase
ωz ω
0° + 90°
− 45° + 45°
− 90° 0°
ωz ω

B. Murmann EE214B Winter 2013-14 – Chapter 10 41

Issue with RHP Zero

• RHP zero can destroy

the phase margin if it
occurs before or near
the crossover
ωz frequency

B. Murmann EE214B Winter 2013-14 – Chapter 10 42

 Mitigating the Impact of RHP Zero

Somehow create “unilateral” feedback through Cc

– Source follower from output to drive Cc
• Additional power & swing reduction issues
– Introduce a nulling resistor
• Most popular approach
– Ahuja compensation (also called cascode compensation)
• Ahuja, IEEE JSSC, 12/1983
• Ribner, IEEE JSSC, 12/1984

B. Murmann EE214B Winter 2013-14 – Chapter 10 43

Nulling Resistor

Rz Cc

gm1 -gm2
C1 R1 C2 R2

The new transfer function becomes

 1 
1 − sCc  − Rz 
a ( s ) ≅ av0 ⋅  gm2 
 s  s   s 
1 −  ⋅ 1 −  ⋅ 1 − 
 p1   p2   p3 

• p1 and p2 unchanged, new pole p3, and a “knob” to tune the zero

B. Murmann EE214B Winter 2013-14 – Chapter 10 44

 Implementation Example

Text, page 243

B. Murmann EE214B Winter 2013-14 – Chapter 10 45

Rz = 1/gm2 pushes the zero to +∞

Rz ≅ (1+C2/Cc)/gm2 places the zero such that it cancels p2!

B. Murmann EE214B Winter 2013-14 – Chapter 10 46

 Third Pole

1
ωp3 ≅
R z C1

gm2

For Rz = 1/gm2 ωp3 ≅ ≅ ωT
C1

gm2 ωT

For Rz = (1+C2/Cc)/gm2 ωp3 ≅ ≅
 C2   C2 
1+  C1 1+ 
 Cc   Cc 

Thus, as we try to cancel the second pole, the third pole moves to a
lower frequency, and may move to a frequency that is comparable to
the original ωp2 before cancellation

My recommendation: Simply push the zero to infinity

The textbook’s recommendation: Spice-monkey the zero into the LHP
and try to squeeze out some phase margin

B. Murmann EE214B Winter 2013-14 – Chapter 10 47

Process Insensitive Implementation of Rz

gm=KVOV
Text, page 260

Ron=1/(KVOV)=1/gm

B. Murmann EE214B Winter 2013-14 – Chapter 10 48

 Ahuja Compensation
1

=
1 1
1/gma  + 
௠௔ ௖

gma
Cc

gm1 -gm2
C1 R1 C2 R2

Idea: insert a current buffer (instead of Rz) to obtain unilateral feedback

This removes the feedforward zero and leads to a smaller LP product
degradation than in plain Miller compensation
– We can see this from the two-port model of the inner loop

B. Murmann EE214B Winter 2013-14 – Chapter 10 49

Two-Port Model of Inner Loop

1

 =−
1 1
 + 
௠௔ ௖

௖

 =−
௖
1 + 
௠௔

Good news: Cc does not contribute extra loading at the input

– Less LP product degradation than Miller compensation

Bad news: f(s) of the inner loop contains a pole
– Bad for stability of the inner loop

B. Murmann EE214B Winter 2013-14 – Chapter 10 50

 Possible Scenarios
Pole in f(s) occurs after Pole in f(s) occurs before
crossover of inner loop: crossover of inner loop:

Mag ( jω ) Mag ( jω )
a(s) a(s)

1 1
f(s) gma/Cc f(s)
ω ω
gma/Cc

Inner loop has no phase margin!

Expect peaking, complex poles in the amplifier
even before outer feedback is applied

Ahuja compensation is somewhat harder to design, but can bring

significant benefits when used properly

B. Murmann EE214B Winter 2013-14 – Chapter 10 51

Implementation Options

P.J. Hurst et al. "Miller compensation using current

buffers in fully differential CMOS two-stage
operational amplifiers,“ IEEE Transactions
on Circuits and Systems I, vol.51, no.2, pp. 275-
285, Feb. 2004.

B. Murmann EE214B Winter 2013-14 – Chapter 10 52

 Nested Miller Compensation

Mag ( jω ) Cm2
Cm1

gm1, gm2

gm0, gm1, gm2

B. Murmann EE214B Winter 2013-14 – Chapter 10 53

Feedforward Compensation

[e.g. Thandri, JSSC 2/2003]

Parallel path through gm3 dominates

|a(jω)|
transfer function at high frequencies
and returns the circuit behavior back
to first order

ω

Very large achievable bandwidth
|p1| |p2| |z1|

Potential issue
φ(jω)
ω
– The doublet p1, z1 can make it
– π/2 difficult to achieve a fast
–π transient response
• See Kamath, JSSC 12/1974

B. Murmann EE214B Winter 2013-14 – Chapter 10 54

 Issues with Pole-Zero Doublet (1)

B.Y.T. Kamath, R.G. Meyer and P.R. Gray, "Relationship between frequency response and
settling time of operational amplifiers," IEEE JSSC, Vol. 9, No. 6, pp.347–352, Dec. 1974.

B. Murmann EE214B Winter 2013-14 – Chapter 10 55

Issues with Pole-Zero Doublet (2)

For fast and accurate settling, need either small

pole-zero spacing or large wz

B.Y.T. Kamath, R.G. Meyer and P.R. Gray, "Relationship between frequency response and
settling time of operational amplifiers," IEEE JSSC, Vol. 9, No. 6, pp.347–352, Dec. 1974.

B. Murmann EE214B Winter 2013-14 – Chapter 10 56

 Recent Example of a Feedforward OTA

[Shibata et al., JSSC 12/2012]

B. Murmann EE214B Winter 2013-14 – Chapter 10 57

Summary

Technique Internal External Lead Lag Comments

Narrowbanding X X X Practical mostly in single-stage

amplifiers
Feedback zero X X Preferred method whenever
applicable; highest bandwidth
efficiency
Miller X X Easy to design and robust
when zero is moved to infinity
Ahuja X X Hard to design, but potentially
large gains in achievable
bandwidth
Feedforward X X Do not use in circuits that
demand fast and precise
transient settling

B. Murmann EE214B Winter 2013-14 – Chapter 10 58

 Aside: Slewing

All of our analyses have been concerned with the small-signal behavior
of feedback amplifiers at high frequencies

Sometimes the behavior with large input signals (either step inputs or
sinusoidal signals) is also of interest
– See e.g. switched capacitor circuits in EE315A

Consider a step applied to an amplifier in unity gain feedback

B. Murmann EE214B Winter 2013-14 – Chapter 10 59

Output Response – Expected versus Actual

B. Murmann EE214B Winter 2013-14 – Chapter 10 60

 Maximum Rate of Output Change for a Two-Stage Amplifier

Slew Rate

B. Murmann EE214B Winter 2013-14 – Chapter 10 61

 Chapter 11
Low Frequency Distortion Analysis

Boris Murmann
Stanford University
Winter 2013-14

Textbook Sections: 9.5

Introduction

All electronic circuits exhibit some level of nonlinear behavior

– The resulting waveform distortion is not captured in small-signal
circuit models

We will begin by looking at the basic tools needed to analyze
“memoryless” nonlinearities, i.e. nonlinearities that can be represented
by a frequency independent model
– Such models are valid in a frequency range where all capacitances
and inductances in the circuit of interest can be ignored

As a driving example, we will analyze the nonlinearity in the V-I
transduction of BJTs and MOSFETs

The general approach taken is to model the nonlinearities via a power
series that links the input and output of the circuit
– This approach is useful and accurate for the case of “small distortion”
and cannot be used to predict the effect of gross distortion, e.g. due
to signal clipping

B. Murmann EE214 Winter 2013-14 – Chapter 11 2

 Small-Signal AC Model

Io = IOQ + io io

+ gm⋅vi
+
Vi = VIQ + vi vi
-
dIo -
gm =
dVi V = V
i IQ

Io = f(Vi) = f '(VIQ ) io

gm gm
vi

Vi
VIQ

B. Murmann EE214 Winter 2013-14 – Chapter 11 3

Taylor Series Model

(3)
f '(VIQ ) f ''(VIQ ) 2 f (VIQ )
f(Vi ) = f(VIQ ) + (Vi − VIQ ) + (Vi − VIQ ) + (Vi − VIQ )3 + ...
1! 2! 3!

f2(Vi)

f3(Vi)

f(Vi)

f2(Vi)

Vi
VIQ
f3(Vi)

B. Murmann EE214 Winter 2013-14 – Chapter 11 4

 Relationship Between Incremental Variables

Using vi = Vi − VIQ and io = Io − IOQ = f(Vi ) − f(VIQ )

we obtain io = a1v i + a2 v i2 + a3 v i3 + ...

f (m) (VIQ )
where am =
m!

1 ' 1 ''

Note that a1 ≡ gm a2 ≡ gm a3 ≡ gm
2 6

In practice, it is often sufficient to work with a truncated nth order power

series
io ≅ a1v i + a2 v i2 + ... + an v in

B. Murmann EE214 Winter 2013-14 – Chapter 11 5

Graphical Illustration
io

n=2
vi

n→∞

n=3

A model that relates the incremental signal components (vi, io) though a
nonlinear expression is sometimes called “large-signal AC model”

The accuracy of a truncated power series model depends on the signal
range and the curvature of the actual transfer function
– Using a higher order series generally helps, but also makes the
analysis more complex
– As we will see, using a third order series is often sufficient to model
the relevant distortion effects in practical, weakly nonlinear circuits

B. Murmann EE214 Winter 2013-14 – Chapter 11 6

 Harmonic Distortion Analysis

Apply a sinusoidal signal and collect harmonic terms in the output signal

v i = vˆ i ⋅ cos ( ω t )
2 3
io = a1vˆ i cos ( ω t ) + a2  vˆ i cos ( ω t )  + a3  vˆ i cos ( ω t )  + ...

1 1
cos2 ( α ) = cos ( 2α ) + 1 cos3 ( α ) = cos ( 3α ) + 3 cos ( α ) 
2 4

1  DC shift
∴ io =  a2 vˆ i2 
 2 

 3 
+ a1vˆ i + a3 vˆ i3  cos ( ω t ) Fundamental
 4 

1  1 
+  a2 vˆ i2  cos ( 2ω t ) +  a3 vˆ i3  cos ( 3ω t ) + ... Harmonics
2  4 

B. Murmann EE214 Winter 2013-14 – Chapter 11 7

Observations

The quadratic term (a2) give rises to an undesired second harmonic tone
and a DC shift

The cubic term (a3) give rises to an undesired third harmonic tone and it
also modifies the amplitude of the fundamental
– a3 < 0  “gain compression”
– a3 > 0  “gain expansion”

y x + 0.3x3
x

x - 0.3x3

B. Murmann EE214 Winter 2013-14 – Chapter 11 8

 Waveforms with Gain Expansion

x = cos ( 2πt ) a1 = 1 a3 = 0.3

B. Murmann EE214 Winter 2013-14 – Chapter 11 9

Waveforms with Gain Compression

x = cos ( 2πt ) a1 = 1 a3 = −0.3

B. Murmann EE214 Winter 2013-14 – Chapter 11 10

 Higher Order Terms

m
1 m 1 m − j( m − k ) α
cosm ( α ) =
2 m ( e jα + e − jα ) =
2m ∑k 
e jkα e
k =0  

1
cos4 ( α ) = cos ( 4α ) + 4cos ( 2α ) + 3 
8

1
cos5 ( α ) = cos ( 5α ) + 5 cos ( 3α ) + 10cos ( α ) 
16 

Can show that

– Terms raised to even powers of m affect the DC shift and even
harmonics up to m
– Terms raised to odd powers of m affect the fundamental and odd
harmonics up to m

B. Murmann EE214 Winter 2013-14 – Chapter 11 11

Inspection of 4th and 5th Order Contributions

1 3 
As long as
∴ io =  a2 vˆ i2 + a4 vˆ i4 
2 8 
a 4 vˆ i4 << a2 vˆ i2 and a5 vˆ i5 << a3 vˆ i3
 3 5 
+ a1vˆ i + a3 vˆ i3 + a5 vˆ i5  cos ( ω t )
 4 16 
or equivalently
1 1 
+  a2 vˆ i2 + a 4 vˆ i4  cos ( 2ω t )
2 2  a2 a3
vˆ i << and vˆ i <<
1 5  a4 a5
+  a3 vˆ i3 + a5 vˆ i5  cos ( 3ω t )
4 16 
the 4th and 5th order terms can
1  be neglected
+  a4 vˆ i4  cos ( 4ω t )
8 

This condition is usually met in
1 
+  a5 vˆ i5  cos ( 5ω t ) practical, weakly nonlinear
 16  circuits

B. Murmann EE214 Winter 2013-14 – Chapter 11 12

 Fractional Harmonic Distortion Metrics

amplitude of second harmonic distortion signal

HD2 =
amplitude of fundamental
amplitude of third harmonic distortion signal
HD3 =
amplitude of fundamental

Including only contributions from terms up to 3rd order, these quantities

become
1
a2 vˆ i2
2 1 a2
HD2 ≅ ≅ vˆ i
3 3 2 a
ˆ
a1vi + a3 v i ˆ 1
4
1
a3 vˆ i3
4 1 a3 2
HD3 ≅ ≅ vˆ i
3 3 4 a
a1vˆ i + a3 vˆ i 1
4

B. Murmann EE214 Winter 2013-14 – Chapter 11 13

Total Harmonic Distortion

total power of distortion signals

THD =
power of fundamental

= HD22 + HD32 + HD24 + ...

THD is often dominated by the HD2 and/or HD3 term

Typical application requirements
– Telephone audio: THD < ~10%
– Video: THD < ~1%
– RF low noise amplifiers: THD < ~0.1%
– High quality audio: THD < ~0.01%

B. Murmann EE214 Winter 2013-14 – Chapter 11 14

 Intermodulation Distortion (1)

Consider applying two tones to the nonlinear device

v i = vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω2 t )

io = a1  vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω 2 t ) 

2
+a2  vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω2 t ) 

3
+a3  vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω2 t )  + ...

Inspect second-order term

2 2
a2  vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω2 t )  = a2  vˆ i1 ⋅ cos ( ω1t ) 
Causes HD
2
+a2  vˆ i2 ⋅ cos ( ω 2 t ) 

+2a2  vˆ i1vˆ i2 ⋅ cos ( ω1t ) cos ( ω 2 t )  New

B. Murmann EE214 Winter 2013-14 – Chapter 11 15

Second-Order Intermodulation

2a2  vˆ i1vˆ i2 ⋅ cos ( ω1t ) cos ( ω2 t )  = a2 vˆ i1vˆ i2 cos ({ω1 + ω 2 } t ) + cos ({ω1 − ω 2 } t ) 

The output will contain tones at the sums and differences of the applied
frequencies

We define the fractional second-order intermodulation as

amplitude of second-order IM components (for vˆ i1 = vˆ i2 = vˆ i )

IM2 =
amplitude of fundamentals

a2 vˆ i2 a2
= = v̂i
a1 vˆ i a1

= 2HD2

B. Murmann EE214 Winter 2013-14 – Chapter 11 16

 Third-Order Intermodulation (1)

3 3
a3  vˆ i1 ⋅ cos ( ω1t ) + vˆ i2 ⋅ cos ( ω 2 t )  = a3  vˆ i1 ⋅ cos ( ω1t ) 
Causes HD
3
+a3  vˆ i2 ⋅ cos ( ω 2 t ) 

+3a3  vˆ i1vˆ i2
2
⋅ cos ( ω1t ) cos2 ( ω2 t ) 
 
New
+3a3  vˆ i1
2ˆ
v i2 ⋅ cos2 ( ω1t ) cos ( ω2 t ) 
 

3a3  vˆ i1vˆ i2
2
⋅ cos ( ω1t ) cos2 ( ω 2 t ) 
 
3 2  
=
4
a3 vˆ i1vˆ i2 2cos ( ω1t ) + cos ({2ω2 − ω1} t ) + cos ({2ω 2 + ω1} t ) 

“Gain desensitization term” Third-order

For a3<0, large vi2 reduces Intermodulation
fundamental tone due to vi1 Products

B. Murmann EE214 Winter 2013-14 – Chapter 11 17

Third-Order Intermodulation (2)

Third-order intermodulation products appear at (2ω2 ± ω1) and (2ω1 ± ω2)

We define the fractional third-order intermodulation as

amplitude of third-order IM components (for vˆ i1 = vˆ i2 = vˆ i )

IM3 =
amplitude of fundamentals

3 a3 vˆ i3 3 a3 2
= = v̂i = 3HD3
4 a1 vˆ i 4 a1

Note that for ω2 ≅ ω1, the third-order

intermodulation products are close to the
original frequencies and cannot be
filtered out
– This is a significant issue in
narrowband systems

B. Murmann EE214 Winter 2013-14 – Chapter 11 18

 Distortion in a CE Stage (1)

Vbe Vbe
kT dIc I
Ic = Ise VT VT = a1 = = s e VT
q dVbe VT
Vbe = VBEQ
Vbe = VBEQ

ICQ
= ≡ gm
VT

1 d2Ic 1 ICQ
a2 = 2
=
2 dVbe 2 VT2
Vbe = VBEQ

1 ICQ
am =
m! VTm

B. Murmann EE214 Winter 2013-14 – Chapter 11 19

Distortion in a CE Stage (2)

2
1 a2 1 vˆ be 1 a3 2 1  vˆ be 
HD2 ≅ vˆ be = HD3 ≅ vˆ be =  
2 a1 4 VT 4 a1 24  VT 

Low distortion in the collector current requires the B-E voltage excursion
to be much smaller than VT ≅ 26mV

Checking for the valid range of a third order model yields

a2 a3
vˆ be << = 12VT and vˆ be << = 20VT
a4 a5

For a B-E voltage swing of VT, we have

HD2 ≅ 25% HD3 ≅ 4.17%

Note that a typical application will demand much lower distortion

B. Murmann EE214 Winter 2013-14 – Chapter 11 20

 Simulation Example
.include
/usr/class/ee214b/hspice/ee214_hspice.sp
q1 c b 0 npn214
vc c 0 1
vb b 0 sin (0.7 26m 1meg)
.op
.tran 1n 20u
.fourier 1meg i(vc)
.options post brief accurate delmax = 10n
.end

element 0:q1 fourier components of transient response i(vc)

model 0:npn214
dc component = -2.75315e-05
ib 72.4210n
ic 21.7276u harmonic frequency fourier normalized phase normalized
vbe 700.0000m no (hz) component component (deg) phase (deg)
vce 1.0000 1 1.00000x 24.6708u 1.00000 179.998 0.
vbc -300.0000m 2 2.00000x 5.91637u 239.813m 89.9948 -90.0032
vs -998.6963m 3 3.00000x 953.092n 38.6324m -16.6414m -180.015
power 21.7783u 4 4.00000x 113.221n 4.58926m -90.0393 -270.037
betad 300.0183 5 5.00000x 10.2412n 415.113u 179.922 -76.1163m
gm 842.7150u 6 6.00000x 681.044p 27.6052u 89.8697 -90.1284
rpi 354.7570k 7 7.00000x 25.1855p 1.02086u 74.7880m -179.923
rx 25.0000 8 8.00000x 1.30730p 52.9898n 87.5824 -92.4156
ro 4.1559x 9 9.00000x 297.603f 12.0629n 17.1666 -162.831
cpi 8.9254f total harmonic distortion = 24.2948 percent
…

B. Murmann EE214 Winter 2013-14 – Chapter 11 21

Distortion in a CS Stage (1)

1 W 2 dId W
Id =
2
µCox
L
(
Vgs − Vt ) a1 =
dVgs
= µCox
L
(
Vgs − Vt )
Vgs = VGSQ Vgs = VGSQ

W 2I
= µCox VOV = DQ ≡ gm
L VOV

1 d2Id 1 W IDQ
a2 = 2
= µCox = 2
2 dVgs 2 L VOV
Vgs = VGSQ

a3 = 0

B. Murmann EE214 Winter 2013-14 – Chapter 11 22

 Distortion in a CS Stage (2)

1 a2 1 v̂ gs
HD2 ≅ vˆ gs = HD3 = 0
2 a1 4 VOV

Small second harmonic distortion in the drain current requires the G-S
voltage excursion to be much smaller than the quiescent point gate
overdrive (VOV=VGS-Vt)

An idealized square-law device does not introduce high order distortion
– However, this is not true for a real short-channel MOSFET

Relevant effects
– Velocity saturation, mobility reduction due to vertical field
– Biasing in moderate or weak inversion
– Nonlinearity in the device’s output conductance
– F

B. Murmann EE214 Winter 2013-14 – Chapter 11 23

Distortion in Modern MOSFETS

Distortion in modern MOSFET devices is generally hard to model

accurately

A basic approach for devices operating in strong inversion is to include
short channel effects via basic extensions to the square law model
– E.g. model velocity saturation as resistive source degeneration
– See e.g. Terrovitis & Meyer, JSCC 10/2000

Another approach is to extract the coefficients from “known-to-be-
accurate” Spice models
– Find coefficients am by simulating the derivatives of I-V curves
– See e.g. Blaakmeer et al., JSSC 6/2008

Unfortunately, generating accurate Spice models for MOSFET distortion
is a very difficult task
– See e.g. R. van Langevelde et al., IEDM 2000

Never trust a Spice model blindly!

B. Murmann EE214 Winter 2013-14 – Chapter 11 24

 Extracting Distortion Coefficients of EE214B NMOS Device

B. Murmann EE214 Winter 2013-14 – Chapter 11 25

Relationship to gm/ID

We can obtain reasonable estimates/bounds for a MOSFET’s distortion

using the transistor’s gm/ID in the operating point
Square Law Weak Inversion
VGS
2
ID = K ( VGS − Vt ) nVT
ID = I0e
'
ID = 2K ( VGS − Vt ) = gm VGS
I
''
'
ID = 0 e nVT = gm
ID = 2K nVT

1 '' VGS
I0
a2 2 ID 1 1 gm ''
ID = e nVT

a1
= ' =
ID
=
2 ( VGS − Vt ) 4 ID (nVT )2
1 ''

In strong inversion, 2/(gm/ID) can a2 2 ID 1 1 gm
be used as an estimate for “VOV” in = ' = =
distortion calculations
a1 ID 2nVT 2 ID

B. Murmann EE214 Winter 2013-14 – Chapter 11 26

 Simulation Data

NMOS, L = 0.18µm, VDS = 0.9V

0.8

0.7

0.6
Weak Inversion
a2/a1 / (gm/I D) 0.5
Approximation
Square Law
0.4 Approximation
0.3

0.2

0.1 Velocity Saturation

0
5 10 15 20 25
gm /I D [S/A]

For the low-distortion region (small gm/ID), it is OK to use the square-law

approximation for first cut design

B. Murmann EE214 Winter 2013-14 – Chapter 11 27

Simulation Example
.include /usr/class/ee214b/hspice/ee214_hspice.sp
m1 d g s s nmos214 w=34u l=0.18u
௠ 
= 10 ௚௦ = 50

vd d 0 1 ஽ 
vg g 0 sin (0.6 50m 1meg)
c1 s 0 1 Expected:
ib s 0 1m
.op 1 ௚௦
.tran 1n 20u ଶ ≅ = 6.25%
.fourier 1meg i(vd) 4 2/(
௠ /஽ )
.options post brief accurate delmax = 10n
.end

fourier components of transient response i(vd)

element 0:m1 dc component = -0.00102773
model 0:nmos214
region Saturati harmonic frequency fourier normalized phase normalized
id 1.0000m no (hz) component component (deg) phase (deg)
vgs 665.2146m 1 1.00000x 494.448u 1.00000 179.999 0.
vds 1.0652 2 2.00000x 27.7272u 56.0770m 89.9952 -90.0036
vbs 0. 3 3.00000x 1.46986u 2.97273m 179.986 -12.7111m
vth 484.8771m 4 4.00000x 3.10325n 6.27619u 89.8778 -90.1210
vdsat 137.9596m 5 5.00000x 13.3632n 27.0265u -179.927 -359.925
vod 180.3375m 6 6.00000x 1.28017n 2.58909u -90.4216 -270.420
gm 9.9785m 7 7.00000x 33.1378p 67.0198n -111.907 -291.906
gds 265.9749u 8 8.00000x 76.9550p 155.638n -100.995 -280.994
gmb 2.3549m 9 9.00000x 33.7118p 68.1807n -71.0912 -251.090
…
total harmonic distortion = 5.61557 percent

B. Murmann EE214 Winter 2013-14 – Chapter 11 28

 Distortion in a BJT Differential Pair (1)

 V 
Icd = Ic1 − Ic2 = αIEE tanh  id 
 2VT 
Ic1 Ic2
1 3 2 5
tanh ( x ) = x − x + x − +...
3 15
+
Vid
αIEE αIEE αIEE
- a1 = ≡ Gm a3 = − a5 =
2VT 24VT3 240VT5
IEE

Third-order model is accurate for

a3
v̂id << = 10VT
a5

B. Murmann EE214 Winter 2013-14 – Chapter 11 29

Distortion in a BJT Differential Pair (2)

A differential pair with perfectly matched transistors does not generate

any even-order distortion products

Any mismatch (e.g. in Is) will cause non-zero even-order terms
– The resulting even order distortion products are typically smaller than
the inherent odd-order distortion

The HD3 performance of a BJT differential pair is better than that of a

single BJT transistor

2 2
1 a3 2 1  vˆ id  1  vˆ be 
HD3,BJTdiff ≅ vˆ id =   HD3,BJT ≅  
4 a1 48  VT  24  VT 

B. Murmann EE214 Winter 2013-14 – Chapter 11 30

 Distortion in a MOS Differential Pair

2
 V   V 
Iod = Id1 − Id2 = ISS id  1 −  id 
 VOV   2VOV 

2
x 1 1 5
Id1 Id2 x 1 −   = x − x3 − x + ...
2 8 128

+ ISS ISS ISS

Vid a1 = ≡ Gm a3 = − 3
a5 = 5
VOV 8VOV 128VOV
-

ISS a3
Third-order model is accurate for: v̂id << = 4VOV
a5

2
1 a3 2 1  vˆ id 
HD3 ≅ vˆ id =  
4 a1 32  VOV 


B. Murmann EE214 Winter 2013-14 – Chapter 11 31

Feedback and Distortion

Low-frequency distortion is a result of variations in the slope of an

amplifier’s transfer characteristic. Feedback reduces the relative
variation, and thus the distortion, to the same extent that it reduces
fractional changes in gain.

Vout

Vin

Note that feedback reduces distortion without reducing the output

voltage range. The gain is also reduced, but additional gain can be
provided with a preamplifer the operates with smaller signal swings, and
therefore less distortion.

B. Murmann EE214 Winter 2013-14 – Chapter 11 32

 Power Series Analysis (1)

+ Sε
Si – a So
–
Sfb
f

So = a1Sε + a2Sε2 + a3S3ε + ...

Sε = Si − f ⋅ So

∴ So = a1(Si − f ⋅ So ) + a 2 (Si − f ⋅ So )2 + a3 (Si − f ⋅ So )3 + K

B. Murmann EE214 Winter 2013-14 – Chapter 11 33

Power Series Analysis (2)

Expressing So as a power series expansion in Si

So = b1Si + b2Si2 + b3Si3 + ...

Substitute this expression for So into the result on the previous page and
compare coefficients to find bi

b1Si = a1(Si − f ⋅b1Si )

a1
b1 =
1+ a1f

Thus, the feedback reduces the coefficient of the fundamental term in

the forward amplifier by 1 + af

B. Murmann EE214 Winter 2013-14 – Chapter 11 34

 Power Series Analysis (3)

Second-order terms

b 2Si2 = −a1f ⋅ b 2Si2 + a 2 (Si − f ⋅ b1Si )2

a 2 (1− b1f)2 a2
b2 = =
1+ a1f (1+ a1f)3

Third-order terms

b3Si3 = −a1f ⋅b3Si3 − 2a 2Si3 f ⋅ b 2 (1− f ⋅ b1) + a3 (Si − f ⋅ b1Si )3

a3 (1− b1f)3 − 2a 2 f ⋅b 2 (1− f ⋅ b1) a3 (1+ a1f) − 2a 22 ⋅ f
b3 = =
1+ a1f (1+ a f)51

B. Murmann EE214 Winter 2013-14 – Chapter 11 35

Comments

Large loop gain (a1f) leads to small nonlinearity

b3 contains a term due to a2
– This is due to signal interaction with the second-order term fed back
to the input
– It is possible to obtain b3 = 0 without large loop gain

B. Murmann EE214 Winter 2013-14 – Chapter 11 36

 An Interesting Example

VCC

IC = ICQ+ iC So = iC = a1Sε + a2Sε2 + a3S3ε + ...

Sε = vBE = v i − f ⋅ iC
Q
vi
~
RE
1 IC 1 IC
Vi f = RE a1 = gm a2 = a3 =
2 V2 6 V3
T T

a1 gm 1 IC 1
b1 = = b2 =
1+ a1f 1+ gmRE 2
2 V (1+ g R )3
T m E

1 IC 1 IC
(1+ gmRE ) − g R
6V 3 2 V3 m E 1
T T gmRE = ⇒ b3 = 0 ⇒ HD3 = 0
b3 =
(1+ gmRE )5 2

B. Murmann EE214 Winter 2013-14 – Chapter 11 37

TIA Example (Forward Amplifier “a”)

Parameters:
RD
௠ 
଴ = 14.2 ி = 1Ω = 10
஽ 
M2
̂௜ = 150  ௚௦ଵ = 150 ∙ 1Ω = 150
M3

Distortion estimate:
(Assuming that distortion from M1 dominates)

vo
M1 1 1 ଶ 1 1  ௚௦ଵ
ଶ =  =
2 (1 + ଴ )ଶ ଵ ௚௦ଵ 4 (1 + ଴ )ଶ 2/(
௠ /஽ )
ii RF RF
ଶ = 0.08%

B. Murmann EE214 Winter 2013-14 – Chapter 11 38

 Simulation Result
fourier components of transient response v(vo)
dc component = 0.68938

harmonic frequency fourier normalized phase normalized

no (hz) component component (deg) phase (deg)
1 1.00000x 139.467m 1.00000 -31.6540m 0.
2 2.00000x 46.3537u 332.363u 90.1638 90.1955
3 3.00000x 4.51955u 32.4058u 433.759m 465.413m
4 4.00000x 5.16067n 37.0028n -108.906 -108.875
5 5.00000x 7.29043n 52.2735n 171.380 171.412
6 6.00000x 1.08216n 7.75922n -132.803 -132.771
7 7.00000x 752.672p 5.39677n 25.7349 25.7666
8 8.00000x 656.750p 4.70899n -167.929 -167.897
9 9.00000x 472.851p 3.39041n 10.7810 10.8126

total harmonic distortion = 0.0333939 percent

The distortion is on the order of what we would expect from a simple

hand calculation

Note that some discrepancy is to be expected, since the other
transistors in the circuit also contribute some nonlinearity
– Which in our case appears to improve the overall linearity!
– Unlike noise, distortion products can (partially) cancel

B. Murmann EE214 Winter 2013-14 – Chapter 11 39

 Chapter 12
High Frequency Distortion Analysis

Boris Murmann
Stanford University
Winter 2013-14

High Frequency Distortion Analysis

The power series approach studied previously ignores any frequency

dependence introduced by reactive elements
– Sufficient for 90% of typical circuits, including some operating at RF

Assuming weakly nonlinear behavior, the frequency dependence can be
included using a Volterra Series model
– Vito Volterra, 1887

The following discussion provides a few basic
examples that will allow you to appreciate the
general framework

Examples
– Memoryless nonlinearity followed by a filter
– Memoryless nonlinearity preceded and followed by a filter
– RC circuit with nonlinear capacitance

B. Murmann EE214B Winter 2013-14 – Chapter 12 2

 Classification of Nonlinear Models

Memoryless With Memory

Continuous Discrete
Time Time

Time Frequency Time Frequency

Domain Domain Domain Domain

(Our focus)

B. Murmann EE214B Winter 2013-14 – Chapter 12 3

Example 1

R
ic ic = a1vi + a2 vi2 + a3 vi3 + ...
vo
1 ICQ 1 ICQ
a1 = gm a2 = a3 =
C 2 VT2 6 VT3
vi

VI
vo −R
K(jω) = =
ic 1 + jωRC

The expressions above ignore device capacitances and finite output

resistance (for simplicity)

The circuit represents a nonlinear block followed by a linear filter
– Also called “Hammerstein model”
– A circuit with the reverse order (filter followed by a nonlinear block) is
called a “Wiener model”

B. Murmann EE214B Winter 2013-14 – Chapter 12 4

 Applying a Single-Tone Input

vi = vˆ i cos ( ω t )

Ignoring DC offset and gain expansion, we have

1 1
ic = a1vˆ i cos ( ω t ) + a2 vˆ i2 cos ( 2ω t ) + a3 vˆ i3 cos ( 3ω t ) + ...
2 4

The output voltage consists of the same tones, with their magnitude and
phase altered by the linear filter K(jω)

v o = K ( jω ) ⋅ a1vˆ i cos ( ω t + φω )

1 φm ω = ∠ K ( m ⋅ j ω )
+ K ( 2jω ) ⋅ a2 vˆ i2 cos ( 2ω t + φ2ω )
2
1
+ K ( 3jω ) ⋅ a3 vˆ i3 cos ( 3ω t + φ3ω ) + ...
4

B. Murmann EE214B Winter 2013-14 – Chapter 12 5

Two-Tone Input

vi = vˆ 1 cos ( ω1t ) + vˆ 2 cos ( ω2 t )

Substituting this input into the power series, and using the identities
shown below, the complete expression for the collector current is most
elegantly expressed as shown on the next slide

1
cos ( α ) cos ( β ) = cos ( α + β ) + cos ( α − β ) 
2
1
cos ( α ) cos ( β ) cos ( γ ) = cos ( α + β + γ ) + cos ( α + β − γ )
4
+ cos ( α − β + γ ) + cos ( α − β − γ ) 

B. Murmann EE214B Winter 2013-14 – Chapter 12 6

 Frequency
Components

ic = a1  vˆ 1 cos ( ω1t ) + vˆ 2 cos ( ω2 t )  ω1, ω2

a2  2
+ vˆ 1 cos ([ ω1 ± ω1] t ) + vˆ 22 cos ([ ω2 ± ω 2 ] t ) 0, 2ω1, 2ω2
2 

+2vˆ 1 vˆ 2 cos ([ ω1 ± ω 2 ] t )  ω1-ω2, ω1+ω2


a3  3
+ vˆ 1 cos ([ ω1 ± ω1 ± ω1] t ) + vˆ 32 cos ([ ω2 ± ω 2 ± ω2 ] t ) ω1, ω2, 3ω1, 3ω2
4 

+ 3vˆ 12 vˆ 2 cos ([ ω1 ± ω1 ± ω2 ] t ) ω2, 2ω1-ω2, 2ω1+ω2

+ 3vˆ 1 vˆ 22 cos ([ ω1 ± ω2 ± ω 2 ] t )  + ... ω1, 2ω2-ω1, 2ω2+ω1



B. Murmann EE214B Winter 2013-14 – Chapter 12 7

Filtered Output

v o = a1  vˆ 1 K ( jω1 ) cos ω1t + φω1 + vˆ 2 K ( jω2 ) cos ω2 t + φω2 

( ) ( )
 
a2 
+
2  ( )
K ( 2jω1 ) ⋅ vˆ 12 cos 2ω1t + φ2ω1 + vˆ 12 K ( 0 )

( )
+ K ( 2jω2 ) ⋅ vˆ 22 cos 2ω 2 t + φ2ω2 + vˆ 22 K ( 0 )

(
+ K ( j [ ω1 − ω2 ]) ⋅ 2vˆ 1 vˆ 2 cos [ ω1 − ω2 ] t + φω1−ω2 )
+ K ( j [ ω1 + ω 2 ]) ⋅ 2vˆ 1 vˆ 2 cos [ ω1 + ω 2 ] t + φω1+ω2 
( )

a3
+ [...]
4

B. Murmann EE214B Winter 2013-14 – Chapter 12 8

 Short Hand Notation

v o = a1K ( jωa )
vi + a2K ( jωa + jωb )
v i2 + a3K ( jωa + jωb + jωc )
vi3 + ...
     
H1( jωa ) H2 ( jωa + jωb ) H3 ( jωa + jωb + jωc )

Operator “◦” means

– Multiply each frequency component in vim by

Hm ( jωa, jωb,...)
and shift phase by
∠Hm ( jωa, jωb,...)

The arguments ωa, ωb, ωc, 6 are auxiliary variables taking on all
permutations of ω1, ±ω2, 6 ±ωm

B. Murmann EE214B Winter 2013-14 – Chapter 12 9

General Frequency Domain Volterra Series

v o = H1 ( jωa )
vi + H2 ( jωa , jωb )
v i2 + H3 ( jωa , jωb , jωc )
vi3 + ...

In the time domain, the corresponding expression is a multi-dimensional

convolution integral

For the circuit example discussed previously, the coefficients of the
frequency domain series are given as follows

−a1R
H1(jωa ) =
1 + jωaRC

−a2R
H2 (jωa , jωb ) =
1 + ( jωa + jωb ) RC

−a3R
H3 (jωa , jωb , jωc ) =
1 + ( jωa + jωb + jωc ) RC

B. Murmann EE214B Winter 2013-14 – Chapter 12 10

 Distortion Metrics

Taylor Series Volterra Series

1 a2 1 H2 ( jω1, jω1 )
HD2 v̂i v̂i
2 a1 2 H1 ( jω1 )

1 a3 2 1 H3 ( jω1, jω1, jω1 ) 2

HD3 v̂i v̂i
4 a1 4 H1 ( jω1 )

3 a3 2 3 H3 ( jω1, jω1, − jω 2 ) 2
IM3 v̂i v̂i
4 a1 4 H1 ( jω1 )

Volterra series model

– Second and third order distortion still vary with square and cube of input
amplitude, respectively
– But, there is no fixed relationship between HD2 and IM2, and HD3 and IM3

B. Murmann EE214B Winter 2013-14 – Chapter 12 11

Distortion Metrics for Example 1

1
1 H2 ( jω, jω ) 1 a2 1 + 2jω RC 1 a2 1 + jω RC
HD2 = vˆ i = vˆ i = vˆ i
2 H1 ( jω ) 2 a1 1 2 a1 1 + 2jω RC
1 + jω RC

1 H3 ( jω, jω, jω ) 2 1 a3 1 + jω RC 2
HD3 = vˆ i = vˆ i
4 H1 ( jω ) 4 a1 1 + 3jω RC

3 H3 ( jω1, jω1, − jω2 ) 2 1 a3 1 + jω1RC

IM3 = vˆ i = vˆ i2
4 H1 ( jω1 ) 4 a1 1 + j ( 2ω1 − ω 2 ) RC

B. Murmann EE214B Winter 2013-14 – Chapter 12 12

 HD2 and HD3 Distortion Plots for Example 1
VT
ICQ = 1mA vˆ i =
5

B. Murmann EE214B Winter 2013-14 – Chapter 12 13

IM3 Distortion Plot for Example 1

ICQ = 1mA
0.5
VT
vˆ i1 = vˆ i2 =
0.4 5
IM3 [%]

0.3

0.2 Taylor
Volterra, ω 2/ω 1=0.9
0.1

0 -2 -1 0 1
10 10 10 10
ω 1RC

Unlike HD2,3, IM3 is almost frequency independent

The tones “slide” along the filter transfer function together and see
(approximately) the same attenuation

B. Murmann EE214B Winter 2013-14 – Chapter 12 14

 Example 2

2 3
ic = a1v be + a2 vbe + a3 vbe + ...

vo −R
K(jω ) = =
ic 1 + jω RC

vbe 1
Kin (jω) = =
vi 1 + jωRinCin

Similar to example 1, but now including an additional filter at the input

B. Murmann EE214B Winter 2013-14 – Chapter 12 15

Two-Tone Input

vi = vˆ 1 cos ( ω1t ) + vˆ 2 cos ( ω2t )

The two input tones are now processed by a linear filter before being
sent through the nonlinearity

At the base of the BJT, we have

( ) (
vbe = K in ( jω1 ) ⋅ vˆ 1 cos ω1t + ψ ω1 + K in ( jω 2 ) ⋅ vˆ 2 cos ω 2 t + ψ ω2 )
ψmω = ∠K in ( m ⋅ jω )

In short hand notation, this can be written as

vbe = K in ( jωa )
v i

B. Murmann EE214B Winter 2013-14 – Chapter 12 16

 2 3
v o = a1K ( jωa )
vbe + a2K ( jωa + jωb )
vbe + a3K ( jωa + jωb + jωc )
vbe + ...

v o = a1K ( jωa )
K in ( jωa )
vi 

2
+ a2K ( jωa + jωb )
K in ( jωa )
v i 

3
+ a3K ( jωa + jωb + jωc )
K in ( jωa )
v i 

First order term

a1K ( jωa )
K in ( jωa )
vi  = a1K ( jωa ) K in ( jωa )
v i

“Volterra algebra rules”

B. Murmann EE214B Winter 2013-14 – Chapter 12 17

Second order term

2
a2K ( jωa + jωb )
K in ( jωa )
vi  = ?

2 2
K in ( jωa )
vi  = K in ( jωa )
{vˆ 1 cos ( ω1t ) + vˆ 2 cos ( ω 2 t )}

2
=  K in ( jω1 ) ⋅ vˆ 1 cos ω1t + ψ ω1 + K in ( jω 2 ) ⋅ vˆ 2 cos ω2 t + ψ ω2 
( ) ( )
 
2
(
= K in ( jω1 ) ⋅ vˆ 12 cos {ω1 ± ω1} t + ψ ω1 ± ψ ω1 )
2
(
+ K in ( jω 2 ) ⋅ vˆ 22 cos {ω 2 ± ω2 } t + ψ ω2 ± ψ ω2 )
(
+ K in ( jω1 ) K in ( jω 2 ) ⋅ vˆ 1 vˆ 2 cos {ω1 ± ω2 } t + ψ ω1 ± ψ ω2 )
= K in ( jωa ) K in ( jωb )
v i2

B. Murmann EE214B Winter 2013-14 – Chapter 12 18

 Coefficients

1 −a1R
H1(jωa ) =
1 + jωaRC 1 + jωaRC

1 1 −a2R
H2 (jωa , jωb ) =
1 + jωaRC 1 + jωbRC 1 + ( jωa + jωb ) RC

1 1 1 −a3R
H3 (jωa , jωb , jωc ) =
1 + jωaRC 1 + jωbRC 1 + jωcRC 1 + ( jωa + jωb + jωc ) RC

B. Murmann EE214B Winter 2013-14 – Chapter 12 19

Example 3

ij

[Chun & Murmann, JSSC 10/2006]

Cj models the nonlinear capacitance of an electrostatic discharge (ESD)

protection device (e.g. a basic diode structure as shown to the right)

Analysis options
1) “Quick and dirty” – neglects second-order interaction terms
2) Full blown analysis

B. Murmann EE214B Winter 2013-14 – Chapter 12 20

Step 1: Set up Capacitance Model (Common to both Approaches)

C j0 C j0 1
Cj = M
= M M
 VOQ + v o   ψ0 + VOQ   ψ0 + VOQ + v o 
1+     
 ψ0   ψ0   ψ0 + VOQ 

Using C j0 1 1
C jQ =
 VOQ 
M
(1 + x ) M
= 1 − Mx +
2
( )
M + M2 x 2 + ...
1 + 
 ψ0 

M M + M2
VR = VOQ + ψ0 b1 = − b2 =
VR 2VR

we can write C jQ
Cj = = C jQ 1 + b1v o + b2 v o2 + ...
M  
 vo 
1 + 
 VR 

B. Murmann EE214B Winter 2013-14 – Chapter 12 21

Step 2: Circuit Analysis (Common to both Approaches)

dv o dv  dv 1 dv 2 1 dv 3 
ij = C j = C jQ 1 + b1v o + b2 v o2 + ... o = C jQ  o + b1 o + b3 o 
dt   dt  dt 2 dt 3 dt 

 2 3
(
i = C jQ + CI ) dvdto + C jQ  21 b1 dvdto + 31 b3 dvdto 
 

dv o  1 dv 2 1 dv 3 
(
vi = v o + i ⋅ R = v o + R C jQ + CI ) dt
+ RC jQ  b1 o + b3 o 
 2 dt 3 dt 

d d d
vi = v o + RC0 v o + RC1 v o2 + RC2 v 3o
dt dt dt

C0 = C jQ + Ci
b
C1 = 1 C jQ = −
MC jQ b1
C2 = C jQ = −
M + M2 C jQ( )
2 2VR 3 6VR2

B. Murmann EE214B Winter 2013-14 – Chapter 12 22

 Circuit Representation

Linear Nonlinear

݀ ଶ
݅ଶ = ‫ܥ‬ଵ ‫ݒ‬
݀‫ ݐ‬௢
݀ ଷ
݅ଷ = ‫ܥ‬ଶ ‫ݒ‬
݀‫ ݐ‬௢

Quick first-order analysis for weak nonlinearities (Bussgang, 1974)

– Compute vo using only the linear part of the circuit (remove the
nonlinear elements)
– Compute the induced nonlinear currents (harmonics) using the
computed first order response
– Inject the current harmonics into the linear portion of the circuit to find
the filtered amplitudes

B. Murmann EE214B Winter 2013-14 – Chapter 12 23

Example Calculation for HD2

Linear response
1

௢,ଵ =
௜ sin  ∙ =
௜ cos  ∙ ()
1 + ଴

Second order current generator

ଶ
ଶ
ଶ = ଵ
= ଵ
 cos  ∙  

 ௢,ଵ
 ௜

1 1
ଶ =
௜ଶ   ଶ
ଵ + cos 2 = −
௜ଶ   ଶ
ଵ sin (2)

 2 2

Inject second order current into linear filter



௢,ଶ = −
௜ଶ   ଶ
ଵ sin (2) ∙ = −
௜ଶ   ଶ
ଵ sin (2) ∙ (2)
1 + 2଴

ଶ
 
 
௢,ଶ   ଵ (2)
 ଶ = =
௜
 
 
௢,ଵ ()

 ଶ = ଵ () (2)
௜

B. Murmann EE214B Winter 2013-14 – Chapter 12 24

 Full Analysis using a Volterra Series Representation

We are looking for a Volterra series representation of the form

v o = H1 ( jωa )
vi + H2 ( jωa , jωb )
v i2 + H3 ( jωa , jωb , jωc )
vi3 + ...

The coefficients H1, H2 and H3 can be found by inserting the above

series into the nonlinear differential equation of the circuit and
subsequently comparing the coefficients on the LHS and RHS of the
equation

vi = H1 ( jωa )
vi + H2 ( jωa , jωb )
vi2 + H3 ( jωa , jωb , jωc )
vi3

d
+ RC0 H1 ( jωa )
v i + H2 ( jωa , jωb )
vi2 + H3 ( jωa , jωb , jωc )
vi3 
dt  

d 2
+ RC1 H1 ( jωa )
vi + H2 ( jωa , jωb )
vi2 + H3 ( jωa , jωb , jωc )
vi3 
dt  

d 3
+ RC2 H1 ( jωa )
v i + H2 ( jωa , jωb )
vi2 + H3 ( jωa , jωb , jωc )
vi3 
dt  

B. Murmann EE214B Winter 2013-14 – Chapter 12 25

Coefficient Comparison (1)

First order
 d
1
vi = 1 + RC0  H1 ( jωa )
vi
 dt 

 d
1 = 1 + RC0  H1 ( jωa ) = 1 + RC0 jωa  H1 ( jωa )
 dt 

1
∴ H1 ( jωa ) =
1 + RC0 jωa

This is just the linear transfer function as expected

B. Murmann EE214B Winter 2013-14 – Chapter 12 26

 Coefficient Comparison (2)

Second order

 d d 2
0
vi2 = 1 + RC0  H2 ( jωa , jωb )
vi2 + RC1 H1 ( jωa )
vi 
 dt  dt  

Simplify using the following rules

d
H2 ( jωa , jωb ) = ( jωa + jωb ) H2 ( jωa , jωb )
dt
2
H1 ( jωa )
vi  = H1 ( jωa ) H1 ( jωb )
vi2
 
d
H1 ( jωa ) H1 ( jωb )  = ( jωa + jωb ) H1 ( jωa ) H1 ( jωb )
dt 

B. Murmann EE214B Winter 2013-14 – Chapter 12 27

Coefficient Comparison (3)

0 = 1 + RC0 ( jωa + jωb )  H2 ( jωa , jωb ) + RC1 ( jωa + jωb ) H1 ( jωa ) H1 ( jωb )

−RC1 ( jωa + jωb ) H1 ( jωa ) H1 ( jωb )

H2 ( jωa , jωb ) =
1 + RC0 ( jωa + jωb )

∴ H2 ( jωa , jωb ) = −RC1 ( jωa + jωb ) H1 ( jωa ) H1 ( jωb ) H1 ( jωa + jωb )

H2 becomes zero for ω→0; this makes intuitive sense

B. Murmann EE214B Winter 2013-14 – Chapter 12 28

 Coefficient Comparison (4)

Third order

 d
0
vi3 = 1 + RC0  H3 ( jωa , jωb , jωc )
vi3
 dt 
d
+ RC1 (
2 H1 ( jωa )
vi ) (H ( jωa, jωb )
vi2 ) Second-order
dt 
2 Interaction Term

d 3
+ RC2 H1 ( jωa )
vi 
dt  

Simplifying and neglecting the second-order interaction term yields

∴ H3 ( jωa , jωb , jωc ) = −RC2 ( jωa + jωb + jωc ) H1 ( jωa ) H1 ( jωb ) H1 ( jωc )

⋅ H1 ( jωa + jωb + jωc )

B. Murmann EE214B Winter 2013-14 – Chapter 12 29

Harmonic Distortion Expressions (1)

2
RC1 ( 2jω ) H1 ( jω )  H1 ( 2jω )
1 H2 ( jω, jω ) 1
HD2 = vˆ i = vˆ i = ω RC1 H1 ( jω ) H1 ( 2jω ) vˆ i
2 H1 ( jω ) 2 H1 ( jω )

1  v̂ 
∴ HD2 = Mω RC jQ H1 ( jω ) H1 ( 2jω )  i 
2  VR 
 

HD2 improves for

– Lower swing (vi/VR)
– Lower frequency
– Lower drive resistance (R)
– Smaller capacitive nonlinearity (M→0) and smaller CjQ

Adding extra linear capacitance (CI) will only lower the corner frequency of H1
– Assuming that we cannot tolerate much signal attenuation, this won’t help
reduce the distortion all that much in the useable frequency range

B. Murmann EE214B Winter 2013-14 – Chapter 12 30

 Harmonic Distortion Expressions (2)

3
RC2 ( 3jω ) (H1 ( jω ) ) H1 ( 3jω )
1 H3 ( jω, jω, jω ) 2 1
HD3 = vˆ i = vˆ i2
4 H1 ( jω ) 4 H1 ( jω )

3 2
= ω RC2 H1 ( jω ) H1 ( 3jω ) vˆ i2
4

2
1  v̂ 
( )
∴ HD3 = M + M2 ω RC jQ H1 ( jω ) H1 ( 3jω )  i 
8  VR 
 

HD3 behaves similar to HD2

– The distortion depends on similar quantities and cannot be improved
by adding additional linear capacitance (Ci)

HD3 is often more critical than HD2, since the latter can be improved
significantly by employing a differential circuit topology

B. Murmann EE214B Winter 2013-14 – Chapter 12 31

Plot for Typical Values

v̂i = 0.5V

R = 25Ω

Ci = 0

C jQ = 1pF

M = 0.3

VR = VOQ + ψ 0 = 2.2V

1
= 6.4GHz
2πRC jQ

B. Murmann EE214B Winter 2013-14 – Chapter 12 32

 Additional Topics in Distortion Analysis

Covered in EE314A
– RF-centric metrics
• Intercept points
• 1-dB gain compression point

Other
– Nonlinearity in MOSFET output conductance
– Nonlinearities in passive components
– Distortion cancelation or pre-/post-compensation techniques
– Cascading nonlinearities
– Series reversion
– Distortion in clipped or amplitude limiting waveforms
• E.g. in oscillators

B. Murmann EE214B Winter 2013-14 – Chapter 12 33

References (1)

D. O. Pederson and K. Mayaram, Analog Integrated Circuits for

Communication, Springer, 1991

P. Wambacq and W. M. C. Sansen, Distortion Analysis of Analog
Integrated Circuits, Springer, 1998

Hurst, Lewis, Gray & Meyer, 5th edition, pp. 355-359
– Distortion analysis of a source follower

B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill,
2000, Chapter 13

W. Sansen, “Distortion in elementary transistor circuits,” IEEE Trans.
Circuits and Systems II, vol. 46, pp. 315-325, March 1999

P. Wambacq, G. Gielen, and P. Kinget, “High-Frequency Distortion
Analysis of Analog Integrated Circuits,” IEEE Trans. Circuits and Syst. II,
pp. 335-345, March 1999

W. Rugh, Nonlinear System Theory,
http://rfic.eecs.berkeley.edu/ee242/pdf/volterra_book.pdf

B. Murmann EE214B Winter 2013-14 – Chapter 12 34

 References (2)

R.G. Meyer, EE242 Lecture Notes, 1999

R.G. Meyer and M.L. Stephens, "Distortion in variable-capacitance
diodes," IEEE J. Solid-State Circuits, pp. 47-54, Feb. 1975

J. Bussgang, L. Ehrman, and J. Graham, “Analysis of nonlinear systems
with multiple inputs,” Proc. IEEE, vol. 62, no. 8, pp. 1088–1119, 1974

K. L. Fong and R.G. Meyer, "High-frequency nonlinearity analysis of
common-emitter and differential-pair transconductance stages," IEEE J.
Solid-State Circuits, pp. 548-555, Apr. 1998

M.T. Terrovitis and R.G. Meyer, "Intermodulation distortion in current-
commutating CMOS mixers," IEEE J. Solid-State Circuits, pp.1461-
1473, Oct. 2000

J. Chun and B. Murmann, "Analysis and Measurement of Signal
Distortion due to ESD Protection Circuits," IEEE J. Solid-State Circuits,
pp. 2354-2358, Oct. 2006

W. Yu, S. Sen and B.H. Leung, "Distortion analysis of MOS track-and-
hold sampling mixers using time-varying Volterra series," IEEE Trans.
Circuits and Syst. II, pp. 101-113, Feb. 1999

B. Murmann EE214B Winter 2013-14 – Chapter 12 35

 Chapter 13
Mismatch

Boris Murmann
Stanford University
Winter 2013-14

Textbook Sections: 2.3

Motivation

K. Kuhn et al., “Managing Process Variation in Intel's 45nm CMOS

Courtesy A. Bowling Technology,” http://www.intel.com/technology/itj/2008/v12i2/3-
Texas Instruments managing/1-abstract.htm

As transistors become smaller and more intricate, it becomes

increasingly important to understand device mismatch

Important distinctions
– Global process variations
– Device-to-device mismatch: Random & systematic errors

B. Murmann EE214B Winter 2013-14 – Chapter 13 2

 Global Process Variations

Wafer made yesterday Wafer made today

All NMOS are “slow” All NMOS are “fast”
All PMOS are “nominal” All PMOS are “fast”
All R are nominal All R are nominal
All C are “fast” All C are “slow”

Parameter “Slow” “Nominal” “Fast”

Vt 0.4V 0.3V 0.2V
mCox (NMOS) 240 mA/V2 300 mA/V2 360 mA/V2
mCox (PMOS) 80 mA/V2 100 mA/V2 120 mA/V2
Rpoly 60Ω/□ 50Ω/□ 40Ω/□
Rnwell 1.4 kΩ/□ 1 kΩ/□ 0.6 kΩ/□
CMIM 1.15 fF/mm2 1 fF/mm2 0.85 fF/mm2

B. Murmann EE214B Winter 2013-14 – Chapter 13 3

Device-to-Device Mismatch

Device parameters not only vary from lot-to-lot or wafer-to-wafer, but

there are also differences between closely spaced, nominally identical
devices on the same chip
– These differences are called mismatch

Vt1 − Vt2 = ∆Vt

M1 M2  W  W
 µCox L  −  µCox L  = ∆β
 1  2

C1 C2
C1 − C2 = ∆C
R1 R2 R1 − R2 = ∆R

B. Murmann EE214B Winter 2013-14 – Chapter 13 4

 Statistical Model

Experiments over the past decades have shown that device-to-device

mismatch (∆Vt, ∆C, =) for properly laid out devices (no systematic
errors) is “random” and well-described by a Gaussian distribution
– With zero mean and a standard deviation that depends on the
process and the size of the device

The standard deviation of the parameter mismatch between two closely
spaced devices is modeled using the following expression

AP Sometimes referred to as
σ∆P = “Pelgrom’s rule”
WL AP: “Pelgrom coefficient”

where W·L represents the area of the device, and P is the device
parameter under consideration

[M. Pelgrom et al., “Matching Properties of MOS Transistors,” JSSC, Oct. 1989]

B. Murmann EE214B Winter 2013-14 – Chapter 13 5

Parameters for a Typical 0.18-µm Process

Parameter Value
Avt (MOSFET) 5 mV-µm
A∆β/β (MOSFET) 1 %-µm
A∆Is/Is (Bipolar transistor) 2 %-µm
A∆β/β (Bipolar transistor) 4 %-µm
A∆C/C (MIM capacitor) 1 %-µm
A∆R/R (Poly resistor) 3 %-µm

B. Murmann EE214B Winter 2013-14 – Chapter 13 6

 Example

Example: MIM-capacitor with W=10µm, L=10µm (~100-200 fF)

1%
σ∆C/C = = 0.1% 3σ∆C/C = 0.3%
100

http://en.wikipedia.org/wiki/Image:Standard_deviation_diagram.svg

B. Murmann EE214B Winter 2013-14 – Chapter 13 7

Vt Mismatch due to Doping Fluctuations (First Order Analysis)

Average number of dopants

G
N = NAWLZ
S D
Z

To first order, the number of doping atoms in the depletion region follow
a Poisson distribution with mean λ and standard deviation sqrt(λ)
– Example: 1000 dopants on average  standard deviation of ~30



௧ =
ி஻ +
௢௫
௢௫
   ஺
௢௫

(
௧ ) = =
௢௫ 
௢௫
௢௫  ஺  ௏௧

(∆
௧ ) = 2 =
 

B. Murmann EE214B Winter 2013-14 – Chapter 13 8

 AVt Data Confirming (Approximate) tox Proportionality

[M. Pelgrom, IEDM 1998]

[Pelgrom, “A Designer’s View on Mismatch,” in
Analog Circuit Design, Springer, 2013]

For constant device area (WL), Vt mismatch improves as technology is scaled

Unfortunately, AVt reduces not as fast as minimum device area (WL), and
hence Vt mismatch for minimum-size devices worsens

B. Murmann EE214B Winter 2013-14 – Chapter 13 9

Mismatch in a MOS Current Mirror

∆β
∆I = I1 − I2 ≅ −gm ∆Vt + I1
β
∆I g ∆β
≅ − m ∆Vt +
I1 I1 β

Example: W=20µm, L=0.2µm, gm/ID=10S/A, AVt = 5mVµm, Aβ = 1%µm

2
 S  2 2 2
σ ∆I =  10 ⋅ 2.5mV  + ( 0.5% ) = ( 2.5%) + ( 0.5%) = 2.54%
I1  A 

• Threshold mismatch usually dominates, unless gm/ID is impractically low

B. Murmann EE214B Winter 2013-14 – Chapter 13 10

 Design Scenarios (1)

If the device area is fixed, choose small gm/ID (large VOV) for improved
matching
ଶ
∆஽ g ୫ ଶ௏௧
 ≅
஽ ஽ 

Text, p. 101
AVt = 4 mVµm
Aβ = 1 %µm
W/L = 2 µm/0.2µm

(β)

B. Murmann EE214B Winter 2013-14 – Chapter 13 11

Design Scenarios (2)

More interesting case: Mirror input current is fixed

ଶ
ଶ ଶ
∆஽ g୫ ଶ௏௧ 2 ଶ௏௧  1 1 2஽
 ≅ = ∝ = ଶ
ை௏ =
஽ ஽ 
ை௏     
௢௫ 

The primary “knob” to improve matching is the channel length

For a real MOSFET, the W terms do not cancel perfectly and the best
matching is achieved when the transistor operates in weak inversion
4
Mismatch StDev [%], Width [mm]

Mismatch W
2 ID = 500µA

0
5 10 15 20 25
gm /I D [S/A]

B. Murmann EE214B Winter 2013-14 – Chapter 13 12

 Design Scenarios (3)

Obvious issues with pushing the mirror into weak inversion

– The devices get huge and their parasitics (e.g. junction caps) may
significantly load the signal path
– With large gm/ID, the thermal noise contribution from the mirror may
become unacceptably high
– Usually not worth it=

Additional issue in practice: sensitivity to systematic errors, e.g. IR drop

V1 V2=V1
I1 I2 ∆I = I1 − I2 ≅ gm Vwire

M1
∆I gm
M2 ≅ Vwire
I1 I1
- Vwire +

Rwire Want small gm/ID

B. Murmann EE214B Winter 2013-14 – Chapter 13 13

Mismatch in a BJT Current Mirror

Neglecting finite β effects

∆I ∆IS
≅
I1 IS

Example: AE = 0.7µm2 (EE214B unit BJT), A∆Is/Is = 2%µm

2%
σ ∆I = = 2.4%
I1 0.7

• Error magnitude is similar to that of 20/0.2 MOSFET

• Can use multiple unit devices or resistive degeneration to achieve a
smaller mirror error

B. Murmann EE214B Winter 2013-14 – Chapter 13 14

 Input-Referred Offset due to Mismatch

In a perfectly symmetric differential pair, Vid = 0 yields Vod = 0

Imbalances can be modeled as input referred offsets
VCC VCC

RC1 RC2 RC RC

Vo1 Vo2 Vo1 Vo2

∆IS Vos
IB1
∆β – +
Vi1 Q1 Q2 Vi1 Q1 Q2

Ios/2
Vi2 Vi2
IB2
IEE IEE
OFFSETS
VEE VEE

PAIR W/ MISMATCH IDEAL PAIR

B. Murmann EE214B Winter 2013-14 – Chapter 13 15

Analysis (1)

Vos − VBE1 + VBE2 = 0

I  I 
∴ Vos = VT ln  C1  − VT ln  C2 
 IS1   IS2 
 I   I   kT
= VT ln  C1   S2   , where VT =
 IC2   IS1   q

If Vod = 0, then

IC1RC1 = IC2RC2

IC1 RC2
∴ =
IC2 RC1

Thus
 R   I  
Vos = VT ln   C2   S2  
  RC1   IS1  

B. Murmann EE214B Winter 2013-14 – Chapter 13 16

 Analysis (2)

For small mismatches ∆RC << RC and ∆IS << IS, it follows that

−1
 ∆RC ∆IS   gm   ∆RC ∆IS 
Vos ≅ VT  − − =  − − 
 RC IS   ID   RC IS 

And similarly IC  ∆RC ∆β 

Ios ≅ −  + 
β  RC β 

Offset voltage drift

dVos d  kT  ∆RC ∆IS   Vos
=  − − =
dT dT  q  RC IS   T

Example
– VOS was determined to be 2 mV through a measurement at 300°K
– Means that the offset voltage will drift by 2 mV/300°K = 6.6 µV/ °K

B. Murmann EE214B Winter 2013-14 – Chapter 13 17

Comparison of VOS for MOS and BJT Differential Pairs

−1
 g   ∆R ∆IS 
VOS,BJT ≅  m   − − 
 ID   R IS 
−1
 g   ∆R ∆β  A Vt
VOS,MOS ≅ ∆Vt +  m   − −
β 
σ∆Vt =
 ID   R WL

Want large area
Extra Worse
term than BJT

Example (using previous numbers and neglecting resistor mismatch)

 g −1  ∆I  
std ( VOS,BJT ) ≅ std  m   S   = 26mV ⋅ 2.4% = 0.62mV
 ID   IS  
 
  g   ∆β  
−1
std ( VOS,MOS ) ≅ std  ∆Vt +  m    ≅ ( 2.5mV )2 + (100mV ⋅ 1%)2 = 2.69mV

  ID   β  

MOS offset is typically 5-10 times worse than BJT

Need large MOS devices for low offset
– Or use offset cancellation tricks – see EE315A

B. Murmann EE214B Winter 2013-14 – Chapter 13 18

 Mismatch “Gotchas” in Modern CMOS Technology

In CMOS technologies at/below 130nm, a variety of matching “pitfalls”

have even discovered

Well proximity effect

Shallow-Trench Isolation (STI) edge effects

Metal coverage effects

Matching degradation due to pocket implants

Increased ratio of mismatch/process variation

=

B. Murmann EE214B Winter 2013-14 – Chapter 13 19

Well Proximity Effect

P. G. Drennan et al., "Implications of Proximity Effects for Analog Design," Proc. CICC, pp.169-176, Sep. 2006.

Transistors near the well edge may see a threshold shift of up to 50mV

B. Murmann EE214B Winter 2013-14 – Chapter 13 20

 STI Stress Effects

[Text, p. 98]

[Pelgrom, “A Designer’s View on

Mismatch,” in Analog Circuit Design,
Springer, 2013]

Good matching requires

proper matching of STI stress
– Match edge distances,
avoid placing critical
fingers at STI edge (use
dummies), etc.

B. Murmann EE214B Winter 2013-14 – Chapter 13 21

Metal Coverage Stress Effects

Covering transistors with

metal may reduce mobility
– Change in annealing
– Change in stress pattern

Must match metal coverage
and keep wiring away from
matching sensitive structures
(tens of microns)

[H.P. Tuinhout, M.J.M. Pelgrom, R. Penning de Vries,

M. Vertregt, “Effects of Metal Coverage on MOSFET
Matching,” IEDM Digest, pp. 735-739, 1996]

B. Murmann EE214B Winter 2013-14 – Chapter 13 22

 Matching Degradation due to Pocket Implants

[C.M. Mezzomo, et al., "Characterization and Modeling of Transistor Variability in Advanced CMOS
Technologies," IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2235-2248, Aug. 2011]

Doping concentration and electrostatic control is not uniform in a device

with pocket implants

Increasing L does not improve matching, since the drain current is
mostly controlled by the pocket regions  Apparent increase in Avt

Need a better mismatch model, e.g. A B
σ∆Vt = +
WL W

B. Murmann EE214B Winter 2013-14 – Chapter 13 23

Increased Ratio of Mismatch/Process Variation

[Pelgrom, “A Designer’s View on

Mismatch,” in Analog Circuit Design,
Springer, 2013]

For minimum size transistors, device-to-device mismatch has become

comparable in magnitude to global process variations
– Why still bother with corner models (slow, nom, fast)?

B. Murmann EE214B Winter 2013-14 – Chapter 13 24