Renewable and Sustainable Energy Reviews 120 (2020) 109631

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Renewable and Sustainable Energy Reviews

journal homepage: http://www.elsevier.com/locate/rser

Protection and grounding methods in DC microgrids: Comprehensive

review and analysis
D.K.J.S. Jayamaha a, *, N.W.A. Lidula a, A.D. Rajapakse b
a
Department of Electrical Engineering, University of Moratuwa, Katubedda, Moratuwa, 10400, Sri Lanka
b
Department of Electrical and Computer Engineering, University of Manitoba, MB, R3T 5V6, Canada

A R T I C L E I N F O A B S T R A C T

Keywords: DC microgrids (DCMGs) presents an effective means for the integration of renewable-based distributed gener­
DC microgrids ations (DGs) to the utility network. DCMGs have clear benefits such as high efficiency, high reliability, better
Fault current interruption compatibility with DC sources and loads, and simpler control, over its AC equivalent system. While advantages of
Fault detection
DCMGs are considerable, of particular concern are the associated protection challenges, such as lack of phasor
Grounding
Protection
and frequency information, rapid fault current rise, breaking DC arc and certainly the lack of standards,
guidelines and practical experience. This paper presents an extensive review of fault characteristics of DCMGs
and the protection challenges. Innovative protection techniques proposed to solve these issues, and comparative
analysis of these techniques are presented outlining the strengths and drawbacks of each. Possible improvements
to the current technologies and future directions for research, which could enhance the protection of DCMGs, are
outlined in this paper.

can be carefully designed to achieve high reliability, uninterruptable

power supply, increased efficiency, reduced conduction losses and bet­
1. Introduction ter local voltages [6]. Hence, microgrids are also an effective solution to
supply critical loads such as data centers, and rural areas. In addition,
Conventional fossil fuel based power generation is one of the largest microgrids embedding DGs are particularly a relief to the conventional
contributors to the world’s greenhouse gas emissions and climate power generation and transmission infrastructure [3,4].
change. A rapid increase in the development of renewable energy Increasing use of solar PV arrays, electronic loads and electric ve­
sources (RESs) has seen in all parts of the world in recent years as hicles (EVs) have prompted the idea of using DC microgrid (DCMG)
countries endeavor to move towards a sustainable energy supply [1–4]. systems; to achieve increased efficiency due to the reduction of power
Efforts to integrate cleaner energy sources has resulted in increasing conversion stages [7]. Innovations in the areas of smart home­
amount of distributed generators (DGs) based on RESs, such as solar s/buildings, fast EV charging stations, vehicle to grid (V2G) technology,
photovoltaic (PV) arrays, micro wind turbines, biomass power plants hybrid energy storage systems, and renewable energy parks, DCMGs are
and fuel cells, being integrated to the utility network. However, the gaining increasing attention [8–11]. Although emerging as an attractive
increased penetration of DGs also brings along certain adverse impacts option for future power distribution systems, there are several con­
on utility grids, partly due to the intermittent nature of most RESs. The straints that hinder the widespread deployment of DCMGs. Protection of
major concerns include voltage rise, power quality, protection coordi­ DCMGs is one of the key issues [8,11]. Protection challenges associated
nation and system stability. Therefore, in order to accommodate high with DCMGs include [11–15]:
penetration of RES, more controllable, reliable, configurable and intel­
ligent energy distribution systems were needed. As a result, microgrids 1) Lack of frequency and phasor information making it difficult to
have emerged and become an attractive arrangement for the integration detect and locate faults.
of renewable-based DGs [5,6]. 2) Absence of natural zero crossings to extinguish the arc that occurs in
Microgrid is an active distribution network embedding DGs, energy breaker opening.
storage (ES) elements and consumer loads, and capable of operating 3) Fast current rise imposing strict time limits for fault interruption.
either grid-connected or as an autonomous island system. A microgrid

* Corresponding author.
E-mail address: [email protected] (D.K.J.S. Jayamaha).

https://doi.org/10.1016/j.rser.2019.109631
Received 17 February 2019; Received in revised form 27 September 2019; Accepted 27 November 2019
Available online 13 December 2019
1364-0321/© 2019 Elsevier Ltd. All rights reserved.
D.K.J.S. Jayamaha et al. Renewable and Sustainable Energy Reviews 120 (2020) 109631

Nomenclature ACCB AC circuit breaker

HVDC High voltage DC
English symbols MVDC Medium voltage DC
Rf Fault impedance IED Intelligent electronic device
Vdc DC bus voltage di/dt Derivative of current
Van AC side line to neutral voltage FTT Fast Fourier transform
Ivsc Current through lower terminal of VSC STFT Short-time Fourier transform
Vpoleþ DC positive pole to the ground potential WT Wavelet transform
Idc DC line current ANN Artificial neural network
Ig Ground fault current DWT Discrete wavelet transform
Rg Ground fault impedance ETO Emitter turn off
MMC Modular multi-level converter
Acronyms used FCL Fault current limiter
DCMG DC microgrids DCCB DC circuit breaker
DG Distributed generator SSCB Solid-state circuit breaker
RES Renewable energy source IGBT Insulated gate bipolar transistor
PV Photovoltaic IGCT Insulated gate commutated transistor
EV Electric vehicle ZSCB Z source circuit breaker
ES Energy storage SCR Silicon controlled rectifier
V2G Vehicle to grid SiC Silicon Carbide
PE Power electronic GaN Gallium Nitride
G-VSC Grid-connected voltage source converter HCB Hybrid circuit breaker
DESAT Desaturation FMS Fast mechanical switch
ACMG AC microgrid CS Commutating switch
CB Circuit breaker

4) Protection coordination issues due to the intermittent nature of RESs 6, respectively. Finally, the conclusions and future trends are provided
and different modes of operation. in Section 7.
5) Absence of protection standards, guidelines and lack of practical
experience. 2. Fault characteristics in DC microgrid systems

An adequate level of speed, sensitivity, precision, selectivity, and In this section, the DCMG fault characteristics are analyzed in order
security, are the key requirements of an effective protection system [16]. to identify the trends of voltage and currents within the network, and to
Conventional fault detection, localizing and interruption devices are get insights on the protection requirements of a DCMG. In order to
largely inadequate for DCMG protection [15,17–19]. analyze the fault characteristics of a DCMG system, consider the
The main objective of this paper is to present a comprehensive and notional DCMG network shown in Fig. 1. In a DCMG, the possible fault
analytical review on the state of the art protection techniques for types are pole-pole, pole-ground and AC grid faults, and are shown in
DCMGs. Furthermore, an in-depth investigation has been made to Fig. 1. These faults can occur in the DC bus, within converters, AC grid,
identify transient fault characteristics, effects of electrical parameters on DG sources, ESs and load branches [24–26]. Pole-ground faults are the
fault current, and limitations of currently available protection devices. most common type of fault in a distribution network [27]. Often
In addition to the post fault behavior of individual converters, simula­ pole-pole faults are low impedance faults, while pole-ground faults can
tion studies are presented to investigate the overall DCMG system be either low or high impedance faults. These faults are critical for the
response under fault events. Grounding configurations utilized in DC whole network; in particular, power electronic (PE) converters and
networks are detailed, and their advantages and limitations are battery units [24].
compared in terms of; personnel and equipment safety, fault detection Fault characteristics vary with the fault type and the fault location.
capability, fault ride-through capability and minimizing stray current Other key factors which influence the fault characteristics are fault
induced corrosion. Protection techniques, which appear to be effective impedance Rf, microgrid topology, grounding configuration, DG inter­
and feasible to implement in DC networks are reviewed. Compared with face converters and types of DG sources [7,25–30]. Under this section,
previous review studies in Refs. [20–23], this paper presents a more transient and steady-state characteristics of DCMGs during most com­
detailed study into the adoption of novel data-driven DCMG protection mon faults, pole-pole and pole-ground faults are analyzed based on
schemes. Ground fault behavior of the network under different simulation results. These fault characteristics are important when
grounding configurations is evaluated under different considerations to designing fault detection, interruption schemes and protection coordi­
provide insights into the DCMG grounding system design. Furthermore, nation [11,25–28].
fault current limiting converter architectures and interrupting devices
adopted in DC networks are compared in detail, considering several key
2.1. Power electronic converter fault response
performance parameters.
Rest of the paper is organized as follows; Section 2 discusses different
A fault in the DC network causes the DC side capacitors of the power
fault types in DCMGs, and provides an in-depth analysis of fault features
electronic (PE) converters to discharge rapidly, and DC bus voltage Vdc,
of a DCMG. The protection challenges in DCMGs are identified in Section
drops as a result. The fault current during the capacitor discharge de­
3. Different grounding arrangements and design considerations in
pends on the total DC side capacitance and the total fault current loop
selecting a grounding arrangement for a DCMG are discussed in Section
impedance. The DC side capacitance is the total cumulative capacitance
4. Fault detection and interruption schemes that are employed or pro­
of grid-connected voltage source converter (G-VSC) capacitor, other
posed for DCMG systems are discussed and compared in Sections 5 and
converter capacitors, and line capacitances. Fault loop impedance is

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D.K.J.S. Jayamaha et al. Renewable and Sustainable Energy Reviews 120 (2020) 109631

Fig. 1. Schematic diagram of the notional DCMG model.

reliant on fault impedance and fault location. must be considered when analyzing the PE converter behavior during a
The healthy operation of an IGBT based converter is assured only fault. Typically, desaturation (DESAT) protection activates within 2 μs
when antiparallel diodes across the IGBTs are reverse biased by the DC [31,32]. However, even if the converter operation is cutoff by
link voltage of the converter capacitor [13]. DC bus voltage Vdc, drops self-protection, PE converters may continue to conduct fault current
due to initial discharge of DC side capacitance during a fault, and if Vdc through freewheeling diodes of the converter, only to be limited by fault
goes below reverse bias voltage of the freewheeling diodes, PE con­ loop impedance, unless fault currents are interrupted [25,26]. These
verters may behave erratically. Fault current flow through the free­ diodes are sensitive to overcurrent, and the current through them must
wheeling diodes, and is only limited by network impedance upstream of not exceed a certain magnitude, determined based on their ratings [25,
the fault. 28]. DC network fault response depends on the PE converters interfacing
Commercially available IGBT based converters adopt self-protection DGs. Pole-pole fault response of two commonly used PE converters in
schemes for overvoltage and overcurrent protection, and their effects DCMGs, two-level VSC and DC-DC boost converter is examined in the

Fig. 2. (a) G-VSC with pole-pole fault, (b) Equivalent circuit for G-VSC fault current feeding through diodes.

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D.K.J.S. Jayamaha et al. Renewable and Sustainable Energy Reviews 120 (2020) 109631

following sub-sections. values, if Vdc goes below converter input voltage, Vin, freewheeling di­
odes are forward biased. Inductor current will increase, only to be
2.1.1. G-VSC fault response limited by fault current loop impedance. Hence, the fault current
Fig. 2(a) shows a VSC with a pole-pole fault in the DC side. Low fault through the converter will be higher than the nominal current of the
impedance, Rf values give rise to higher voltage drops due to DC side converter. The IGBTs may be blocked leaving the diodes exposed to fault
capacitor discharge; consequently, VSC loses its control capability [17, currents. Fig. 3(b) shows the equivalent circuit for fault current feeding
25,28]. from ES through diode path.
To analyze the fault characteristics of VSCs, three different stages of PV interfacing DC-DC converter shows a similar fault response.
fault response; capacitor discharge, diode freewheeling and grid current However, PV plant maximum current is limited; hence, the fault current
feeding stage are presented in Ref. [28]. DC link capacitor discharges contribution from the solar PV is limited.
immediately after a fault resulting in DC bus voltage drop. This capacitor DC-DC buck converters show a similar fault response to that of a
discharge initiates the diode freewheeling and current commutate to the boost converter discussed above [20]. Post fault response of dual active
freewheeling diodes. Due to the potential damages to the diodes and bridge based DC-DC converters is presented in Ref. [20].
other components, it is desirable to interrupt the fault current before the
VSC reaches diode freewheeling stage. However, if suitable protective 2.2. Pole-pole fault characteristics
actions are not taken, the VSC will continue to feed grid current to the
fault through freewheeling diodes. Fault response of VSC under each A pole-pole fault is the most critical condition in a DC network,
stage can be analyzed separately to derive expressions for DC link particularly because of the very high fault currents involved. Moreover,
voltage and cable current; thus provides the theoretical basis for the pole-pole fault on DC terminals of the network (see Fig. 1), can be
designing of protection schemes [20,28]. Post fault behavior of a VSC is considered as an additional load with low resistance [25].
explained below in order to investigate on overall response of the DCMG As discussed in Section 2.1, depending on Rf, fault location and fault
system under different fault events. type, PE converters in a DC network show different fault responses [25,
pffiffiffi
During a fault, if Vdc drops below 1:35 3V an (i.e. generated voltage 28,29]. Transient and steady-state current paths in the network during a
by a diode rectifier), where Van is the phase voltage of VSC input side, pole-pole fault are shown in Fig. 4. The trend of DC line current, Idc and
freewheeling diodes are forward biased and G-VSC is no longer PWM Vdc during a pole-pole fault are shown in Fig. 5. Initially, after the fault,
controlled; hence, VSC starts to work in an irregular way. As a result, DC capacitors discharge causing a sudden drop in Vdc, and is shown in Fig. 5
current fed by VSC Ivsc, rise to a considerably higher value, exceeding (a). DC link capacitor discharge results in a current transient with high
the converter nominal current. Also, with IGBT control signals being amplitude and very low rise time. This capacitor discharge causes a
blocked, there is no PWM control action by VSC [25,26], and will quick rise of Idc and can be seen in Fig. 5(b). Current from DGs increase
continue to feed fault current through diode path. The equivalent circuit rapidly and flow to the fault through diode paths [24,25,28]. Pole-pole
for G-VSC fault current feeding, through the diode path, is shown in fault characteristics in a ring-type DCMG are further investigated in
Fig. 2(b). However, for high Rf values, if Vdc is not dropped below Ref. [33].
pffiffiffi
1:35 3V an , no freewheeling diode conduction occurs, and critical
current levels are avoided [25,28]. 2.3. Pole-ground fault characteristics

2.1.2. DC-DC boost converter fault response Networks with different grounding configurations show different
DGs connected to the DC bus contribute to the fault through inter­ ground fault characteristics. The notional DCMG (see Fig. 1) under
facing converters. Fig. 3(a) shows a DC-DC converter with a pole-pole consideration for this analysis has the neutral point of AC side trans­
fault. The fault response of a boost converter is similar to that of a former solidly grounded and DC bus ungrounded. During a pole-ground
VSC with three stages; capacitor discharge, diode freewheeling and DG fault on the terminals of the DC bus (Fig. 6), PE converters show a similar
current feeding stage, and is further discussed in Ref. [20]. response to that of a pole-pole fault discussed in Section 2.1 [25–27,33,
Similar to VSCs, DC-DC converter capacitors also contribute to the 34].
initial capacitor discharge current resulting in the Vdc drop. For low Rf During the ground fault Vdc drops and forward bias the freewheeling
diodes, and AC grid, ES and solar PV plant feed the fault through diode
paths as shown in Fig. 6. For the ES and PV plant, a current reclosing
path for possible ground fault contribution is absent during high Rg
faults [27]. However, if ground fault component through G-VSC is
higher than the current flowing in the DC negative pole into the lower
terminal of the G-VSC Ivsc-, current changes its direction and Ivsc- starts
to flow through the lower terminal of the VSC into the DC negative pole.
As a result, for low Rg values, both PV plant and the ES contribute to the
ground fault, as shown in Fig. 6 [25–27].
In case of the activation of IGBT self-protection schemes, the fault
current path of ES and solar PV through the VSC lower terminal is
blocked off. However, the fault is still fed by the AC grid through the VSC
freewheeling diode path.
The trend of DC positive pole to ground potential, Vpoleþ and ground
fault current, Ig are shown in Fig. 7. It can be seen that Vpoleþ and Ig have
the same frequency and waveform pattern during the fault. Ground fault
characteristics of DC networks employing different grounding configu­
rations are further analyzed in Refs. [25–27,34].

3. DC microgrid protection requirements and challenges

Fig. 3. (a) DC-DC converter with pole-pole fault, (b) Equivalent circuit for DC- Designing a power network protection scheme is a comprehensive
DC converter fault current feeding through diodes. task that involves several challenges [16]. Key requirements of DCMG

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D.K.J.S. Jayamaha et al. Renewable and Sustainable Energy Reviews 120 (2020) 109631

Fig. 4. Fault current flow paths during a pole-pole fault in a DCMG network [25].

Fig. 5. Trend of (a) DC bus voltage (top), (b) DC line current (bottom), during a pole-pole fault in a DCMG.

Fig. 6. Pole-ground fault current paths in a DCMG with neutral point of AC side transformer solidly grounded- DC bus ungrounded [26].

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D.K.J.S. Jayamaha et al. Renewable and Sustainable Energy Reviews 120 (2020) 109631

Fig. 7. Trend of (a) positive pole to ground potential (top), (b) ground fault current (bottom), during a ground fault on the DC side, in a DCMG with neutral point of
AC side transformer solidly grounded- DC bus ungrounded.

protection and protection challenges are reviewed under this section. 3.2. Challenges: fault current interruption
The main protection requirements include personnel and equipment
safety, reliable fault detection, fast detection, minimum loss of load, AC currents naturally cross zero at every half cycle, causing the self-
fault ride-through capability and backup protection. These must be extinction of the arc between parting contacts of electromechanical
weighed against the cost of devising a protection scheme [16,19–23]. breakers. In a DC system, however, there is no zero-crossings and de­
mands the current to be forced to zero by additional mechanism [14,20,
3.1. Challenges: fault detection and discrimination 38,39]. Traditional AC circuit breakers (ACCBs) have been employed for
DC fault interruption, with considerable voltage and current derating
Lack of effective techniques for fault detection in DC networks rep­ [18,40]. In addition, specially designed mechanical CBs with arc chutes
resents a major barrier to widespread adoption of DCMGs. Conven­ can be used to dissipate and cool the arc [38]. However, these require
tionally most of the DC networks are protected by overcurrent and large and expensive arrangements.
differential elements. However, due to the intermittent nature of DGs DCMGs rely on PE converters for the integration of DGs and battery
connected to the network, different modes of operation and high units. PE converters have a limited fault current withstand capability,
sensitivity of network response to fault impedance, protection of DCMGs typically in the range 2–3 times nominal load current for few tens of
using the above mentioned conventional techniques is not straight for­ microseconds. In addition, DC systems have very short current rise time
ward; changing fault level and changing power flow direction pose resulting in a rapidly increasing fault current transient. Consequently, a
challenges to relay coordination [17]. In addition, complex network fault in a DCMG must be detected and interrupted quickly before
architectures may lead to suboptimal fault discrimination, resulting in reaching critical fault current levels [40]. Electromechanical CBs have a
disconnection of healthy sections of the network. Hence, the conven­ long interruption time due to their mechanical restrictions, and cannot
tional fault detection schemes have become largely inadequate [17, interrupt DC fault current within the required time and current limits
20–24], and there is a need for sensitive, intelligent and adaptive DC [37,41]. Fast breaker designs based on solid-state switches have become
fault detection and discrimination schemes. widely popular for DC protection [42]. However, due to their high costs,
Fault localizing is a crucial requirement, as quick isolation of the high on-state losses, large volume and weight, and susceptibility to
faulty section of the network is essential for fast recovery of the network. overvoltage, it is still questionable whether they offer an effective so­
Line impedance and traveling wave methods have been adopted as an lution [42,43]. DCMG fault interruption schemes are discussed in Sec­
industry standard for fault localization in AC networks [35]. However, tion 6.
the inherent absence of frequency and phasor information prevents the
direct adoption of line impedance based methods in DC systems [36,37]. 4. DC microgrid grounding
In addition, due to the short length of distribution cables, it is difficult to
obtain exact time difference, which rules out the possibility of using System grounding is an important factor for safe and stable operation
traveling wave methods for fault location. of a power distribution network [44]. Grounding aspects of DC networks
AC power system protection has plenty of standards, guidelines, and have not been fully explored, and there are still concerns about safety
experience, which can be easily translated to AC microgrids (ACMGs). [42,45]. Hence, it is important to address the grounding issues and
Standards for protection are absent when it comes to DC systems [21,35, identify the grounding configurations that enable safer and more reli­
36]. In addition, protection devices for AC systems are very mature and able operation of the network.
commercially available. Conversely, DC protective devices are costly, as Grounding is a complex topic involving several design considerations
they are specialty devices to-date. DCMG fault detection and localization and tradeoffs [45–47]. In order to contribute to a better understanding
techniques are discussed in Section 5. of DCMG grounding, this section will review different grounding con­
figurations adopted, based on the following considerations [26,45];

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1) Facilitation of reliable ground fault detection. there will be high stray current. Hence, when designing a grounding
2) Fault ride-through capability during ground faults. scheme, considerations to be prioritized are decided according to the
3) Limiting touch voltages and fault currents to safe levels. specific application the network being used for.
4) Immunity to disturbances and noise in the network. The following grounding configurations have been proposed in the
5) Minimizing stray current induced corrosion. literature for DCMG system grounding [20,31,47–51];

Safety of both personal and equipment is the main objective when 1) Ungrounded DC bus
designing a grounding scheme. Fault current magnitudes, fault detection 2) High resistance grounding
capability, susceptibility to faults and voltage surges are the factors to be 3) DC bus solid grounding
considered in this regard. 4) DC bus midpoint solid grounding
Compatibility of a ground fault detection scheme for a particular 5) Reconfigurable grounding
network depends on the grounding configuration [26,45]. In addition,
the grounding configuration endows the ground fault ride-through In general, a DCMG is interfaced to the AC utility grid [31]. AC grid
capability to the network. While solidly grounded networks have can have different grounding configurations such as TN, TT, IT [52]. AC
certain positive attributes, their inability to ride-through faults and grid side grounding arrangement of a network has its impacts on
maintain service in the presence of a ground fault, outweighs in certain selecting the DC side grounding arrangement [20,21,25–27].
applications. Conversely, ungrounded or high resistance grounded sys­ In IEC 60364-1 grounding configurations for the grounding of DCMG
tems offer good fault ride-through capability, but the network is prone to components are categorized as TT, TN-S, TN-C, TN-C-S and IT, and are
disturbances. Especially during a fault transient, aggregate pole to further reviewed in Ref. [20]. However, in this study, we mainly focus
ground capacitance and cable inductance may lead to underdamped on DCMG system grounding configurations, and design considerations
oscillatory overvoltages with respect to ground, that potentially cause in the selection of DCMG system grounding configurations.
insulation and equipment damage [47]. Under this section, solidly grounded AC grid and ungrounded AC
Corrosion due to stray current is a major problem associated with DC grid systems are considered separately to investigate the possible DCMG
networks [48,49]. Structural damages to the network components due system grounding configurations, and features of a DCMG network with
to corrosion can be avoided, by taking measures to reduce the stray these grounding configurations. For better comparison and to summa­
current [48–51]. In a high resistance grounded or an ungrounded rize the discussion below, comparative analysis of different DCMG
network, stray current will be minimized, but the network is prone to grounding configurations and their features are provided in Table 1.
transient overvoltages, as discussed above. On the contrary, if the
network is solidly grounded, transients will be quickly absorbed, but

Table 1
DC microgrid grounding configurations, and their characteristic features.
DC bus grounding configuration Fault detection Fault ride- Ground fault Stray Transient Remarks
schemes applicable through current current over-voltages
capability magnitude

Neutral point of AC side transformer � Ground current No High High Low � Fault detection is relatively easy.
solidly grounded, DC bus monitoring.
ungrounded. � Insulation
monitoring
Neutral point of AC side transformer � Ground current No High High Low � Fault detection is relatively easy.
ungrounded, DC bus solidly monitoring.
grounded. � Insulation
monitoring
Neutral point of AC side transformer � Insulation Yes Very low Low High � Ground faults should be cleared to
ungrounded, DC bus monitoring. prevent subsequent ground fault
ungrounded. creating a pole-pole fault.
Neutral point of AC side transformer � Ground current Yes Moderate Moderate/ High/ � Low resistance grounding is proposed to
ungrounded, DC bus high monitoring. low Moderate mitigate high transient overvoltages
resistance grounded. � Insulation during disturbances.
monitoring.
Neutral point of AC side transformer � Detection of pole Yes low (only a High Low � Reduces insulation requirements as
ungrounded, DC bus midpoint voltage shift. transient Ig) touch voltage is half the nominal
grounded. � Ground current voltage.
monitoring. � Protection of both poles required.
� Insulation
monitoring
Neutral point of AC side Transformer � Detection of pole Yes Low High High � Limits the transient capacitor discharge/
ungrounded, DC bus midpoint voltage shift. charge current.
high resistance grounded. � Ground current
monitoring.
� Insulation
monitoring
Neutral point of AC side Transformer � Ground current No High Moderate/ Moderate/ � Diode grounding does not completely
ungrounded, DC bus monitoring. low low eliminate the stay current induced
reconfigurable grounding. � Insulation corrosion.
monitoring � Reverse diode grounding can eliminate
the issue of stray current.
� Thyristor grounding scheme provides
the flexibility to operate in both
ungrounded and grounded
configurations.

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4.1. Solidly grounded (TT/TN) AC grid network monitor the system response, in order to identify the drop in insulation
level due to a ground fault [55,59–61].
In a network with solidly grounded AC grid, solid grounding of the The main disadvantage of an ungrounded network is, it poses a
non-isolated DC bus creates a permanent fault. Hence, AC grid network danger to the public, as the bus voltages may reach an elevated level
with solidly grounded neutral, preclude the possibility of solid with respect to the ground. Furthermore, they are very susceptible to the
grounding of the DC bus, unless the network is electrically isolated using noise, and disturbances in the network could give rise to underdamped
an isolation transformer, as in Fig. 8(a). However, the use of isolation transient overvoltages, which could deteriorate insulation and damage
transformers increases the installation costs, and not used often [53,54]. the equipment [47].
Another possible grounding arrangement without using an isolation
transformer is to keep the DC bus ungrounded as shown in Fig. 8(b). As 4.2.3. High resistance grounding
discussed in Section 2.3 ground current level in this network could be High resistance grounded systems (Fig. 9 (c)), similar to ungrounded
considerably higher than the permissible level of 30 mA, as in IEC networks, enables fault ride-through capability as a low resistance path
60479-1 [44]. Therefore, it is required to implement appropriate ground for the circulation of Ig is absent [45,62–64]. The magnitude of Ig during
fault protection measures [25,45]. a ground fault can be controlled at a safe level by careful selection of
Fault detection in this grounding configuration is fairly easy, as it grounding resistance; certain tradeoffs are made in the selection of
typically gives rise to significantly high Ig, and ground current moni­ grounding resistance [26,45].
toring based ground fault detection schemes are adequate. However, Generally, grounding resistance is selected such that, a ground fault
high impedance faults which result in significantly low Ig require more causes a modest current flow to facilitate fault detection, but is not high
sensitive fault detection scheme, such as insulation monitoring [25,26]. to pose a threat to the personal (should be less than 30 mA to be
consistent with IEC 60479-1 standard) [45,45]. Ground current moni­
toring and insulation monitoring relays can be employed to detect
4.2. Ungrounded (IT) AC grid network
ground faults in these networks. A directional element for localization of
ground faults in high resistance grounded networks was proposed in
Networks with AC side transformer neutral point ungrounded pro­
Ref. [63]. In addition, digital signal processing based method has been
vides more flexibility in selecting DC bus grounding configuration.
proposed to locate faults in high resistance grounded networks in Refs.
Possible DC bus grounding configurations are; 1) DC bus solid
[65–67].
grounding 2) ungrounded DC bus, 3) high resistance grounding, 4) DC
Similar to ungrounded DC networks, in high resistance grounded
bus midpoint solid grounding, 5) DC bus midpoint high resistance
networks stray current flow is minimized, but are prone to transient
grounding and 6) reconfigurable grounding [25,26,45].
overvoltages during disturbances [47,55]. The literature proposes the
use of low resistance grounding of DC bus [47,55]. As opposed to high
4.2.1. DC bus solid grounding
resistance grounding, one commonly perceived benefit of low resistance
DC bus solidly grounded systems (Fig. 9(a)) give rise to significantly
grounding is the damping of oscillations caused by transient distur­
high Ig, as it will effectively create a pole-pole fault during a ground
bances [47].
fault. Therefore, the network responds as in a pole-pole fault situation
(see Section 2.2), and quick protective actions are required [25,26,55].
4.2.4. DC bus midpoint point solid grounding
Ground current monitoring relays can be employed to detect ground
In a DC bus midpoint solidly grounded network (Fig. 9(d)), the po­
faults in these networks [55]. Ground currents of few milliamperes are
tential of each pole is half the pole-pole voltage, which reduces the
easily detected by currently available high sensitive ground current
insulation requirements. However, both poles have potential with
monitoring relays [56,57]. Ability to absorb disturbances in the
respect to ground, and necessitate the protection of both poles of the
network, and mitigate voltage spikes from such disturbances, is another
network [26,45,46].
advantage of this configuration. However, these networks are subjected
In this configuration, during a ground fault, the network is subjected
to corrosion due to stray current flow [26,50,54].
to Ig caused by DC link capacitor charge-discharge. However, the system
is free from Ig in steady-state. Literature suggests DC bus midpoint
4.2.2. Ungrounded DC bus
grounding through a high grounding resistance, in an effort to limit the
Ungrounded DC bus system (Fig. 9(b)) enables fault ride-through
initial capacitor charge-discharge current magnitude [26,45]. Pole
capability during ground faults. It has a zero or very low Ig with a sin­
voltage shift indicates the occurrence of a ground fault in these networks
gle ground fault [58]. However, subsequent ground faults may create a
and is used for detection [55,59]. However, a voltage shift based ground
pole-pole condition and can cause significant system damage. Hence, the
fault detection has its limitations on detection speed and the ability to
initial ground fault should be cleared immediately.
locate the faults [26,59].
Ground current monitoring schemes cannot detect ground faults in
Also, this grounding configuration endows ground fault ride-through
this system, and require more sensitive schemes. One such scheme is
capability to the network. In addition, the inherent drawbacks of high
insulation monitoring, where AC or DC signal injection is used to

Fig. 8. Possible grounding configurations with neutral point of AC grid transformer solidly grounded networks (a) DC bus solidly grounded with isolation trans­
former, (b) DC bus ungrounded network [54].

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Fig. 9. Possible grounding configurations with neutral point of AC side transformer ungrounded networks, (a) DC bus solid grounding, (b) DC bus ungrounded, (c)
high resistance grounded, (d) DC bus midpoint grounding, (e) diode grounding, (f) thyristor grounding [45,50,51].

resistance grounded and ungrounded networks such as bus voltage blocked, and at the same time, transient overvoltages created in the
reaching elevated levels and transient overvoltages caused by distur­ network are diminished.
bances, are eliminated [45].
� Thyristor grounding
4.2.5. Reconfigurable grounding options in DC microgrids
As discussed earlier, minimizing stray current and avoiding unsafe Unlike diode grounding, thyristor grounding shown in Fig. 9(f) offers
transient overvoltages are two contradictory requirements, when more control over the grounding configuration. In this scheme, if the
selecting a grounding configuration for a DCMG. Contrary to the DC ground to negative bus voltage rises above a threshold value, thyristor
network grounding methods discussed earlier, in Ref. [51], it presents gate is triggered to ground the DC bus [49–51]. The main advantage of
reconfigurable grounding methods for DC traction networks, where the thyristor grounding over diode grounding configuration is, its ability to
network is operated in ungrounded configuration to reduce the corro­ maintain DC bus ungrounded, minimizing the stray current [50,51].
sion intensity, and upon detection of a high voltage, the network is From the above discussion, it is clear that different tradeoffs have to
grounded to reduce the voltages to safe levels. be taken into consideration when deciding the grounding configuration
Reconfigurable grounding options are mainly proposed for DC trac­ for a particular application. A wide system study is required in selecting
tion networks as a means of reducing the stray current [49,68]. Use of the appropriate DCMG grounding configuration, and ground fault
reconfigurable grounding configurations for DCMGs has not been detection technique should be selected accordingly.
explored yet.
5. DCMG fault detection and localization
� Diode grounding
Fast and accurate fault detection and localization is an essential
Diode grounding involves solid grounding of DC bus through a diode requirement for network protection. However, as discussed in Section 3,
as shown in Fig. 9(e). Here, the current is allowed to flow from the there are several challenges for the design of DCMG fault detection
ground towards the negative bus if the voltage across diode exceeds its schemes. Fault detection techniques for DCMGs are still in the early
forward voltage. stage of development, compared to ACMGs. Moreover, the absence of
For small magnitudes of voltage between ground and the negative frequency and phasor information limit the use of well-established fault
pole, the diodes would conduct, resulting in relatively high stray cur­ detection methods in AC systems [13,24,35].
rents. Hence the problem of stray current induced corrosion is not When designing a DCMG protection system, knowledge of the
completely eliminated in this scheme [49–51,68]. In Ref. [48] a reversed existing DC power networks such as HVDC, shipboard and traction
diode grounding scheme is proposed to eliminate the issue with stray networks, is of assistance. However, most of these networks utilize
current. By placing the diode in reverse direction, stray currents are converters with current limiting capability. In contrast, DCMG system

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needs to be interfaced with AC grid using a bidirectional converter; section current protection scheme is proposed for the protection of
consequently, different protection schemes are required for DCMGs MVDC lines. This scheme adopts an instantaneous overcurrent threshold
[24]. Moreover, fault detection in DCMGs has been more challenging as primary protection, and time limit overcurrent threshold as backup
due to their small scale, embedding DGs and higher safety requirements. protection. However, the inability to detect high impedance faults and
Also, while most of these DC networks are used for point to point ap­ inadequate level of selectivity are major drawbacks of these schemes.
plications, DCMGs are by nature multiterminal networks. Fault detection technique relying on intelligent electronic devices
There are several factors that should be taken into consideration in (IEDs) and communication between IEDs is proposed in Ref. [36].
the design of fault detection scheme: the type of faults that can occur, the Current readings from IEDs are used for overcurrent and differential
severity of the faults, network arrangement, grounding configuration, fault detection with predetermined threshold values. This scheme allows
fault current flow paths, need for backup protection, protection coor­ the selective isolation of faulted segments. Moreover, differential pro­
dination, types of fault interruption devices, time limits for fault inter­ tection using IEDs enables the detection of high impedance faults. In
ruption and measures to prevent faulty operation of the protection Ref. [71], a similar approach for fault detection, using IEDs, where
devices. In addition, component level (eg: - IGBTs), device level (eg: - current magnitudes, direction and voltage levels are monitored, is
VSC) and system-level protection schemes should be properly coordi­ proposed.
nated [16,24,25].
5.1.2. Derivatives of current
5.1. DCMG fault detection schemes In Ref. [24], the use of derivatives of current (di/dt) for fast detection
of faults within DC networks is discussed. Immediately after a fault, the
Currently available techniques for fault detection in DCMG systems, discharge of the DC link capacitors can result in fault current transient,
and their performance are reviewed under this section considering the until it is damped by fault loop impedance. In order to interrupt the fault
criteria: detection accuracy, fault diagnosis and localization capability, prior to the peak current discharge of DC capacitors a fast fault detection
sensitivity, communication and sensory requirements, integration method is required, which makes di/dt based protection schemes more
complexity and cost of realization. Fault detection and localizing tech­ suitable for DC networks [24,72].
niques employed in HVDC, MVDC shipboard, traction networks and Fault detection scheme based on initial di/dt is discussed in
ACMGs are also reviewed under this section, to envisage their suitability Ref. [73]. This initial di/dt fault detection concept utilizes DC link
for DCMGs. capacitance initial response to a fault to estimate the fault location and
relay coordination. This study shows that there is a similarity in the
5.1.1. Overcurrent detection initial response for both low and high impedance fault conditions,
Due to simplicity, overcurrent protection schemes are commonly although for high impedance faults di/dt decays more rapidly. Hence,
used in AC as well as DC systems. The objective is to identify abnormal detection of high impedance faults is possible by using initial di/dt
currents flowing in the circuit and identify fault events. However, there response [73]. Although di/dt schemes offer very fast fault detection,
are several difficulties to use overcurrent schemes in DCMGs. As dis­ the accuracy is affected by disturbances and noise in the network [17,24,
cussed in Section 2, fault current parameters, such as magnitude and 73].
direction, depends on network architecture, grounding scheme, fault
impedance, fault type, fault location, converters used to interface DGs to 5.1.3. Differential protection schemes
the DCMG and operating mode of the microgrid. In addition, the fault Differential protection schemes are used to provide zonal protection
loop impedance determines the natural frequency and damping factor of to predefined protection zones. Varying loading levels, the existence of
the current transient. The simulated fault currents are shown in Fig. 10, DGs and different fault levels have no impact on detection accuracy and
in which fault currents with different fault resistances (0.2 and 0.7 Ω) sensitivity of a differential protection scheme; hence, making it a good
are shown. It clearly shows the influence of fault impedance on fault option for protection of microgrids both AC and DC [13,17,36]. Fig. 11
current magnitude and oscillatory response. shows the schematic diagram for the implementation of a differential
Changing fault levels and changing power flow direction may cause scheme to protect a selected DC feeder segment.
relay coordination issues, delayed and non-operation of relays, and false In Ref. [74], a differential scheme is proposed, where each protection
tripping [17,24]. In Ref. [69] a smart relay utilizing current and voltage zone consists of a master controller and two slave controllers. Slave
levels to detect faults is discussed. If the current through the converters controllers monitor currents at two ends of the protected zone, and send
exceeds a threshold value and stays above beyond a certain time, and it to the master controller. In case of a fault, the difference of current at
voltage drops below 0.8 pu, a fault is detected by the relay. Relays are two ends exceeds a certain threshold, and the master controller sends a
embedded in the converters and DCMG is divided into several zones, signal to the slave controllers to isolate the faulty section.
which allows the relays to operate autonomously. In Ref. [70] two Differential schemes rely on communication between protective

Fig. 10. DC line current waveform during a pole-pole fault (at t ¼ 0.1s), with a fault impedance of 0.2Ω and 0.7Ω.

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D.K.J.S. Jayamaha et al. Renewable and Sustainable Energy Reviews 120 (2020) 109631

DC waveform analysis. Fig. 12 shows the discrete wavelet trans­

formation (DWT) of the DC line current waveform during a ground fault,
up to 5 levels of decomposition. In this study, a sampling frequency of
50 kHz and Daubechies 5 (db5) mother wavelet is used. It can be seen
that there is a clear increase in magnitudes of the detail coefficients
during the fault, especially in detail levels 2, 3 and 4.
The general approach for Wavelet based fault detection is capturing
characteristic features of a fault signal by using WT and applying these
characteristics to an algorithm as a variable to detect faults. There are
different approaches to capture these characteristics. One such approach
is to compare the value of detail coefficients. In Ref. [80], fault detection
Fig. 11. Differential current scheme for a DCMG distribution feeder protec­
and localization scheme based on detail coefficients of current and
tion [13].
voltage signals is discussed.
Adopting the wavelet coefficients directly for fault detection requires
devices on both ends of the protection zones for fault detection. Hence,
large memory space and computing time. WT based technique for fault
communication delay between protection devices should be taken into
detection in MV shipboard power systems proposed in Ref. [76] uses the
consideration, when devising a differential scheme.
energy variations in detail coefficients. In this approach, Perceval’s
theorem is used to reduce the quantity of feature vector without losing
5.1.4. Distance protection
its original properties, and thus, required memory and processing time
Traditional AC networks adopt distance protection schemes, which
has reduced. In addition, several statistical measures for fault feature
uses impedance to represent the occurrence of a fault and distance from
extraction with reduced quantities have been discussed in the literature
the relay to the fault location. However, during a fault transient in a DC
[80,82].
system, there are rapid oscillations and frequency changes, where no
In addition, literature proposes the use of signal processing in com­
fundamental frequency can be defined. Novel techniques for electrical
bination with pattern recognition techniques to detect faults and is
parameter evaluation to determine the system impedance, which in­
discussed in the following section.
dicates the occurrence and distance of fault in a DC network, have been
proposed in Refs. [28,75].
5.1.6. Pattern recognition schemes
In Ref. [75], distance protection scheme for DC shipboard systems
In recent years a growing interest to employ data-driven or pattern
based on active impedance measurement is discussed. The network is
recognition approaches for power system control and protection is seen.
injected with a current signal with a wide frequency range and the
Pattern recognition based fault detection overcomes the drawback of
resultant voltage is measured to calculate the equivalent impedance.
having to define hard thresholds, and aids in accurate fault detection
Impedance estimation technique for DC systems without external
unaffected by disturbances and noise. The steps involved in fault
signal injection is discussed in Ref. [28]. Voltage reference comparison
detection and classification using pattern recognition techniques are
method is used to determine the pole-pole fault location. Moreover, the
depicted in Fig. 13.
ground fault location is determined by analyzing the initial fault
Artificial neural networks (ANN) have already been applied in AC,
transient.
HVDC and MVDC networks for fault detection and have shown to be
accurate, robust and fast in performance [82–87]. Application of ANN
5.1.5. Signal processing based fault detection
for detection and classification of faults according to fault type and
Lack of time domain information in fast Fourier transforms (FFT)
location, in DCMG networks have been studied in Refs. [88,89]. An ANN
makes it difficult to be used for transient signal analysis. This limits the
can determine the existence of normal, faulty conditions and different
use of FFT based methods for power system protection [76]. However,
fault locations, fast and accurately. ANNs are trained using post-fault
short-time Fourier transforms (STFT), which analyses the signal in both
data at different locations and different fault levels to ensure correct
time and frequency domains, is being widely studied for power system
protection applications [76,77].
Utilization of STFT for quantitative investigation of high frequency
harmonics during fault transients in DC networks is presented in
Ref. [78]. Various factors that affect the STFT based fault detection, such
as sampling frequency, type of window functions, window size, number
of FFT points and external factors such as ripple in the voltage and
current signals were investigated in Ref. [78]. However, capabilities of
STFT for signal processing is limited due to constraints on window size,
i.e wide time window will result in particularly good frequency reso­
lution but poor time resolution. Conversely, the narrow time window
will result in poor frequency resolution but good time resolution.
Wavelet transform has the capability to decompose a time-frequency
signal into specific time-frequency resolutions. Hence, offers better time
and frequency resolution compared with STFT and FFT techniques.
Wavelet representation of a signal provides a portrayal of the variation
of the frequency content with time, and hence reveal when and what
type of transients take place in the signal. Wavelet analysis techniques
have been proposed extensively for several power system applications,
including fault classification and network event recognition [79–87].
Use of Wavelet transform (WT) to capture fault characteristics from
monitored signals in DCMGs and MV shipboard networks have been
discussed in Refs. [76,79–81] respectively. Simulation studies were
Fig. 12. DWT decomposition of DC line current signal, during a pole-ground
carried out to evaluate the effectiveness of using wavelet transforms for
fault, up to 5 detail levels.

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these pattern recognition techniques show a high level of effectiveness

in event classification applications such as HVDC fault detection, AC
microgrid fault detection and islanding detection [93–96], the applica­
bility of these classifier techniques for accurate detection of DCMG fault
events require further study.
For pattern recognition based fault detection, it is important to
determine which classification algorithm provides the best classification
performance. Moreover, the required level of accuracy, reliability and
speed of classification are the determinant factors when deciding what
sampling rates to be used, the processing power required, signals to be
monitored and amount of training samples required.
In this section comparative analysis on the performance of each fault
Fig. 13. Steps involved in pattern recognition based fault detection and
detection technique was provided. To summarize the above analysis,
classification. strengths and drawbacks of DC fault detection techniques are provided
in Table 2.
fault identification.
5.2. Fault localization and protection coordination requirements
In Ref. [90] relative wavelet energy variations in line current are
used to construct a feature vector. Fig. 14 shows the relative wavelet
Fault localization and protection coordination techniques employed
energy variations in 6 decomposition levels under different fault and
in DCMG systems are discussed under the sections below.
non-fault events. From Fig. 14, it is clear that the capability of the fault
detection scheme to identify fault events can be realized by comparing
5.2.1. Fault localization
the feature vectors extracted from current signals. The constructed
Fault localization is an essential requirement for the quick isolation
feature vectors are then used to train an ANN for DCMG fault detection
of the faulty segment. The absence of frequency and phasor information
and classification.
prevents the use of line impedance based distance protection scheme for
In Ref. [91] ACMG faults are classified according to fault type, phase,
locating faults. Furthermore, traveling wave based and signal injection
and location. The network line current signals were monitored to extract
based methods are ineffective since it is difficult to discriminate between
statistical features using DWT and a statistical feature vector is used as
reflected waves, as the cables are short in length. Differential protection
input to a deep neural network to develop a classifier scheme, which
schemes which protect bounded zones of the network presents an
achieves a significant level of classification accuracy compared to other
effective solution for fault localization. Differential schemes presented
schemes.
in Refs. [36,74], enables selective fault isolation capability, and were
A preliminary investigation on the use of different classifier tech­
previously discussed in section 5.1.3. Fault location estimation tech­
niques including; ANNs, decision trees and support vector machines for
niques based on local measurements are presented in Refs. [28,73].
fault detection and classification in MVDC shipboard power networks is
Selective positioning of fault interrupting devices working in conjunc­
presented in Ref. [92]. Pattern recognition based fault detection
tion with these fault localizing schemes enables selective fault isolation
schemes proposed in the literature demonstrate a significant level of
capability, to improve network reliability.
effectiveness in terms of classification accuracy, intelligent fault detec­
tion capability and robustness to measurement uncertainties. While

Fig. 14. RWE distribution in decomposition levels of DC line current under normal operation under (a) pole-ground fault in DC side, (b) pole-pole fault in DC side, (c)
fault in AC side, (d) normal operation, (e) load switching operation [90].

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Table 2
Comparison of strengths and drawbacks of different DC network fault detection schemes.
Detection technique Strengths Drawbacks

Overcurrent schemes � Simple and fast. � Sensitivity and relay coordination issues due to different levels of faults
� Adaptive overcurrent schemes have been developed, to overcome issues during different modes of operation.
due to changing fault levels and current directions. � Difficult to detect high impedance faults.
� Easier to implement. � Accuracy will be affected by network disturbances and noise in the
� Smart devices (IEDs) have been developed, to provide selective measurements.
protection.
di/dt based schemes � Simple and fast. � Accuracy affected by network disturbances in the network.
� Not affected by fault impedance. (can detect high impedance faults) � Mostly used in conjunction with other protection schemes. for backup
protection.
Differential schemes � High sensitivity and precision. � Based on device communication
� Simple and fast. � The requirement of synchronized measurements.
� Sensitivity not affected by fault impedance. � Protects only a bounded zone of the network.
� Facilitates selective tripping, minimizing interruptions to the healthy � Inability to provide backup protection to the adjacent zones of the
sections. network.
� Accuracy affected by sensor and communication errors.
� The high cost due to additional sensory and communication
requirements.
Distance protection � Simple and fast. � Mostly relies on the external signal injection for active impedance
schemes � Can provide backup protection to adjacent zones of protection. measurements.
� More sensitivity to fault resistance and location. � Sensitivity affected by fault impedance.
� Affected by network disturbances or noise in the network.
� Dependent on network architecture.
Signal processing based � Accurate and reliable. � Affected by network disturbances or measurement noise.
schemes � The possibility of identifying features of high impedance faults to detect � Additional sensory and signal conditioning requirements.
them more accurately. � Complex algorithms and difficulty to use in real time applications.
� Signal processing techniques in combination with pattern recognition � High cost of realization.
significantly improve detection accuracy. � Mostly non-unit schemes; hence, rely on device communication for se­
� Fault diagnosis and localization capability. lective tripping, upon fault location.
Pattern recognition � Accurate and robust. � Require large amount of training samples and training time.
based schemes � Intelligent fault detection capability. � Training data not globally available, and difficult to acquire.
� Fault diagnosis and localization capability. � Accuracy affected by training data.
� Complex structure, thus difficult to use in real time application.
� Selection of classification algorithm and feature vectors to meet strict
time limits for DC fault interruption is challenging.

5.2.2. Protection coordination strategies Protection coordination scheme between fuses and relays embedded
Protection coordination strategies are employed to coordinate be­ in fault current blocking converters is presented in Ref. [69]. Fast acting
tween primary and backup protection. Primary protection devices act as fuses which act as the primary protection device of the AC zone of the
the main protection device of a particular component or section of the network are used in this study. Relays which operates much faster than
DCMG. Backup protection is implemented in case of failure of primary the fuses are employed to interrupt faults in the DC side, thereby pre­
protection. The selection of primary and backup protection scheme is venting the fuses to blow off for faults in the DC side.
based on protection component, fault location, required fault clearing
time, identification of temporary and permanent faults and fault ride- � Communication based relay coordination
through capability.
An effective protection coordination strategy minimizes critical fault DCMG protection coordination based on communication between
clearing time, enables quick system restoration and minimizes outages. devices offers a reliable solution. In Ref. [32] Intelligent electronic de­
In Refs. [36,74] differential scheme with non-overlapping zones of vices (IEDs) are installed at different zones of the network, and
protection is adopted. However, the inability to provide backup pro­ communication link between IED is used to maintain proper coordina­
tection is a major drawback in these schemes. tion. The embedded sensors in IEDs monitor real time current mea­
This Section reviews protection coordination strategies based on surements and communicates the information between IEDs, which
time grading of relays and communication between relays, deployed in determines the faulted section and send trip signals. In Ref. [11] DCMG
DC distribution networks. protection scheme in which voltage and current information at different
relay locations are communicated between relays to determine fault
� Time grading of relays occurrence and fault locations is presented. The communication link is
of crucial importance for these protection schemes; hence, severely
In order to achieve selective protection capability, relays are time affected by communication delays and failures.
graded. In principle, operating times of the relays are set such that relays
closest to the fault operates first. Time grading of the relays enables the 5.2.2.1. DC microgrid fault interruption schemes. An effective protection
backup protection relays to operate if the primary protection fails to scheme requires the availability of fault interruption devices, which can
operate. block or limit fault currents and isolate faulty sections of the network. As
In Ref. [97] protection coordination scheme for a DCMG, employing discussed in Section 3, very fast current rise and absence of natural zero
fast acting fuses and circuit breakers for selective protection is pre­ crossing impose very critical time limits for fault current interruption in
sented. Fast acting fuses used at selected locations provide faster fault a DC network. Hence, DC network switchgear is required to operate very
clearing capability and are more cost effective compared with circuit fast, and special measures are adopted for DC current breaking and
breakers. Time graded overcurrent relay embedded into circuit breakers extinguishing the arc [24,36,37].
are deployed at selected locations to protect selected zones/components In Refs. [24,37], limits for fault current interruption in a VSC based
of the network.

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DCMG network is investigated. Current handling capabilities of PE de­ and current regulation capability on either side of the converter. This
vices were considered mainly in these studies. Restraining transient converter assembly is capable of blocking fault current, and prevents DC
overvoltages, coordinated operation, fault detection time, power losses, link capacitor discharge [100,101]. Once the fault is cleared, the con­
cost of implementation and ability to minimize outages are important verter is capable of immediate power supply once the fault is cleared,
considerations in the choice of fault interruption devices for DCMGs. In because the DC link capacitor remains charged.
this section, currently available switchgear and proposed schemes for The requirement of two active VSCs which consequently increases
DC fault interruption are discussed. the converter size and installation costs is a main drawback. In addition,
two conversion stages increase the power loses compared to single VSC
configuration.
5.3. Converter blocking and current limiting schemes

5.3.3. Isolated DC-DC converter

Most HVDC and MVDC applications including shipboard power
Isolated DC-DC converter architectures capable of controlling cur­
systems and traction networks use PE converters with fault current
rent under fault events are discussed in Refs. [100,103–105]. Dual active
blocking capability. It allows the fault current to be interrupted quickly
bridge (DAB) converter architecture employing two full-bridge con­
through converter blocking. As discussed in Section 2, typical IGBT
verters connected through a high frequency transformer is shown in
based converters are equipped with IGBT self-protection schemes such
Fig. 17. DC Fault characteristics of a DAB converter is discussed in
as DESAT protection, to protect against fault current [31,32]. However,
Ref. [20]. DAB converter has an inherent capability of limiting fault
the fault current will continue to flow through freewheeling diodes with
current during a fault in either side of the converter [20,100].
no possible means of limiting. Hence, it is not possible to employ con­
For high power applications, several modular multilevel DAB ar­
verter blocking schemes with conventional VSC and buck/boost archi­
chitectures are proposed in literature [100,102,106]. Although tradi­
tectures, and require modifications to the converter architecture to
tionally modular multilevel converters are employed in HVDC networks,
achieve current blocking capability [24,98].
as they require high number of active switches and have several con­
Conventional converters, although limits maximum current flow
version stages; Hence are not cost effective for LVDC and MVDC appli­
during normal operation, are incapable of limiting fault current. How­
cations. However, recent developments in the wideband gap devices
ever, specially designed converters which have the current limiting ca­
(WBG) devices such as silicon carbide (SiC) and Gallium nitride (GaN)
pabilities during a fault in the network are discussed in Refs. [98–105].
presents a viable option to fully exploit the advantages of these con­
Fault current limiting converters adopt multi-mode control schemes,
verter architectures for LVDC and MVDC distribution networks [20,107,
and changes the control scheme to limit current upon detection of a
108].
fault. These converters working in coordination with protection devices
Fig. 18 shows a modular multilevel DAB architecture, which com­
minimizes the risk of damages to the network, and increase the resil­
prises of several submodules. These submodules can be actively
ience and fault ride-through capability of the network. Loss of power to
controlled to limit the fault current. Since the submodule capacitors are
the healthy sections of the network is a major drawback in this scheme.
decoupled from the output, transient fault current due to capacitor
Fault current blocking converter architectures for DC distribution net­
discharge can also be actively limited. Furthermore, submodule capac­
works are discussed below.
itors act as an energy buffer, enabling fault ride-through capability
against temporary faults [100,106].
5.3.1. ETO thyristor based converters
In order to achieve fault current blocking capability, replacing the
5.3.4. Modular multilevel converter architectures
freewheeling diode of the VSC by ETO thyristors is proposed in
The literature proposes several multilevel converter architectures
Ref. [69], and is shown in Fig. 15. The ETOs typically have a higher
capable of blocking DC side fault currents [100,109,110]. Fig. 19 shows
voltage and current handling capability, and switching requirements are
an alternate arm multilevel converter to be employed at AC-DC inter­
quite lenient compared to IGBTs. Once the fault is detected, soft shut
face. During a fault, all the IGBTs are blocked off, cutting off the fault
down technique is used, and ETO gate voltage is reduced dynamically to
current through the converter.
limit the fault current [69,98,99]. For permanent faults gate voltage is
With the fault current blocking converter action, the faulty segment
reduced until the device is completely turned off.
of the network can be isolated without breaking large currents. Hence,
the strategic positioning of fast-acting DC breakers operating in coor­
5.3.2. Back-to-back voltage source converters
dination with fault current blocking converters can facilitate quick fault
Back-to-back VSCs configuration (see Fig. 16) provides full voltage
isolation, minimize damages to the network components and minimize
interruptions. Protection scheme based on coordinated control between
power supply converters and contactors for faster extinction of fault
current and to minimize outage time is presented in Ref. [111].

5.4. Fault current limiters (FCLs)

Limiting the fault level can protect DCMG components against high
fault currents. Fault current limiter (FCL) can be used in DC networks to
limit fault currents as soon as a fault is detected [112]. FCL has an
effective impedance of zero at normal operation, but increases upon
detection of a fault in order to limit the fault current. Strategic posi­
tioning of FCLs is analyzed in Refs. [112,113], which shows the point of
integration of DG source to the network is the best position to place the
FCL.
The possibility of installing protective inductors at the converter
terminals to limit fault current transients in an HVDC network is
investigated in Ref. [114]. However, the requirement of a large size iron
Fig. 15. Modified ETO based VSC architecture, replacing freewheeling di­ core, which consequently increases the size, weight and cost of instal­
odes [69]. lation, is the main disadvantage of this scheme. In addition, this FCL is

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Fig. 16. Modified back-to-back VSC architecture, employing two active VSCs [100].

Fig. 17. Dual active bridge converter architecture with fault current blocking capability [20].

Fig. 18. Modular multilevel dual active bridge converter architecture with fault current blocking capability [100].

only capable of limiting rising currents which makes it effective only additional cooling system.
during transient stages. Several solid-state FCL designs for DC networks have been discussed
Use of FCLs based on superconducting materials in DC networks is in Refs. [118,119]. Solid-state FCL has its advantages, such as small size,
studied in Ref. [115]. The FCL operates in the superconducting mode fully controllable and fast response times. The main drawback of
under normal conditions, and loses its zero resistance if the current solid-state FCL is having high conducting losses.
density reaches a critical value. Design criteria and parameter selection Solid-state FCL topology which consists of SCR and IGBT assembly is
in superconducting FCLs, based on power networks requirements are shown in Fig. 20. Under normal operation, FCL is operating in the
analyzed in Ref. [115]. Practical realizations of superconducting FCLs conducting state. i.e T1 is turned ON and T2 is turned OFF. Load power is
are discussed in Refs. [116,117]. The main disadvantage of this type of supplied through T1. Since SCR T1 is a semi controlled device, has a low
FCL is the requirement of long lengths of superconducting materials, conducting loss compared to IGBTs. Capacitors C0 and C1 are also
which makes FCL large, heavy and expensive. In addition, it requires an charged until C0 and C1 equals DC bus voltage. Load current flow

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D.K.J.S. Jayamaha et al. Renewable and Sustainable Energy Reviews 120 (2020) 109631

Fig. 19. Alternate arm multilevel converter architecture with fault current blocking capability [100].

Fig. 20. Current flow path though FCL during (a) normal operation of the DCMG, (b) after a fault is detected in the DCMG [118].

through FCL under normal operating conditions is shown in Fig. 20 (a). the arc that occurs during current breaking. Protection of DC networks is
When a fault is detected, T1 is turned OFF and T2 is triggered. Compo­ done with specially constructed DC circuit breakers (DCCBs) as well as
nents R1, C1 and T3 act as an input buffer to absorb energy to prevent T2 with oversized ACCBs.
being exposed to overvoltages during triggering. C0, D0, R3, and D3 form Use of ACCBs in series with a reactor in DC networks is discussed in
a forced turnoff circuit. During turnoff of T1, C0 applies an inverse Ref. [120]. However, ACCBs cannot meet strict time limits for fault
voltage to the T1 for forced turnoff. After T1 is turned off, the FCL be­ current interruption in DC networks due to their mechanical restrictions.
comes a buck converter and current through T2 (see Fig. 20 (b)) can be Even though AC devices have advantages such as low cost, DCCBs are
controlled [118]. always the better option to be used in DC networks, as they have fast
constant current interruption capability [37]. Several mechanical,
5.5. Fault current blocking with DC side CBs solid-state and hybrid (solid-state and mechanical) breaker designs for
DC network protection have been developed over the past few years.
DC network fault interrupting schemes employing DC side CBs have
been proposed in Refs. [37,40,120,121]. These schemes offer selectivity 5.5.1. Mechanical DC breakers
in interrupting faulted section of the network, thereby allowing healthy Resonance based principle is generally applied in mechanical DC
sections of the network to operate normally. breakers where oscillator circuits are used to generate a current zero-
With the absence of a zero-crossing in the current waveform, DC crossing point. The general circuitry of a mechanical DCCB with both
switchgear faces a unique challenge of no natural method for quenching passive and active commutation are shown in Fig. 21 [14,122,123]. It

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D.K.J.S. Jayamaha et al. Renewable and Sustainable Energy Reviews 120 (2020) 109631

required increases response time and cost. To address these issues, Z

source circuit breaker (ZSCB) which autonomously responds to faults
(see Fig. 23) is proposed in Ref. [14]. ZSCB creates a current
zero-crossing by absorbing part of the large transient fault current and
once the zero-crossing is created the silicon control rectifier (SCR) is
naturally switched off. This natural commutation of the solid-state
switch allows the fault to be interrupted, without having to apply
signal to disable gate pulses to SCR. Additionally, passive elements used
in ZSCB limit peak current in solid-state device. Hence, it is not required
to withstand high fault currents.
Fig. 21. Mechanical DC circuit breaker, with (a) passive commutation, (b)
active commutation [20]. Inability to provide overload protection and being able to interrupt
faults with high fault transients only are some of the inherited draw­
backs of ZSCB design proposed in Ref. [14]. For less severe faults,
generally comprises of a mechanical switch, commutation circuit, and
transient fault current may not be sufficient to naturally commutate.
MOV for absorption and dissipation of energy after the interruption.
New series ZSCB design which adopts a separate force commutation
Once a fault occurs, the mechanical switch opens and arc voltage is
circuitry is proposed in Ref. [125]. In addition, ZSCB circuitry has been
created which commutates the current through the commutation circuit.
modified to achieve bidirectional power flow capability in Ref. [111].
The series arrangement of capacitor and inductor generates an oscil­
Although SSCBs has its advantages, they require additional sensing,
lating current, thus creating zero-crossing points between mechanical
processing, control circuitry. In addition, they require an additional
switch, and the mechanical switch completely interrupts the current
cooling system and have high power loss at semiconductor junctions. In
[20]. However, response time is much slower (~30 ms) than DC link
order to address the issue of power loss, use of SiC and GaN, WBG de­
capacitor discharge speed, and the network is subjected to very high
vices are been investigated [14,20,125,126]. It is expected the perfor­
fault current transient, under severe fault conditions.
mance of SSCBs can be significantly improved by using WBG devices,
once they become available and economically feasible.
5.5.2. Solid-state circuit breakers (SSCBs)
SSCBs offer a promising solution for DC fault interruption with its
5.5.3. Hybrid CBs (HCBs)
high speed fault current interruption and high fault current handling
An alternative to the lack of steady-state efficiency of SSCB is Hybrid
capability. There are several SSCB designs available based on GTO
CBs (HCBs). As depicted in Fig. 24 HCB is a combination of SSCB, and
thyristors, ETO thyristors, IGBTs and IGCTs [20,40]. A detailed survey
bypass branch consisting of commutating switches (CSs) in series with
into the solid-state technology for the SSCBs considering the switching
FMS. During the normal operation, current flows through the bypass
frequency and voltage/power level the SSCBs are being used for, is
branch only [127–132]. To interrupt fault current, CSs are turned OFF to
provided in Ref. [20].
commutate all the current through SSCB branch, allowing FMS to be
An improved bidirectional SSCB design is shown in Fig. 22. The
opened at zero current. Then the current is blocked by the SCCB as­
breaker comprises of series string of solid-state switches to safely handle
sembly. Since low voltage CSs are adequate to commutate current, low
the DC voltage and it is not possible for transients to exceed the with­
conduction losses are achieved. Possible transient interrupt voltage is
stand levels of the individual components. IGBTs are often the common
prevented by MOVs, which also absorb stored inductive energy in the
choice because of their commercial availability, low power requirement
line. Several practical realizations of this concept are presented in Refs.
to drive the gate and short response time. However, for high power
[128–131].
applications, IGCTs are preferred due to their low conduction losses
For use in HCBs, IGBTs and IGCTs are particularly more suitable due
[40].
to its quick response times and availability for high voltage and current
SSCB design shown in Fig. 22, provides the functionality of complete
applications [43]. Due to the short ON state, solid-state devices do not
CB assembly, where local fault protection is provided through control
require any additional cooling, allowing HCBs to be built compactly.
system of the breaker itself, and external fault detection is not required.
Although HCBs offer advantages of both mechanical and solid-state
Current sensors feed current measurements to the control unit. In case of
breaker technologies combined, due to mechanical restrictions, HCBs
a fault in the network, the control unit activates the gate drive circuit
have limited response speeds compared to SSCBs [43,132].
and turns off active switches. Snubber elements and freewheeling diodes
From the above discussion, it is clear, there has been significant
absorb the residual energy at the time of current interruption [14,40,
progress made in the DC fault interruption technology. It is however,
124].
acknowledged that technical and economic issues associated with these
In SSCB design discussed above, solid-state switches must be actively
driven to reverse bias before fault current exceeds the interrupt capa­
bility of the switch. Hence, timely fault detection is a crucial require­
ment. In addition, fault detection, processing, and control system

Fig. 22. Bidirectional solid-state circuit breaker, general circuitry [40]. Fig. 23. Z source circuit breaker, general circuitry [14].

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D.K.J.S. Jayamaha et al. Renewable and Sustainable Energy Reviews 120 (2020) 109631

Moreover, the protection techniques adopted in ACMGs, HVDC and

MVDC networks were compared, and it is fair to mention protections
aspects of DCMGs are still less explored in research. In conclusion, this
study shows that fault detection, localization and interruption schemes
for DCMGs require further improvements, especially in terms of speed,
accuracy and cost effectiveness.
The following are the specific conclusions and recommendations of
this study:

� Fault features of a DCMG were analyzed using a notional DCMG

model, employing conventional converters. Limitation of DC fault
current utilizing the fast clearance action of fault current blocking
converters significantly improve the post-fault behavior of the DC
network. However, the use of fault current blocking converters for
fault current interruption in DC distribution networks is an under
researched topic that requires further investigation.
� Careful selection of grounding configuration enables the safety of
Fig. 24. Hybrid circuit breaker, general circuitry [129]. personnel and equipment, facilitate reliable fault detection and fault
ride-through capability.
schemes require further investigation. � Fast capacitor discharge and the current rise in DC systems impose
To summarize the above discussion, a comparison of the perfor­ strict time limits for fault detection and interruption; in this respect,
mance of DC fault interruption schemes, and their operational features it is important to consider the speed of fault detection, communica­
are provided in Table 3. tion delays and response time of protective switchgear.
� The absence of frequency and phasor information makes fault
6. Conclusions and future trends detection and localization challenging, compared to its AC counter­
part. Conventional protection schemes such as overcurrent, differ­
This paper analyzed the fault characteristics of DCMGs and explored ential and distance protection require modifications to suit DCMG
the current status of protection devices and challenges associated. fault characteristics. Advanced machine learning and signal

Table 3
Performance and operational features of DC Fault interruption schemes.
Interruption scheme Operating principle High speed Response On state losses selectivity Remarks
fault detection time
required?

Fault current blocking with AC side � ACCBs operate cutting off fault No ~30 Negligible No � Low cost
CBs current from utility grid. ms–100 (<0.1%)
ms
Converters with current blocking � Utilizes the current blocking and No <10 μs Very high (depend No � Very High cost.
and limiting capability limiting capability of solid-state on the converter � Uses self-protection
switches. architecture) schemes, external trig­
gering not required.
Fault current Protective � Limiting fault current transients to No – – No � Only effective in the
limiters inductors at the mitigate fast rising fault current transient stage of the
converter fault.
terminals
Semi- conductor � Operates in superconducting mode No <2 ms Low (<0.1%) No � Unable to completely
FCL under normal operation, non- interrupt fault current,
superconducting mode under fault hence require series
current conditions. connected switches.
Solid-state FCL � Utilizes current limiting Yes <100 μs High (~0.1–2%) No � Lower power loss,
capabilities of solid-state switches. compared to converters
with FCL capability.
Fault current Mechanical DCCB � Creating a zero-crossing point by No ~40 ms Negligible Yes � Provides galvanic
blocking an oscillating circuit, to open the (<0.1%) isolation.
with DC side mechanical switch at zero current. � Low cost.
CBs.

SSCB � Utilizes the current blocking Yes <100 μs High (~0.1–2%) Yes � Bulky cooling system
capability of solid-state devices. required.
� High cost.
� No galvanic isolation
capability.
ZSCB � Creating a zero-crossing point by No <100 μs High (~0.1–2%) Yes � Bulky cooling required.
absorbing part of transient energy � High cost.
to naturally commutate SCR. � No galvanic isolation
capability.
HCB � Creating a zero-crossing point by Yes 500μs-2ms Low (<0.1%) Yes � Very high cost.
parallel solid-state devices to open � Relatively small size.
fast acting switches at zero � No galvanic isolation
current. capability.

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D.K.J.S. Jayamaha et al. Renewable and Sustainable Energy Reviews 120 (2020) 109631

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