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Lecture 34

The document discusses field effect transistors and MOSFET circuits. It describes how to build an inverter using an n-type MOSFET with a resistive load. It also discusses complementary MOSFET (CMOS) inverters using both n-type and p-type MOSFETs. Additionally, it covers biasing enhancement MOSFETs using voltage divider and feedback biasing schemes. Finally, it provides examples of tutorial problems calculating MOSFET voltages, currents, and regions of operation based on given transistor parameters and circuit configurations.

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Saumitra Pandey
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27 views

Lecture 34

The document discusses field effect transistors and MOSFET circuits. It describes how to build an inverter using an n-type MOSFET with a resistive load. It also discusses complementary MOSFET (CMOS) inverters using both n-type and p-type MOSFETs. Additionally, it covers biasing enhancement MOSFETs using voltage divider and feedback biasing schemes. Finally, it provides examples of tutorial problems calculating MOSFET voltages, currents, and regions of operation based on given transistor parameters and circuit configurations.

Uploaded by

Saumitra Pandey
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Electrical Sciences (EEE F111)

Lecture No – 34

Field Effect Transistor

Dr. Manish Gupta


Department of Electrical and Electronics Engineering
BITS-Pilani, K K Birla Goa Campus
Ideal Inverter (NOT Gate)

• Vth is called the threshold voltage of the inverter

BITS Pilani, K K Birla Goa Campus


Resistive Load Inverter

• The digital inverter can be designed using n-type enhancement


MOSFET

• The inverter circuit can be realized by


connecting a load resistor to the drain
terminal

• Assume that the threshold voltage of the


n-type transistor is Vt = 2 V.

• Example of Practical Inverter Circuit

BITS Pilani, K K Birla Goa Campus


Resistive Load Inverter

BITS Pilani, K K Birla Goa Campus


Resistive Load Inverter
Transfer Characteristics

BITS Pilani, K K Birla Goa Campus


Complementary MOSFETs (CMOS)

• If two enhancement MOSFETs, one n-MOSFET and one p-


MOSFET, have identical characteristics (differing only by a minus
sign), they posses complementary symmetry.

• The resulting devices are known as CMOS devices or CMOS


technology. Example: Inverter circuit realized from CMOS
technology

M1: p-type MOSFET

M2: n-type MOSFET

Transfer Characteristics
BITS Pilani, K K Birla Goa Campus
Biasing Enhancement MOSFETs
• As we have biasing circuit is BJTs to obtain the stabilize
operation, the similar way MOSFET can also be biased

• As the BJTs have three biasing schemes

• Fixed Bias

• Self Bias

• Voltage Divider Bias

• The enhancement type MOSFET can be biased with any of the


three previously described biasing scheme

• The most stable biasing scheme is voltage divider biasing


BITS Pilani, K K Birla Goa Campus
Biasing Enhancement MOSFETs
Voltage Divider Biasing:

Since the input current or gate current (IG) ~ 0 in


MOSFET. Thus, VG or VGG is given by

Step 1: Find VGS by applying KVL in the


input loop

BITS Pilani, K K Birla Goa Campus


Biasing Enhancement MOSFETs
Step 2: Find VDS by applying KVL in the output loop

Step 3: Intersection of the load line and transfer characteristics of


MOSFET gives the operating point (Q-point) i.e. IDQ and VGSQ

BITS Pilani, K K Birla Goa Campus


Biasing Enhancement MOSFETs
Feedback Biasing:

The input current or gate current (IG) ~ 0 in MOSFET.

DC equivalent circuit
BITS Pilani, K K Birla Goa Campus
Biasing Enhancement MOSFETs
Apply KVL by considering the gate to source voltage drop

VDD - VRD - VRF - VGS = 0

Since gate current = 0, VRF = 0

VDD - VRD - VGS = 0 (1)

Apply KVL by considering the drain to source voltage drop

VDD - VRD – VDS = 0 (2)


Using 1 and 2
VDS = VGS

Feedback biasing circuit always operates in the active region


BITS Pilani, K K Birla Goa Campus
Biasing Enhancement MOSFETs

For the n-type transistor to be in active region

VGS ≥ VT and VDS > VGS - VT

Since the VGS is derived from the VD, the circuit always operates in the
saturation condition

Feedback biasing circuit always operates in the active region

BITS Pilani, K K Birla Goa Campus


Tutorial Problem 1
A certain enhancement MOSFET has a 𝐾 = 0.25 𝑚𝐴Τ𝑉 2 and 𝑉𝑇𝑛 =
2 𝑉. For small values of 𝑉𝐷𝑆 , estimate the approximate source-drain
resistance when 𝑉𝐺𝑆 = 4, 6 𝑎𝑛𝑑 10 𝑉.

BITS Pilani, K K Birla Goa Campus


Tutorial Problem 2
For the circuit given in the figure, 𝐾 = 0.25 𝑚𝐴Τ𝑉 2 and 𝑉𝑇𝑛 = 2 𝑉.
Given that 𝑅𝐷 = 1𝑘Ω and 𝑅𝑆 = 0, 𝑉𝐷𝐷 = 16 𝑉 and 𝑉𝐺𝐺 = 4 𝑉, find
the transistor terminal currents and voltages and the transistor region
of operation.

BITS Pilani, K K Birla Goa Campus


Tutorial Problem 3
Design the circuit so that the transistor operates in active region at
𝐼𝐷 = 0.4𝑚𝐴 and 𝑉𝐷 = +0.5 𝑉. The NMOS transistor has 𝑉𝑇𝑛 = 0.7𝑉
and 𝐾𝑛 = 3.2 𝑚𝐴Τ𝑉 2 .

BITS Pilani, K K Birla Goa Campus


Tutorial Problem 4
Find the value of RD that results in VD=0.7V. The MOSFET parameters
are given by 𝑉𝑇𝑛 = 0.5𝑉 and 𝐾𝑛 = 1.6 𝑚𝐴Τ𝑉 2 .

BITS Pilani, K K Birla Goa Campus


Tutorial Problem 5

The PMOS transistor has a 𝑉𝑇𝑝 = −1𝑉 and 𝐾𝑝 = 0.6 𝑚𝐴Τ𝑉 2


a) Find the range of VG for which the transistor conducts.
b) In terms of VG, find the range of VD for which the transistor operates in the triode
region.
c) In terms of VG, find the range of VD for which the transistor operates in saturation
d) Find the values of VG and VD to operate the transistor in saturation with 𝐼𝐷 = 75𝜇𝐴

BITS Pilani, K K Birla Goa Campus


Thanks

BITS Pilani, K K Birla Goa Campus

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