Singapore Polytechnic Digital Electronics

Introduction to the Bistable multivibrator

Objective: To familiarize with the characteristics and application of: Gated S-C
Latch, D-Latch and JK-flip-flop.
Equipment Logic probe required:
Digital trainer
Notebook installed with NI Multisim
ICs required: 74LS00 - NAND gate
74LS04 - NOT gate
74LS112 - JK edge-triggered flip-flop

Experiment 4A Gated S-C Bistable circuit

Objective : To investigate the operation of a gated S-C Bistable circuit

Start NI Multisim from your Notebook and then capture the circuit
as shown in figure 5.1. In addition to the four 2-input NAND gates,
three DPST switches, Vcc and DGnd, two probes will be required for
the outputs. Name all your input and output signals according to
figure 5.1. Simulate the circuit using the input combinations as
specified in truth table 5.1.

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Experiment 4

1. To start a new circuit, launch the NI Multisim Simulation software from Start »
Programs » National Instruments » Circuit Design Suite 10.0 » and then
select Multisim.

„ Proceed to capture the circuit shown in figure 5.1. Place the required
components in the drawing page as shown in figure 5.1a. For the required NAND
gates, you may use actual IC devices instead of generic gates by accessing the
TTL/74LS library. Select 74LS00N for the NAND gates and one IC would
suffice. Complete the schematic capture according to figure 5.1 and simulate
your circuit by toggling the switches in accordance with the combinational
sequence shown in the truth table of Table 5.1. Record the status of the probes
in the output columns of the table.

Figure 5.1a

2. Using the digital trainer, connect up your circuit as shown in figure 5.1 with the S,
C and Clock inputs going to the toggle switches on your trainer. Verify that the
results are similar to what you obtained through simulation by varying the inputs
C, S and Enable in the same sequence shown.
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Enable S C Q NOT Q

1 1 0 1 0 1

2 1 1 0 1 0

3 1 0 0 1 0

4 1 1 1 1 1

5 1 0 1 0 1

6 0 0 1 0 1

7 0 0 0 0 1

8 0 1 1 0 1

9 0 1 0 0 1

10 1 1 0 1 0

11 0 1 0 1 0

12 0 0 1 11 0

Table5.1 Gated S-C Latch using NAND gates

Experiment 4

3. Interpret your results recorded in table 5.1 and hence, complete the table 5.1.2.

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Singapore Polytechnic Digital Electronics

Enable S C Q Not Q

1 0 0 1 0

1 0 1 0 1

1 1 0 1 0

1 1 1 1 1

1 0 1 0 1

0 1 0 1 0

0 1 1 0 1
Table 5.1.2

If S = 1 and C = 0 and the enable is 0 or low - Q = __1_

If S = 0 and C = 1 and the enable is 1 or high - Q = __0_

If S = 1 and C = 0 and the enable is 1 or high - Q = __1_

If S = 1 and C = 1 and the enable is 1 or high - Q = __1_

Write in your own words the conclusions you can draw from this experiment.

Experiment 4B D-type Bistable Circuit

Objective: To understand the operation of the D-type Bistable circuit

Experiment 4 page 4
Singapore Polytechnic Digital Electronics

Using your Notebook, activate NI Multisim and capture the circuit

as shown in figure 5.2. In addition to the required gates, three
switches, Vcc, DGnd, and two probes will be required. Name all
your input and output signals as according to figure 5.2. Using the
mouse, simulate the circuit and complete the truth table 5.2.

2. Construct the circuit which you have simulated on the logic trainer using the
appropriate ICs. Connect the D and Enable inputs to the toggle switches on your
trainer and the Q and Not Q outputs to LEDs. Hence verify that the results you
obtained from circuit simulation by going through the sequence listed in truth
table 5.2.

NB: If you have problems connecting your circuit, Login to blackboard on the Lab PC
and go to the Lab Folder of the Course Documents Menu and Launch the Guide
for Experiment 4.

Experiment 4

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Enable D Qn+1 *

0 0

0 1

1 0

1 1
Table 5.2 D-type Bistable truth table

* Qn+1 refer to the new value of output Q after the application of the input control
signals. Use the notation Qn to denote the previous value of Q, i.e. the value of
Q prior to the application of the new input states.

Is the D-type Bistable circuit in figure 5 .2 level triggered or edge

triggered?

Write in your own words the conclusions you can draw from this
experiment.

Experiment 4 page 6
Singapore Polytechnic Digital Electronics

Experiment 4C J-K Edge triggered flip-flop

Objective: To understand the Synchronous operation of a J-K flip-flop using the

74LS112 IC.

Using your Notebook, activate NI Multisim and capture the circuit of

74LS112 JK flip-flop as shown in figure 5.3, the symbol of which
can be found in either the TTL  74LS library. In addition to the
flip-flop, three SPDT switches, Vcc, DGnd and two probes will be
required.

Fig. 5.3

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Singapore Polytechnic Digital Electronics

„ Before simulation can start, the Preset (Set) and Clear (Reset) must be
connected to logic 1. As you toggle the switches connected to the Clock and
JK inputs, complete the truth table listed in Table 5.3.

J K Clock Q Not Q

0 0 0

0 0 1

0 0 0

0 1 1

0 1 0

1 0 1

1 0 0

1 1 1

1 1 0
Table 5.3 J-K type flip-flop truth table

2. Optional: On the trainer, connect up the J-K flip-flop circuit using either half
of the 74LS112 with the J and K inputs going to the toggle switches and the
clock input connected to any of the two push-button switches, which are
debounced. The Preset and Clear inputs need to be connected to logic 1 or to
switches set to logic 1. Verify that the JK flip-flop has a truth table as
summarized in Table 5.3.

„ Note: As you proceed down the truth table, set up the J K value first then change the
clock logic level. Also bear in mind that with the push button switch, the
'resting' output logic state is either a 0 or a 1 depending on which output
connector (A or Not A) is used. Refer to experiment 1 and the waveforms

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Singapore Polytechnic Digital Electronics

you've drawn to review on the operation of the push button switches if you are
unsure.

3. Using the results from your previous experiments, complete the JK flip-flop
truth table 5.3.2 for the 74LS112. Under the clock column either put a ↑ or ↓
to indicate the correct trigger (i.e. PGT or NGT) required for the clock signal.

J K Clock Q NOT Q Remarks

0 0 ↑ or ↓
0 1

1 0

1 1

Table 5.3.2 JK-type flip-flop truth table

Is the JK-type flip-flop level triggered or edge triggered?

Write in your own words the conclusions you can draw from this
experiment.

Experiment 4 page 9