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LABS

The document provides instructions for a lab assignment on implementing basic building blocks in Verilog. Students are asked to develop a 8-bit bidirectional shift register module and represent it as a block diagram. Subsequent labs focus on binary multiplication using Booth encoding, implementing an 8-bit adder using a ripple carry approach with pipelining, and testing logic gates and implementing Verilog designs on an FPGA.

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Umar Siddique
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12 views9 pages

LABS

The document provides instructions for a lab assignment on implementing basic building blocks in Verilog. Students are asked to develop a 8-bit bidirectional shift register module and represent it as a block diagram. Subsequent labs focus on binary multiplication using Booth encoding, implementing an 8-bit adder using a ripple carry approach with pipelining, and testing logic gates and implementing Verilog designs on an FPGA.

Uploaded by

Umar Siddique
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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The Islamia University of Bahawalpur

Faculty of Engineering

Department of Computer Systems Engineering

LAB No.7

Name: Instructor

Roll No. Date

Objective: Implement architectures of basic building blocks in Verilog.

o Develop the Verilog module for an 8-bit bi-directional synchronous shift


register .
 Represent the design in the form of block diagram.
Consider the following 8-bit bi-directional synchronous shift register with parallel load capability. The
notation used to represent the input/output pins is explained below.
CLR Asynchronous Clear, overrides all other inputs
Q(7:0) 8-bit output
D(7:0) 8-bit input
S0, S1 mode control inputs
LSI serial input for left shift
RSI serial input for right shift
The mode control inputs work as follows:
Pre Lab:

Design Diagram:

Your Code here:

Lab Task:
The Islamia University of Bahawalpur

Faculty of Engineering

Department of Computer Systems Engineering

LAB No.8

Name: Instructor

Roll No. Date

Objective:
a) Implementation of 4x4 binary signed multiplication on Verilog.
b) Implementation of Booth Algorithm in Verilog

Introduction:
DESIGN A BOOTH RECODER BY USING A COMPRESSION TREE AND
FOUR MULTIPLEXERS FOR THE FOLLOWING CASES OF MULTIPLIERS:
+1, -1, +2 and -2

LAB TASK1:
LAB TASK 2.

Draw a block diagram of the system for n = 8. Use 9-bit registers for A and B, a 9-
bit full adder, an 8-bit complementer, a 3-bit counter, and a control circuit. Use the
counter to count the number of shifts.
The Islamia University of Bahawalpur

Faculty of Engineering

Department of Computer Systems Engineering

LAB No.9

Name: Instructor

Roll No. Date

Objective:
Introduction to Field Programmable Gate Array (FPGA)
Understanding the hardware of FPGA

Introduction to FPGA:

What is FPGA:

FPGA Architecture:

CPLD VS FPGA

SoC FPGAs

FPGA DESIGN:

FPGA APPLICATIONS

LAB TASK:
1. TEST THE OPERATION OF ALL LOGIC GATES ON FPGA
2. Write down all the steps involved in implementation of Verilog on FPGA
The Islamia University of Bahawalpur

Faculty of Engineering

Department of Computer Systems Engineering

LAB No.10

Name: Instructor

Roll No. Date

Objective:
Designing optimized DFG by applying various pipelining and retiming techniques

Pipelining and Retiming:


LAB TASK:
1.

2.
Design a 12 bit ripple carry adder , apply three stage pipelining in your design.
Write the Verilog code of design.

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