Chapter 4

Power Supply, Processors

and Programming Device

1
Introduction to Programmable Logic Controllers Chapter 4

4.1 Introduction

• The typical CPU consists of three components: Processor, memory and power supply.
• The power supply may be a separate unit that is mounted next to the block
enclosure containing the processor and memory.

• The programming device is not

regarded as a part of CPU.
• The programming device communicates
the CPU to load/upload the program.

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4.1 Introduction

PLC Mitsubishi FX series PLC Mitsubishi Q series

with built-in power supply with modular power supply

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4.1 Introduction

• The functional interaction between a

PLC’s basic components can be
described as this figure.
• The processor executes the control
program stored in the memory
system.
• The system power supply provides all
of the necessary voltage levels to the Input Module Output Module
processor and memory components.

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4.2 Processors
• The principal function of the processor is to command and govern the activities of
the entire system.
• It performs this function by interpreting and executing a collection of system
programs known as the executive.
• The processor can perform all of its control, processing, communication, and other
housekeeping functions.
• The CPU of a PLC system may contain more than one processor to execute the
system’s duties and/or communications.

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4.2 Processors
• The approach of using several microprocessors
to divide control and communication tasks is
known as multiprocessing.

Main CPU Motion CPU Intelligent module

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4.2 Processors

PLC Mitsubishi FX series

FX5U – 32M
Output type: Transistor
External source:
100 – 240VAC
Input: 16
Output: 16

AC servo motor
control
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4.3 Processor Scan

• The basic function of a programmable controller is implemented as follows:

▪ Read the state of all field input devices.
▪ Execute the control program which according to logic programmed, will turn the
internal output coils ON or OFF.
▪ The energizing or deenergizing of these internal outputs will turn the field output
devices ON or OFF.
• The process of reading the inputs, executing the program, and updating the outputs
is known as the scan.

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4.3 Processor Scan

(End-Of-Scan)

• The time it takes to implement a scan is called the scan time.

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4.3 Processor Scan

• The scan time is the total time the PLC takes to complete the program and I/O
update scans.
• The program scan time generally depends on two factors: (1) the amount of
memory taken by the control program and (2) the type of instructions used in the
program.
• PLC manufacturers specify the scan time based only on the amount of application
memory used (e.g. 1 msec/1K of programmed memory).
• The use of remote I/O subsystems can increase the scan time, since the PLC
must transmit and receive the I/O update from remote systems.

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4.3 Processor Scan

• Monitoring control programs also adds time to the scan, because the
microprocessor must send data about the status of the coils and contacts to a
monitoring device. (e.g. HMI, PC, SCADA program).
• A processor is able to read an input as long as the input signal is not faster than
the scan time.
For instance, if a controller has a total scan time of 10 msec and must monitor
an input signal that changes states twice during an 8 msec period (less than a
scan), the programmable controller will not be able to “see” the signal.

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4.3 Processor Scan Update

Read 10 msec outputs
inputs Program Execution

• Input signal 1 changes states

Previous
greater than the scan.
Scan EOS EOS
signal signal • Input signal 2 changes states

Input
1 twice less than the scan.
signal 1
0 • Input signal 3 changes states
1
Input fourice less than the scan.
signal 2
0

Input 1
signal 3
0
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4.3 Processor Scan

• Some PLCs provide software instructions that
allow the interruption of the continuous
program scan to receive an input or to
update an output immediately.

• These immediate instructions are very useful

when the PLC must react instantaneously to
a critical input or output.
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4.3 Processor Scan

• Another method for reading extremely fast inputs involves using a pulse stretcher, or
fast-response module.
One Scan One Scan
Read Update

1
Pulse
signal
50 𝜇sec
0
1
Stretched
signal
0

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4.3 Processor Scan

• This module stretches the signal so that it will last for at least one complete scan.
• The user must ensure that the signal does not occur more than once per two scans;
otherwise, some pulses will be lost.
• If a large number of pulses must be read in a shorter time than the scan time, a
high-speed pulse counter input module can be used to read all the pulses and then
send the information to the CPU.

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4.3 Processor Scan

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4.3 Processor Scan

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4.4 Error Checking and Diagnostics

• The PLC’s processor constantly communicates with local and remote subsystems.
• I/O interfaces connect these subsystems to field devices located either close to the
main CPU or at remote locations.
• Subsystem communication involves data transfer exchange at the end of each
program scan.
• The processor sends the latest status of outputs to the I/O subsystem and receives
the current status of inputs and outputs.
• The processor uses error-checking techniques to monitor the functional status of both
the memory and the communication links between subsystems and peripherals.

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4.4 Error Checking and Diagnostics

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4.4 Error Checking and Diagnostics

Error Checking: Common error-checking techniques include parity and checksum.
Parity
• Parity is the most common error detection technique.
• Parity check is often called Vertical Redundancy Check (VRC).
• There are two types of parity checks: even parity and odd parity.
• Even parity checks for an even number of 1s in the data transmission, whereas
odd parity checks for an odd number of 1s.
• An extra bit called Parity bit (P) is appended to the binary word, generally in the
most significant bit, which is used to make each byte or word have an odd or
even number of 1s.
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4.4 Error Checking and Diagnostics

Error Checking >> Parity
Consider these words
1011 0110 1000 1010 - This word has an even number of 1s (8)
1011 0110 1000 1000 - This word has an odd number of 1s (7)
For example: A processor transmits the 7-bit ASCII character C (binary value as
1000011) to a peripheral device. A parity bit is added to the MSB of this byte to
form:
P1000011 - This byte has three of 1s, as an odd number.
If the odd parity is required, P is set to 0 to obtain an odd number of 1s.
Otherwise, the even parity is required, P is set to 1 to obtain an even number of 1s.
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4.4 Error Checking and Diagnostics

Error Checking >> Parity
• If one bit of data in a word changes, an error will be detected.
• It two bits change value, the number of 1s will be changed back, and an error will
not be detected.
• In PLCs, when data is transmitted to a subsystem, the controller defines the type
of parity (odd or even) that will be used.
• However, if the data transmission is from the programmable controller to a
peripheral, the parity method must be prespecified and must be the same for
both devices.

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4.4 Error Checking and Diagnostics

Error Checking >> Checksum
• Checksum error detection spots errors in blocks of many words, instead of in
individual words as parity does.
• Checksum analyzes all of the words in a data block and then adds to the end of
the block one word known as the Block Check Character (BCC).
• There are several methods of checksum computation, with the three most
common being:
▪ Cyclic Redundancy Check (CRC)
▪ Longitudinal Redundancy Check (LRC)
▪ Cyclic Exclusive-OR Checksum (CX–ORC)
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4.4 Error Checking and Diagnostics

Error Checking >> Checksum >> Cyclic Redundancy Check (CRC)
• It performs an addition of all the words in the data block.
Word 1
• Then stores the resulting sum in the last location (BCC).
Word 2
Checksum = Word1 + Word2 + Word3 + … + Last word
Word 3
• One variation of CRC allows the sum to overflow: .
.
At the sender side: .

Resulting sum = Word1 + Word2 + Word3 + … + Last word Last word

Checksum = Complement of resulting sum Checksum

At the receiver side:

Check the complement of “Word1 + Word2 + … + Last word + Checksum” is 0.
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4.4 Error Checking and Diagnostics

Error Checking >> Checksum >> Cyclic Redundancy Check (CRC)
Ex: Implement a checksum utilizing CRC technique for four 6-bit words

1 2 3 4
Word
110011 101101 101110 100111
At the sender side:
• The sum of all segments is obtained as
110011+101101+101110+100111=10110101
• 1’s complement is taken which is 0 1 0 0 1 0 1 0
• CRC checksum value 0 1 0 0 1 0 1 0

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4.4 Error Checking and Diagnostics

Error Checking >> Checksum >> Cyclic Redundancy Check (CRC)
Ex: Implement a checksum utilizing CRC technique for four 6-bit words

1 2 3 4
Word
110011 101101 101110 100111
At the receiver side:
• The sum of all segments is obtained as 1 0 1 1 0 1 0 1
• CRC checksum value 0 1 0 0 1 0 1 0
• The overflow sum = Sum of all segments + Checksum = 1 1 1 1 1 1 1 1
• Complemented value of the overflow sum = 0 0 0 0 0 0 0 0
• Receiver assumes no error occurred in the data and therefore accepts it.
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4.4 Error Checking and Diagnostics

Error Checking >> Checksum >> Longitudinal Redundancy Check (LRC)
• It is an error-checking technique based on the accumulation of the result of
performing an exclusive-OR (XOR) on each of the words in the data block.
• The LRC operation is simply the logical exclusive-OR of the first word with the
second word, the result with the third word, and so on.
• The final exclusive-OR operation is stored at the end of the block as the BCC.
Ex: Implement a checksum utilizing LRC technique for four 6-bit words. Place the
BCC at the end of the data block.
1 2 3 4
Word
110011 101101 101110 100111
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4.4 Error Checking and Diagnostics

Error Checking >> Checksum >> Longitudinal Redundancy Check (LRC)
1 2 3 4
Word
110011 101101 101110 100111
011110 101110
110000 100111
010111

LRC data block:

1 2 3 4 BCC
Word
110011 101101 101110 100111 010111

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4.4 Error Checking and Diagnostics

Error Checking >> Checksum >> Cyclic Exclusive-OR Checksum (CX–ORC)
• The operation starts with a checksum word containing 0s, which is XORed with
the first word of the block.
• This is followed by a left rotation of the bits in the checksum word.
• The next word in the data block is XORed with the checksum word and then
rotated left.
• This procedure is repeated until the last word of the block has been logically
operated on.

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4.4 Error Checking and Diagnostics

Error Checking >> Checksum >> Cyclic Exclusive-OR Checksum (CX–ORC)
Ex: Implement a checksum utilizing CX-ORC technique for four 6-bit words. Place
the BCC at the end of the data block.
1 2 3 4
Word
110011 101101 101110 100111

CS Start 000000 Left rotate 1 0 0 1 1 1 Left rotate 0 1 0 1 0 0

Word 1 110011 Word 2 101101 Word 3 101110

Result 110011 Result 001010 Result 111010
Left rotate 1 0 0 1 1 1 Left rotate 0 1 0 1 0 0 Left rotate 1 1 0 1 0 1

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4.4 Error Checking and Diagnostics

Error Checking >> Checksum >> Cyclic Exclusive-OR Checksum (CX–ORC)
Ex: Implement a checksum utilizing CX-ORC technique for four 6-bit words. Place
the BCC at the end of the data block.
1 2 3 4
Word
110011 101101 101110 100111

Left rotate 1 1 0 1 0 1 CX–ORC data block:

1 2 3 4 BCC
Word 4 100111 110011 101101 101110 100111 100100
Result 010010
Left rotate 1 0 0 1 0 0 Final Checksum

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4.4 Error Checking and Diagnostics

CPU Diagnostics

• The processor is responsible for detecting communication failures, as well as other

failures, that may occur during system operation.
• The processor performs diagnostics, or error checks, during its operation and sends
status information to indicators that are normally located on the front of the CPU.
• Typical diagnostics include memory OK, processor OK, battery OK, and power supply
OK.
• CPU diagnostics are available to the user during the execution of the control program.

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4.5 The System Power Supply

• The system power supply plays a major role in the total system operation.
• Its responsibility is not only to provide internal DC voltages to the system
components;
• but also to monitor and regulate the supplied voltages and warn the CPU if something
is wrong.
• Most PLCs, however, require a 120 VAC or 220 VAC power source, while a few
controllers will accept 24 VDC.
• A PLC power supply must be able to tolerate a 10 to 15% variation in line voltage
conditions.

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4.5 The System Power Supply Screw terminal

PLC Mitsubishi FX series GND
FX0s – 10MT – DSS 0V
24V
Output type: Transistor
External source: 24VDC
Input: 6
Output: 4

24VDC

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4.5 The System Power Supply

PLC Mitsubishi FX series Screw terminal

FX1s – 20MR GND

Neutral
Output type: Relay Line
External source: 100 – 240VAC
Input: 12
Output: 8

100-240
VAC L N

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4.5 The System Power Supply

Screw terminal
GND
Neutral
Line

100-240
VAC L N

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4.5 The System Power Supply

Modular Power Supply

N
INPUT
100-120VAC ~
L

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4.6 Programming Devices

• Two basic types of programming devices are:

▪ Miniprogrammers
▪ Personal computers
• Miniprogrammers, also known as handheld or manual programmers, are an
inexpensive and portable way to program small PLCs.
• These devices resemble handheld calculators, but they have a larger display and a
somewhat different keyboard.
• They are used mainly for editing and inputting control programs, miniprogrammers
can also be useful tools for starting up, changing, and monitoring the control logic.

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4.6 Programming Devices

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4.6 Programming Devices

RS-422 MD8M
USB

Ethernet cable Ethernet

Ethernet
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