Freescale Semiconductor Document Number: MC9S08SF4

Data Sheet: Technical Data Rev. 4, 9/2011

MC9S08SF4
MC9S08SF4 Series 20-Pin TSSOP
Case 948E
16-Pin TSSOP
Case 948F

Features • Peripherals
• 8-Bit S08 Central Processor Unit (CPU) – IPC — Prioritize interrupt sources besides inherent
– Up to 40 MHz CPU at 2.7 V to 5.5 V across temperature CPU interrupt table; support up to 32 interrupt sources
range of –40 C to 125 C and up to 4-level preemptive interrupt nesting
– HC08 instruction set with added BGND instruction – ADC — 8-channel, 10-bit resolution; 2.5 s conversion
– Support for up to 32 interrupt/reset sources time; automatic compare function; temperature sensor;
• On-Chip Memory internal bandgap reference channel; operation in stop;
– 4 KB flash read/program/erase over full operating fully functional from 2.7 V to 5.5 V
voltage and temperature – TPM — One 40 MHz 6-channel and one 40 MHz
– 128-byte random-access memory (RAM) 1-channel timer/pulse-width modulators (TPM)
– Security circuitry to prevent unauthorized access to modules; selectable input capture, output compare, or
RAM and flash contents buffered edge- or center-aligned PWM on each channel
• Power-Saving Modes – MTIM16 — Two 16-bit modulo timers
– Two low power stop modes; reduced power wait mode – PWT — Two 16-bit pulse width timers (PWT);
– Allows clocks to remain enabled to specific peripherals selectable driving clock, positive/negative/period
in stop3 mode capture
• Clock Source Options – PRACMP — Two programmable reference analog
– Internal Clock Source (ICS) — Internal clock source comparators with eight optional inputs for both positive
module containing a frequency-locked-loop (FLL) and negative inputs; 32-level internal reference voltages
controlled by an internal or external reference; precision scaled by selectable reference inputs
trimming of internal reference allows 0.2% resolution – IIC — Inter-integrated circuit bus module capable of
and 1% deviation over 0–70 C and voltage, 2% operation up to 100 kbps with maximum bus loading;
deviation over –40–85 C and voltage, or 3% deviation multi-master operation; programmable slave address;
over –40–125 C and voltage; supporting bus interrupt-driven byte-by-byte data transfer; broadcast
frequencies up to 20 MHz mode; 10-bit addressing
• System Protection – KBI — 4-pin keyboard interrupt module with software
– Watchdog computer operating properly (COP) reset selectable polarity on edge or edge/level modes
with option to run from dedicated 1 kHz internal clock – FDS — Shut down output pin upon fault detection; the
source or bus clock fault sources can be optional enabled separately; the
– Low-voltage detection with reset or interrupt; selectable output pin can be configured as output 1,0 and high
trip points impedance when a fault occurs based on module
– Illegal opcode detection with reset configuration
– Illegal address detection with reset • Input/Output
– Flash block protection – 18 GPIOs including one input-only pin and one
• Development Support output-only pin
– Single-wire background debug interface – Hysteresis and configurable pullup device on all input
– Breakpoint capability to allow single breakpoint setting pins; schmitt trigger on PWT input pins; configurable
during in-circuit debugging (plus two more breakpoints) slew rate and drive strength on all output pins.
– On-chip in-circuit emulator (ICE) debug module • Package Options
containing two comparators and nine trigger modes – 16-pin TSSOP
– 20-pin TSSOP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009-2011. All rights reserved.
Table of Contents
1 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.11 PRACMP Characteristics . . . . . . . . . . . . . . . . . .21
2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.12 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .22
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 5 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 5 5.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . .23
3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 5
3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . 6
3.5 ESD Protection and Latch-Up Immunity . . . . . . . 7
3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 8
3.7 Supply Current Characteristics . . . . . . . . . . . . . 14
3.8 ICS Characteristics . . . . . . . . . . . . . . . . . . . . . . 16
3.9 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 17
3.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . 18
3.9.2 Timer/PWM (TPM) Module Timing . . . . . 19
3.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . 20

Revision History
The following revision history table summarizes changes contained in this document.

Revision Date Description of Changes

2 4/30/2009 Initial public release.
3 8/18/2009 Polished.
4 9/19/2011 Updated VAIN in the Table 12.

Related Documentation
Reference Manual (MC9S08SF4RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module information.

MC9S08SF4 Series MCU Data Sheet, Rev. 4

2 Freescale Semiconductor
1 MCU Block Diagram
The block diagram, Figure 1, shows the structure of the MC9S08SF4 MCU.
DEBUG MODULE
(DBG)

INTERRUPT PRIORITY 16-BIT MODULO TIMER TCLK PTA0/KBI0/TCLK/IRQ

CONTROLLER (IPC) (MTIM16-1)
PTA1/KBI1/RESET
16-BIT MODULO TIMER TCLK
PTA2/KBI2/TPM1C0/FDSOUT0
HCS08 CORE (MTIM16-2)

PORT A
PTA3/KBI3/TPM1C1/FDSOUT1
4-PIN KEYBOARD KBI[3:0]
CPU BDC INTERRUPT (KBI) PTA4/TPM1C2/FDSOUT2

TPM1C[5:0] PTA5/TPM1C3/FDSOUT3
6-CH TIMER/PWM
HCS08 SYSTEM CONTROL MODULE (TPM1) TCLK
PTA6/TPM1C4/FDSOUT4
RESETS AND INTERRUPTS RESET
MODES OF OPERATION IRQ PTA7/TPM1C5/FDSOUT5
POWER MANAGEMENT

COP IRQ FAULT DETECTION FDSOUT[6:0]

PTB0/TPM2C0/FDSOUT6
& SHUTDOWN (FDS)
WAKEUP LVD
PTB1/PWTI1/ADC0
1-CH TIMER/PWM TPM2C0
MODULE (TPM2) TCLK
PTB2/PWTI2/ADC1
USER Flash
4096 BYTES PWTI1

PORT B
PULSE WIDTH TIMER PTB3/ACMP3/ADC2
TCLK
(PWT1)
USER RAM PTB4/ACMP2/ADC3
128 BYTES PULSE WIDTH TIMER PWTI2
(PWT2) TCLK PTB5/ACMP1/ADC4
ACMP3
ANALOG COMPARATOR ACMP2 PTB6/ACMP0/ADC5
40 MHz INTERNAL CLOCK (PRACMP1) ACMP1
SOURCE (ICS) ACMP0
PTB7/BKGD/MS
ACMP3
ANALOG COMPARATOR ACMP2
ACMP1
(PRACMP2) ACMP0
VDD
VSS VOLTAGE REGULATOR

8-CH 10-BIT ADP[5:0]

ANALOG-TO-DIGITAL ADP[6:7]
CONVERTER(ADC)
PORT C

PTC0/ADC6/SCL

INTER-INTERGRATED SCL
PTC1/ADC7/SDA
SDA
CIRCUIT (IIC)

= Not available in the 16-pin TSSOP package

Figure 1. MC9S08SF4 Series Block Diagram

2 Pin Assignments
This section shows the pin assignments for the MC9S08SF4 series devices.

MC9S08SF4 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor 3
 VDD 1 20 VSS
PTA0/KBI0/TCLK/IRQ 2 19 PTC1/SDA/ADC7
PTA1/KBI1/RESET 3 18 PTC0/SCL/ADC6
PTA2/KBI2/TPM1C0/FDSOUT0 4 17 PTB7/BKGD/MS
PTA3/KBI3/TPM1C1/FDSOUT1 5 16 PTB6/ACMP0/ADC5
PTA4/TPM1C2/FDSOUT2 6 15 PTB5/ACMP1/ADC4
PTA5/TPM1C3/FDSOUT3 7 14 PTB4/ACMP2/ADC3
PTA6/TPM1C4/FDSOUT4 8 13 PTB3/ACMP3/ADC2
PTA7/TPM1C5/FDSOUT5 9 12 PTB2/PWTI2/ADC1
PTB0/TPM2C0/FDSOUT6 10 11 PTB1/PWTI1/ADC0

Figure 2. MC9S08SF4 in 20-Pin TSSOP Package

VDD 1 16 VSS
PTA0/KBI0/TCLK/IRQ 2 15 PTB7/BKGD/MS
PTA1/KBI1/RESET 3 14 PTB6/ACMP0/ADC5
PTA2/KBI2/TPM1C0/FDSOUT0 4 13 PTB5/ACMP1/ADC4
PTA3/KBI3/TPM1C1/FDSOUT1 5 12 PTB4/ACMP2/ADC3
PTA4/TPM1C2/FDSOUT2 6 11 PTB3/ACMP3/ADC2
PTA5/TPM1C3/FDSOUT3 7 10 PTB2/PWTI2/ADC1
PTB0/TPM2C0/FDSOUT6 8 9 PTB1/PWTI1/ADC0

Figure 3. MC9S08SF4 in 16-Pin TSSOP Package

MC9S08SF4 Series MCU Data Sheet, Rev. 4

4 Freescale Semiconductor
 Introduction

3 Electrical Characteristics
3.1 Introduction
This section contains electrical and timing specifications for the MC9S08SF4 series of microcontrollers
available at the time of publication.

3.2 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 1. Parameter Classifications

P Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically relevant
C
sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices
T under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.

D Those parameters are derived mainly from simulations.

NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.

3.3 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 2 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pullup resistor associated with the pin is enabled.

MC9S08SF4 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor 5
Thermal Characteristics

Table 2. Absolute Maximum Ratings

Rating Symbol Value Unit

Supply voltage VDD –0.3 to 5.8 V

Maximum current into VDD IDD 120 mA
Digital input voltage VIn –0.3 to VDD + 0.3 V
Instantaneous maximum current
ID 25 mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range Tstg –55 to 150 C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins are internally clamped to VSS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in the external power supply going
out of regulation. Ensure external VDD load shunts current greater than the maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).

3.4 Thermal Characteristics

This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the
MCU design. To take PI/O into account in power calculations, determine the difference between actual pin
voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and VSS or VDD will be small.
Table 3. Thermal Characteristics

Rating Symbol Value Unit

Operating temperature range TL to TH

TA C
(packaged) –40 to 125
Thermal resistance (single-layer board)
20-pin TSSOP 115
JA C/W
16-pin TSSOP 123
Thermal resistance (four-layer board)
20-pin TSSOP 76
JA C/W
16-pin TSSOP 75

The average chip-junction temperature (TJ) in C can be obtained from:

TJ = TA + (PD  JA) Eqn. 1

MC9S08SF4 Series MCU Data Sheet, Rev. 4

6 Freescale Semiconductor
 ESD Protection and Latch-Up Immunity

Where:
TA = Ambient temperature, C
JA = Package thermal resistance, junction-to-ambient, C/W
PD = Pint PI/O
Pint = IDD  VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O  Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:

PD = K  (TJ + 273C) Eqn. 2

Solving Equation 1 and Equation 2 for K gives:

K = PD  (TA + 273C) + JA  (PD)2 Eqn. 3

Where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.

3.5 ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
During the device qualification ESD stresses were performed for the human body model (HBM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.

MC9S08SF4 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor 7
DC Characteristics

Table 4. ESD and Latch-up Test Conditions

Model Description Symbol Value Unit

Series resistance R1 1500 

Human
Storage capacitance C 100 pF
Body
Number of pulses per pin — 1
Minimum input voltage limit — –2.5 V
Latch-up
Maximum input voltage limit — 7.5 V

Table 5. ESD and Latch-Up Protection Characteristics

No. Rating1 Symbol Min Max Unit

1 Human body model (HBM) VHBM 2000 — V

2 Charge device model (CDM) VCDM 500 — V

3 Latch-up current at TA = 125 C ILAT 100 — mA

1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.

3.6 DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 6. DC Characteristics (Temperature Range = –40 to 125 C Ambient)

Num C Parameter Symbol Min Typical Max Unit

1 P Supply voltage (run, wait, and stop modes.) VDD 2.7 — 5.5 V
Low-voltage detection threshold — high range
P (VDD falling) 3.9 — 4.1 V
VLVDH
(VDD rising) 4.0 — 4.2 V
2
Low-voltage detection threshold — low range
P (VDD falling) 2.48 2.56 2.64 V
VLVDL
(VDD rising) 2.54 2.62 2.7 V
Low-voltage warning threshold — high range
P (VDD falling) 2.66 — 2.82 V
VLVWH
(VDD rising) 2.72 — 2.88 V
3
Low-voltage warning threshold — low range
P (VDD falling) 2.84 — 3.00 V
VLVWL
(VDD rising) 2.90 — 3.06 V
Low-voltage inhibit reset/recover hysteresis
4 D 5V — 100 — mV
Vhys
3V — 60 — mV
Bandgap voltage reference
5 P
Factory trimmed at VDD = 3.0 V, Temp = 25 C VBG 1.185 1.200 1.215 V
Input high voltage (2.7 V  VDD 5.5 V) (all
6 P VIH 0.65 × VDD — VDD + 0.3 V
digital inputs)

MC9S08SF4 Series MCU Data Sheet, Rev. 4

8 Freescale Semiconductor
 DC Characteristics

Table 6. DC Characteristics (Temperature Range = –40 to 125 C Ambient) (continued)

Num C Parameter Symbol Min Typical Max Unit

Input low voltage (2.7 V  VDD 5.5 V) (all

7 P VIL VSS – 0.3 — 0.35 × VDD V
digital inputs)
8 D Input hysteresis (all digital inputs) Vhys 0.06 × VDD — 0.30 × VDD V
Input Leakage Current (pins in high ohmic
9 P input mode)1 Iin –1 —  A
V =V or V
in DD5 SS5
P Internal pullup resistors2 RPU 17.5 40.0 52.5 k
10
P Internal pulldown resistor (IRQ) RPD 12.5 — 62.5 k
Output high voltage All I/O pins, low-drive
C VDD – 1.5 — — V
strength, 5 V, Iload = –4 mA
Output high voltage All I/O pins, low-drive
P VDD – 0.8 — — V
strength, 5 V, Iload = –2 mA
Output high voltage All I/O pins, low-drive
C VDD – 0.8 — — V
strength, 3 V, Iload = –1 mA
11 V
Output high voltage All I/O pins, high-drive OH
C VDD – 1.5 — — V
strength, 5 V, Iload = –15 mA
Output high voltage All I/O pins, high-drive
P VDD – 0.8 — — V
strength, 5 V, Iload = –10 mA
Output high voltage All I/O pins, high-drive
C VDD – 0.8 — — V
strength, 3 V, Iload = –5 mA
Output low voltage All I/O pins, low-drive
C — — 1.5 V
strength, 5 V, Iload = 4 mA
Output low voltage All I/O pins, low-drive
P — — 0.8 V
strength, 5 V, Iload = 2 mA
Output low voltage All I/O pins, low-drive
C — — 0.8 V
strength, 3 V, Iload = 1 mA
12 V
Output low voltage All I/O pins, high-drive OL
C — — 1.5 V
strength, 5 V, Iload = 15 mA
Output low voltage All I/O pins, high-drive
P — — 0.8 V
strength, 5 V, Iload = 10 mA
Output low voltage All I/O pins, high-drive
C — — 0.8 V
strength, 3 V, Iload = 5 mA
Maximum total IOH for all port pins
D 5V |IOHT| — — 100
mA
3V — — 60
13
Maximum total IOL for all port pins
D 5V |IOLT| — — 100
mA
3V — — 60
dc injection current2, 3, 4, 5
VIN < VSS, VIN > VDD
14 D Single pin limit |IIC|
— — 0.2 mA
Total MCU limit, includes sum of all stressed
— — 5 mA
pins
15 D Input capacitance (all non-supply pins) CIn — — 7 pF

MC9S08SF4 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor 9
DC Characteristics

1
Maximum leakage current occurs at a maximum operating temperature. The current decreases by approximately one-half for
each 8 C to 12 C in the temperature range from 50 C to 125 C.
2
Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown.
3
All functional non-supply pins are internally clamped to VSS and VDD.
4
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
5
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load shunts current greater than maximum injection
current. This is the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the
clock rate is very low (which reduces overall power consumption).

Typical Low-Side Driver (LDS) Characteristics

VDD = 5 V, PORTA, VOL Vs IOL

5
T=-40C
4 T=0C
V OL(V)

T=25C
3
T=85C
2 T=105C
T=125C
1

0
1 2 3 4 5 6 7 8 9 10 11 12 13 14

IOL(mA)

Figure 4. Typical Low-Side Driver (Sink) Characteristics

Low Drive (PTxDSn = 0), VDD = 5.0 V, VOL vs. IOL

MC9S08SF4 Series MCU Data Sheet, Rev. 4

10 Freescale Semiconductor
 DC Characteristics

Typical Low-Side Driver (LDS) Characteristics

VDD = 3 V, PORTA, VOL Vs IOL

3.5

2.5 T=-40C
T=0C
V OL(V)

2
T=25C

1.5 T=85C
T=105C
1
T=125C

0.5

0
1 2 3 4 5

IOL(mA)

Figure 5. Typical Low-Side Driver (Sink) Characteristics

Low Drive (PTxDSn = 0), VDD = 3.0 V, VOL vs. IOL

Typical Low-Side Driver (HDS) Characteristics

VDD = 5 V, PORTA, VOL Vs IOL

1.20

1.00
T=-40C
0.80
T=0C
V OL(V)

T=25C
0.60
T=85C
T=105C
0.40
T=125C

0.20

0.00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

IOL(mA)

Figure 6. Typical Low-Side Driver (Sink) Characteristics

High Drive (PTxDSn = 1), VDD = 5.0 V, VOL vs. IOL

MC9S08SF4 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor 11
DC Characteristics

Typical Low-Side Driver (HDS) Characteristics

VDD = 3 V, PORTA, VOL Vs IOL

1.8
1.6
1.4 T=-40C
1.2 T=0C
V OL(V)

1 T=25C
0.8 T=85C
0.6 T=85
0.4 T=125C
0.2
0
1 2 3 4 5 6 7 8 9 10 11 12 13

IOL(mA)

Figure 7. Typical Low-Side Driver (Sink) Characteristics

High Drive (PTxDSn = 1), VDD = 3.0 V, VOL vs. IOL

Typical High-Side Driver (LDS) Characteristics

VDD = 5 V, PORTA, VOH Vs IOH

6.00

5.00
T=-40C
4.00 T=0C
V OH(V)

T=25C
3.00
T=85C
2.00 T=105C
T=125C
1.00

0.00
0 -1 -2 -3 -4 -5 -6 -7 -8 -9

IOH(mA)

Figure 8. Typical High-Side Driver (Source) Characteristics

Low Drive (PTxDSn = 0), VDD = 5.0 V, VOH vs. IOH

MC9S08SF4 Series MCU Data Sheet, Rev. 4

12 Freescale Semiconductor
 DC Characteristics

Typical High-Side Driver (LDS) Characteristics

VDD = 3 V, PORTA, VOH Vs IOH

3.5

2.5 T=-40C
T=0C
V OH(V)

2
T=25C

1.5 T=85C
T=105C
1
T=125C

0.5

0
0 -1 -2 -3

IOH(mA)

Figure 9. Typical High-Side Driver (Source) Characteristics

Low Drive (PTxDSn = 0), VDD = 3.0 V, VOH vs. IOH

Typical High-Side Driver (HDS) Characteristics

VDD = 5 V, PORTA, VOH Vs IOH

5.20
5.00
4.80
4.60 T=-40C
4.40 T=0C
V OH(V)

4.20 T=25C
4.00 T=85C
3.80 T=105C
3.60 T=125C
3.40
3.20
3.00
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20

IOH(mA)

Figure 10. Typical High-Side Driver (Source) Characteristics

High Drive (PTxDSn = 1), VDD = 5.0 V, VOH vs. IOH

MC9S08SF4 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor 13
Supply Current Characteristics

Typical High-Side Driver (HDS) Characteristics

VDD = 3 V, PORTA, VOH Vs IOH

3.5

2.5 T=-40C
T=0C
V OH(V)

2 T=25C
1.5 T=85C
T=105C
1 T=125C
0.5

0
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15

IOH(mA)

Figure 11. Typical High-Side Driver (Source) Characteristics

High Drive (PTxDSn = 1), VDD = 3.0 V, VOH vs. IOH

3.7 Supply Current Characteristics

This section includes information about power supply current in various operating modes.
Table 7. Supply Current Characteristics

Num C Parameter Symbol VDD (V) Typical1 Max2 Unit

P Run supply current3 measured at 5 1.75 1.77
1 RIDD
D (CPU clock = 2 MHz, fBus = 1 MHz) 3 1.71 1.73 mA

P Run supply current3 measured at 5 5.69 6.25

2 RIDD
D (CPU clock = 16 MHz, fBus = 8 MHz) 3 4.63 4.66 mA

P Run mode supply current3 measured at 5 11.53 12.00

3 RIDD
D (CPU clock = 40 MHz, fBus = 20 MHz) 3 10.39 11.00 mA

P Wait mode supply current4 measured at 5 3.95 4.54

4 WIDD
D (fBus = 8 MHz) 3 3.58 4.00 mA

P Wait mode supply current4 measured at 5 8.36 9.62

5 WIDD mA
D ( fBus = 20 MHz) 3 7.97 8.07
P Stop2 mode supply current
–40 to 85 C 5 1.99 18.47
–40 to 125 C
6 P S2IDD 100 A
D –40 to 85C 16.9
–40 to 125C 3 1.95
D 90

MC9S08SF4 Series MCU Data Sheet, Rev. 4

14 Freescale Semiconductor
 Supply Current Characteristics

Table 7. Supply Current Characteristics (continued)

Num C Parameter Symbol VDD (V) Typical1 Max2 Unit

P Stop3 mode supply current
–40 to 85 C 5 2 18.4
–40 to 125 C
7 P 100 A
S3IDD
D –40 to 85 C 16.82
–40 to 125 C 3 1.97
D 90
D PRACMP (PRG disabled) adder to stop3, 5 28.87 — nA
8 —
D 25 C 3 27.06 — nA
D PRACMP (PRG enabled) adder to stop3, 5 79.42 — nA
9 —
D 25 C 3 57.4 — nA
D 5 25 — nA
10 ADC adder to stop2 or stop3, 25 C —
D 3 6 — nA
D 5 83.52 — nA
11 LVD adder to stop3 (LVDE = LVDSE = 1) —
D 3 83.52 — nA
D Adder to stop3 for oscillator enabled 5 0.03 — A
12 —
D (IREFSTEN = 1) 3 0.01 — A
D TPM1 and TPM2 adder to run mode, 25 C 5 0.16 — mA
13 —
D (CPU clock = 40 MHz, fBus = 20 MHz) 3 0.18 — mA
D PWT1 and PWT2 adder to run mode, 25 C 5 0.43 — mA
14 —
D (CPU clock = 40 MHz, fBus = 20 MHz) 3 0.41 — mA
D PRACMP adder to run mode, 25 C 5 0.35 — mA
15 —
D (CPU clock = 40 MHz, fBus = 20 MHz) 3 0.35 — mA
D MTIM1 and MTIM2 adder to run mode, 25 C 5 0.26 — mA
16 —
D (CPU clock = 40 MHz, fBus = 20 MHz) 3 0.24 — mA
D ADC adder to run mode, 25 C 5 0.42 — mA
17 —
D (CPU clock = 40 MHz, fBus = 20 MHz) 3 0.32 — mA
D IIC adder to run mode, 25 C 5 0.56 — mA
18 —
D (CPU clock = 40 MHz, fBus = 20 MHz) 3 0.53 — mA
1
Typicals are measured at 25 C.
2
Values given here are preliminary estimates prior to completing characterization.
3 All modules except ADC active, and does not include any dc loads on port pins.
4 Most customers are expected to find that the auto-wakeup from a stop mode can be used instead of the higher current wait mode.

MC9S08SF4 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor 15
ICS Characteristics

Typical RIDD (VDD = 5 V, ADC off) Vs Bus Frequency

12.0000
10.0000
T=-40C
8.0000 T=0C
mA

6.0000 T=25C
4.0000 T=85C
T=125C
2.0000
0.0000
1 4 8 20
Bus Frequency

Figure 12. Typical Run IDD vs. Bus Freq. (FEI) (ADC off)

3.8 ICS Characteristics

Refer to Figure 13 for crystal or resonator circuits.
Table 8. ICS Specifications (Temperature Range = –40 to 125 C Ambient )

No. C Characteristic Symbol Minimum Typical1 Maximum Unit

1 T Internal reference start-up time tIRST — 60 100 s

2 P Average internal reference frequency — trimmed fint_t — 39.0625 — kHz

P DCO output frequency Low range (DRS = 00) 16 — 20

3 range — trimmed fdco_t MHz
P Middle range (DRS = 10) 32 — 40

Total deviation of DCO output from trimmed

2
4 P frequency –1.0 to 0.5 3
Over full voltage and temperature range of –40 C
to 125 C
Total deviation of DCO output from trimmed
frequency fdco_t
5 D — –1.0 to 0.5 2 %fdco
Over full voltage and temperature range of –40 C
to 85 C

Total deviation of DCO output from trimmed

frequency
6 D 0.5 
Over fixed voltage and temperature range of 0 to
70 C

7 C FLL acquisition time2,3 tAcquire — — 1 ms

Long term jitter of DCO output clock (averaged

8 C CJitter — 0.02 0.2 %fdco
over a 2 ms interval) 4

MC9S08SF4 Series MCU Data Sheet, Rev. 4

16 Freescale Semiconductor
 AC Characteristics

1
Data in the Typical column was characterized at 5.0 V, 25 C, or the typical recommended value.
2
This parameter is characterized and not tested on each device.
3
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed,
DMX32 bit changed, DRS bit changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE,
and FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at the maximum

fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the FLL circuitry via VDD and VSS and a variation in the crystal oscillator frequency increases the
CJitter percentage for a given interval.

1.00%

0.50%

0.00%
-60 -40 -20 0 20 40 60 80 100 120
Deviation (%)

-0.50%

-1.00% TBD
-1.50%

-2.00%
Temperature

Figure 13. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V)

3.9 AC Characteristics
This section describes AC timing characteristics for each peripheral system.

MC9S08SF4 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor 17
AC Characteristics

3.9.1 Control Timing

Table 9. Control Timing

Parameter Symbol Minimum Typical1 Maximum Unit

Bus frequency (tcyc = 1/fBus) fBus 1 — 20 MHz
2
External reset pulse width textrst 100 — — ns
IRQ pulse width
Asynchronous path2 100
tILIH, tIHIL — — ns
Synchronous path3 1.5 tcyc
KBIPx pulse width
Asynchronous path2 100
tILIH, tIHIL — — ns
Synchronous path3 1.5 tcyc
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0) tRise, tFall — 3 — ns
Slew rate control enabled (PTxSE = 1) — 30 —
BKGD/MS setup time after issuing background debug force
tMSSU 500 — — ns
reset to enter user or BDM modes
BKGD/MS hold time after issuing background debug force
tMSH 100 — — s
reset to enter user or BDM modes 5
1
Data in Typical column was characterized at 5.0 V, 25 C.
2
This is the shortest pulse that is guaranteed to be recognized.
3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
DD and 80% VDD levels. Temperature range –40 C to 125 C.
4 Timing is shown with respect to 20% V
5 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.

textrst

RESET PIN

Figure 14. Reset Timing

tIHIL

IRQ/KBIPx

IRQ/KBIPx

tILIH

Figure 15. IRQ/KBIPx Timing

MC9S08SF4 Series MCU Data Sheet, Rev. 4

18 Freescale Semiconductor
 AC Characteristics

3.9.2 Timer/PWM (TPM) Module Timing

Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 10. TPM/MTIM Input Timing

Function Symbol Min Max Unit

External clock frequency fTCLK dc ftimer/4 MHz

External clock period tTCLK 4 — tcyc
External clock high time tclkh 1.5 — tcyc
External clock low time tclkl 1.5 — tcyc
Input capture pulse width for TPM tICPW 1.5 — tcyc
Timer clock frequency ftimer — 40 MHz

tText
tclkh

TCLK

tclkl

Figure 16. Timer External Clock

tICPW

TPMCHn

TPMCHn

tICPW

Figure 17. Timer Input Capture Pulse

MC9S08SF4 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor 19
ADC Characteristics

3.10 ADC Characteristics

Table 11. ADC Characteristics

Num C Characteristic Conditions Symb Min Typical1 Max Unit Comment

Supply current VDDA 3.6 V

D — 110 —
ADLPC = 1 (3.0 V Typ)
1 IDDA A
ADLSMP = 1 VDDA 5.5 V
D ADCO = 1 — 130 —
(5.0 V Typ)
Supply current VDDA 3.6 V
D — 200 —
ADLPC = 1 (3.0 V Typ)
2 IDDA A
ADLSMP = 0 VDDA 5.5 V
D ADCO = 1 — 220 —
(5.0 V Typ)
Over
Supply current VDDA 3.6 V
D — 320 — temperature
ADLPC = 0 (3.0 V Typ)
3 IDDA A (Typ 25C)
ADLSMP = 1 VDDA 5.5 V
D ADCO = 1 — 360 —
(5.0 V Typ)
Supply current VDDA 3.6V
D — 580 —
ADLPC = 0 (3.0 V Typ)
4 IDDA A
ADLSMP = 0 VDDA 5.5V
D ADCO = 1 — 660 —
(5.0 V Typ)
Stop, Reset,
5 D Supply current IDDA — <1 100 nA
Module Off
D Ref voltage high — VREFH 2.7 VDDA VDDA V
6
D Ref coltage low — VREFL VSSA VSSA VSSA V
High speed
D 0.4 — 8.0
ADC conversion (ADLPC = 0) tADCK =
7 fADCK MHz
clock Low power 1/fADCK
D 0.4 — 4.0
(ADLPC = 1)
High speed
D ADC 2.5 4 6.6
(ADLPC = 0) tADACK =
8 asynchronous fADACK MHz
Low power 1/fADACK
D clock source 1.25 2 3.3
(ADLPC = 1)
Short sample
D 20 20 23 Add 2 to 5
(ADLSMP = 0) tADCK
9 Conversion time tADC tBus =1/fBus
Long sample cycles
D 40 40 43 cycles
(ADLSMP = 1)
Short sample
D 4 4 4
(ADLSMP = 0) tADCK
10 Sample time tADS
Long sample cycles
D 24 24 24
(ADLSMP = 1)
11 D Input voltage — VADIN VREFL — VREFH V
Input
12 D — CADIN — 7 10 pF Not Tested
capacitance
13 D Input impedance — RADIN — 5 15 k Not Tested
Analog source External to
14 D — RAS — — 102 k
impedance MCU

MC9S08SF4 Series MCU Data Sheet, Rev. 4

20 Freescale Semiconductor
 PRACMP Characteristics

Table 11. ADC Characteristics (continued)

Num C Characteristic Conditions Symb Min Typical1 Max Unit Comment

D Ideal resolution 10-bit mode 2.637 4.883 5.371
15 RES mV VREFH/2N
D (1LSB) 8-bit mode 10.547 19.53 21.48
D Total unadjusted 10-bit mode 0 1.5 3.5 Includes
16 ETUE LSB
D error 8-bit mode 0 0.7 1.0 quantization
P Differential 10-bit mode 0 0.5 1.0
17 DNL LSB
C non-linearity3 8-bit mode 0 0.3 0.5
P Integral 10-bit mode 0 0.5 1.0
18 INL LSB
C non-linearity 8-bit mode 0 0.3 0.5
D 10-bit mode 0 1.5 3.1
19 Zero-scale error EZS LSB VADIN = VSSA
D 8-bit mode 0 0.5 0.7
D 10-bit mode 0 1.0 1.5
20 Full-scale error EFS LSB VADIN = VDDA
D 8-bit mode 0 0.5 0.5
Quantization 8-bit mode is
21 D 10-bit mode EQ — — 0.5 LSB
error not truncated
Temp sensor –40–25 C — — 3.266 — —
22 P
slope 25–125 C — — 3.638 — —
Temp sensor
23 P — — — 1.396 — —
voltage
1
Typical values assume VDDA = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 At 4 MHz, for maximum frequency, use proportionally lower source impedance.
3 Monotonicity and no-missing-codes guaranteed

3.11 PRACMP Characteristics

Table 12. PRACMP Specifications

Num C Characteristic Symbol Min Typical Max Unit

1 P Supply voltage VPWR 2.70 — 5.50 V

2 C Supply current (active) (PRG enabled) IDDACT1 — — 60 A

3 C Supply current (active) (PRG disabled) IDDACT2 — — 40 A

4 C Supply current (ACMP and PRG all disabled) IDDDIS — — 2 nA

5 C Analog input voltage VAIN VSS – 0.3 — VDD V

6 C Analog input offset voltage VAIO — 5 40 mV

7 C Analog comparator hysteresis VH 3.0 — 20.0 mV

8 C Analog input leakage current IALKG — — 1 nA

9 C Analog comparator initialization delay tAINIT — — 1.0 s

MC9S08SF4 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor 21
Flash Specifications

Table 12. PRACMP Specifications (continued)

Num C Characteristic Symbol Min Typical Max Unit

VIn1
10 D Programmable reference generator inputs 2.7 5.0 5.5 V
(VDD50)

VIn2
11 D Programmable reference generator inputs 2.25 2.5 2.75 V
(VDD25)

12 C Programmable reference generator step size Vstep –0.25 0 0.25 LSB

13 P Programmable reference generator voltage range Vprgout VIn/32 — Vin V

3.12 Flash Specifications

This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section.
Table 13. Flash Characteristics

Characteristic Symbol Min Typical Max Unit

Supply voltage for program/erase

Vprog/erase 2.7 — 5.5 V
–40C to 125C
Supply voltage for read operation VRead 2.7 — 5.5 V
Internal FCLK frequency1 fFCLK 150 — 200 kHz
Internal FCLK period (1/FCLK) tFcyc 5 — 6.67 s
Byte program time (random location)(2) tprog 9 tFcyc
Byte program time (burst mode)(2) tBurst 4 tFcyc
Page erase time2 tPage 4000 tFcyc
Mass erase time(2) tMass 20,000 tFcyc
Program/erase endurance3
TL to TH = –40 C to 125 C 10,000 — — cycles
T = 25C — 100,000 —
Data retention4 tD_ret 15 100 — years
1
The frequency of this clock is controlled by a software setting.
2 These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3
Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Delta
defines typical endurance, please refer to engineering bulletin Typical Endurance for Nonvolatile Memory (document
EB619/D).
4 Typical data retention values are based on intrinsic capability of the technology measured at a high temperature and de-rated

to 25 C using the Arrhenius equation. For additional information on how Delta defines typical data retention, please refer to
engineering bulletin Typical Data Retention for Nonvolatile Memory (document EB618/D).

MC9S08SF4 Series MCU Data Sheet, Rev. 4

22 Freescale Semiconductor
 Mechanical Drawings

4 Ordering Information
This section contains ordering information for the device numbering system.
Example of the device numbering system:
MC 9 S08 SF 4 X XX

Status
(MC = Fully Qualified) Package designator (see Table 14)
Temperature range
Memory (M= –40 C to 125 C)
(9 = Flash-based)
(V = –40 C to 105 C)
Core (C = –40 C to 85 C)
Family Approximate flash size in kbytes

5 Package Information
Table 14. Package Descriptions

Pin Count Package Type Abbreviation Designator Case No. Document No.
20 Thin Shrink Small Outline Package TSSOP TJ 948E 98ASH70169A
16 Thin Shrink Small Outline Package TSSOP TG 948F 98ASH70247A

5.1 Mechanical Drawings

The following pages are mechanical drawings for the packages described in Table 14. For the latest
available drawings, please visit our web site (http://www.freescale.com) and enter the package’s document
number into the keyword search box.

MC9S08SF4 Series MCU Data Sheet, Rev. 4

Freescale Semiconductor 23
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MC9S08SF4
Rev. 4
9/2011