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Computer System Architecture Notes

The document discusses several topics related to computer organization and digital logic including: - Binary operations and conversions between binary and decimal - Boolean algebra concepts like Boolean expressions and truth tables - Logic gate operations and logic circuit design - Binary arithmetic like binary addition and multiplication - Computer organization concepts like instruction cycle, program counter, and machine language The document contains examples and explanations of these various digital logic and computer organization topics over its many pages. It provides information and solved examples to help explain essential concepts.

Uploaded by

Saurabh Pandey
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
23 views

Computer System Architecture Notes

The document discusses several topics related to computer organization and digital logic including: - Binary operations and conversions between binary and decimal - Boolean algebra concepts like Boolean expressions and truth tables - Logic gate operations and logic circuit design - Binary arithmetic like binary addition and multiplication - Computer organization concepts like instruction cycle, program counter, and machine language The document contains examples and explanations of these various digital logic and computer organization topics over its many pages. It provides information and solved examples to help explain essential concepts.

Uploaded by

Saurabh Pandey
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Bit: it is the smallest memory measurement unit. It
stands for “ Binary Digit”.
Binary operations
0 +0 =0 1+0 = 1
0+1=1 1 + 1 = 10
0.0 = 0 0.1=0
1.0 = 0 1.1 =1

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(1011)2 * (101)2 = 1011 *1 +1011* 0 +1011*1
1011
X101
=1011
0000x
1011 x
=1 10 1 11
Ans= 110111
= 1*25 + 1 *24 +1 *22 +1*21 +1*20
= 32 + 16 + 4+ 2 + 1 = 55

678 * 12

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Q1.
(511.52)10 = ( )5
For the non- fractional part , we have,
(511)10 = (4021)5
5)511(1
5 ) 102(2
5 ) 20(0
4 (stop here as 4<5 and read from bottom to top)
For the fractional part, we have
0.52 * 5 = 2.60
0.60*5 = 3.00 // considering only the fractional part.
0.0 * 5 = 0.0 // stop here
Note 1: Stop calculation when the result of the multiplication is 0 or there is repeating result.
Note 2: Read only the integer part from top to bottom (opposite to non-fractional part).
Hence (511.52)10 = (4021.23)5

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+6= 00000110 (using 8 bits)
11111001 1’s complement of 6
11111001
+1 =11111010

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Construct the truth table of the following Boolean
expressions:

(a)(xy + z)(y + xz)


(b) (A' + B)(B' + C)
(c) y'z + wxy' + wxz' + w'x'z

AND-> ^
OR V
XOR

(a)Let P=(xy +z).(y+xz)


X Y Z XY XY+Z XZ Y+XZ P
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0
0 1 0 0 0 0 1 0
0 1 1 0 1 0 1 1
1 0 0 0 0 0 0 0
1 0 1 0 1 1 1 1
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1 1 0 1 1 0 1 1
1 1 1 1 1 1 1 1

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X +1 = x+ (x +x’) =x +x’
Q1. Express F= A+B’C into SOP.
There are 2 terms “A” and “B’C”. In the Ist term B & C are
absent and in the 2nd term A is absent.
Introducing missing variables, we have
A= A.(B+B’)= A.B +A.B’
=A.B.(C+C’) + A.B’.(C+C’)
= ABC + ABC’ +AB’C +AB’C’
B’C =B’C.(A+A’)=AB’C + A’B’C
Now combining all terms we have
F= ABC +ABC’ +AB’C+AB’C’ +AB’C +A’B’C
=ABC + ABC’ +AB’C + AB’C’+ A’B’C (Discarding duplicate
terms and writing them only once).
=m7 +m6 +m5 + m4 +m1
=m1 + m4 +m5 +m6 +m7
=∑(1,4,5,6,7)

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Note:- Ignore last two steps of the above simplification.

Note: There is a mistake in the logic diagram. Correct it.

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AA’ +B+C+D
Let B+C+D =X
So we have AA’ + X = (A +X) . (A’+X)
= (A + B+C+D ). (A’ +B+C+D)

A B C D Maxterms Minterms
0 0 0 0 0 M15 m0
1 0 0 0 1 M14 m1
2 0 0 1 0 M13 m2
3 0 0 1 1 M12 m3
4 0 1 0 0 M11 m4
5 0 1 0 1 M10 m5
6 0 1 1 0 M9 m6
7 0 1 1 1 M8 m7
8 1 0 0 0 M7 m8
9 1 0 0 1 M6 m9
10 1 0 1 0 M5 m10

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11 1 0 1 1 M4 m11
12 1 1 0 0 M3 m12
13 1 1 0 1 M2 m13
14 1 1 1 0 M1 m14
15 1 1 1 1 M0 m15

F= XY +X’Z +YZ =XY +X’Z + YZ.(X+X’)

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Q. Design a counter that counts the following sequence:
0,3,6,9.
PRESENT STATE NEXT STATE
A3 A2 A1 A0 A3 A2 A1 A0
0 0 0 0 0 0 1 1
0 0 0 1 X X X X
0 0 1 0 X X X X
0 0 1 1 0 1 1 0
0 1 0 0 X X X X
0 1 0 1 X X X X
0 1 1 0 1 0 0 1
0 1 1 1 X X X X
1 0 0 0 X X X X
1 0 0 1 0 0 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X

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Q2.Design a combinational circuit that
takes three inputs x,y and z. The
circuit produces one output z1 = 1 if
the number of 1’s in the input
combination is even otherwise 0.
Q3.Design a combinational circuit that
takes four inputs w,x,y and z and
produces one output z1 = 1 if the input
is divisible by 3 otherwise 0.

X Y Z Z1
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

KMAP for z1

yz 00 01 11 10

1 1
1 1
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X’y’z’ +xy’z + x’yz + xyz’

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1 1 1 0 0
1 1 1 1 1

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Note : XOR is an odd function. This implies if we supply
odd number of 1’s XOR function, the result is always 1.
Cout<<”abc”

100111011010
pcode operand

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Assume that the length of instruction is 16 bits
Address instruction
009 x=y
011 print x
013 x++
015 print x
We know that PC contains the address of the next
instruction to be executed but before execution of the
program PC will keep the address of the first instruction
and when x=y goes for execution, PC will be incremented
by 2.

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