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Lab

The document contains VHDL code for designing basic digital logic circuits including a half adder, full adder using half adders, ripple carry adder, and an adder/subtractor unit. It defines the entities, ports, and architectures for each module and instantiates lower level components like half adders to build higher level functions like a full adder and ripple carry adder.

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Souvik Pal
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40 views4 pages

Lab

The document contains VHDL code for designing basic digital logic circuits including a half adder, full adder using half adders, ripple carry adder, and an adder/subtractor unit. It defines the entities, ports, and architectures for each module and instantiates lower level components like half adders to build higher level functions like a full adder and ripple carry adder.

Uploaded by

Souvik Pal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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HALF ADDER:

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:45:03 03/16/2023
-- Design Name:
-- Module Name: ha - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ha is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end ha;

architecture Behavioral of ha is

begin
s<= a XOR b;
c<= a AND b;
end Behavioral;

FULL ADDER USING HALF ADDER:


----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:51:26 03/16/2023
-- Design Name:
-- Module Name: fulladds - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladds is
Port ( af : in STD_LOGIC;
bf : in STD_LOGIC;
cin : in STD_LOGIC;
sf : out STD_LOGIC;
cout : out STD_LOGIC);
end fulladds;

architecture Behavioral of fulladds is


component ha is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end component;
signal sig1, sig2,sig3:STD_LOGIC;
begin
h1: ha port map(af, bf, sig1, sig2);
h2: ha port map(sig1, cin, sf, sig3);
cout<= sig3 OR sig2;

end Behavioral;

RIPPLE CARRY ADDER:


----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:38:03 03/16/2023
-- Design Name:
-- Module Name: ripple - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ripple is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end ripple;

architecture Behavioral of ripple is


component fulladds is
Port ( af : in STD_LOGIC;
bf : in STD_LOGIC;
cin : in STD_LOGIC;
sf : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
signal sig: STD_LOGIC_VECTOR (2 downto 0);
begin
f1: fulladds port map(a(0), b(0), cin, s(0), sig(0));
f2: fulladds port map(a(1), b(1), sig(0), s(1), sig(1));
f3: fulladds port map(a(2), b(2), sig(1), s(2), sig(2));
f4: fulladds port map(a(3), b(3), sig(2), s(3), cout);
end Behavioral;

ADDER SUBSTACTOR COMPOSITE UNIT:


----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:02:37 03/16/2023
-- Design Name:
-- Module Name: addsub - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity addsub is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
sw : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end addsub;
architecture Behavioral of addsub is
component fa1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
caary : out STD_LOGIC);
end component;
signal sig: STD_LOGIC_VECTOR(3 downto 0);
signal cp: STD_LOGIC_VECTOR(2 downto 0);
begin
sig(0)<=sw XOR b(0);
sig(1)<=sw XOR b(1);
sig(2)<=sw XOR b(2);
sig(3)<=sw XOR b(3);
f1: fa1 port map(a(0),sig(0), sw, s(0), cp(0));
f2: fa1 port map(a(1),sig(1), cp(0), s(1), cp(1));
f3: fa1 port map(a(2),sig(2), cp(1), s(2), cp(2));
f4: fa1 port map(a(3),sig(3), cp(2), s(3), cout);
end Behavioral;

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