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Lab 13 (Sequential Circuit Design and Implementation)

1) The document describes an electronics lab experiment on designing and implementing basic sequential circuits like latches and flip-flops. 2) The objectives are to design latches like SR, D, and JK latches and flip-flops like SR and D flip-flops. The experiment also involves converting a flip-flop from one type to another. 3) The equipment used includes logic gates, 7474 and 7476 ICs, connecting wires, and a digital logic trainer. Tasks involve implementing an SR latch, a D flip-flop, and converting a D flip-flop to a T flip-flop.

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Husnain 18
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45 views

Lab 13 (Sequential Circuit Design and Implementation)

1) The document describes an electronics lab experiment on designing and implementing basic sequential circuits like latches and flip-flops. 2) The objectives are to design latches like SR, D, and JK latches and flip-flops like SR and D flip-flops. The experiment also involves converting a flip-flop from one type to another. 3) The equipment used includes logic gates, 7474 and 7476 ICs, connecting wires, and a digital logic trainer. Tasks involve implementing an SR latch, a D flip-flop, and converting a D flip-flop to a T flip-flop.

Uploaded by

Husnain 18
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 6

_________________________________________________________________________

Title : Sequential Circuits Design And Implementation

Date Of
:
Experiment

Lab Number : 14

Instructor :

:
Name Afaq Ahmad

:
Roll No 210501032

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_________________________________________________________________________

Objectives:
1. Design and Implementation of basic sequential Circuit (latches and Flipflops).
2. Design and Implementation of conversion of Flipflop from one type to another.

Equipment:
1. Logic Gates.
2. 7474 Dual Positive-Edge-Triggered D-Type Flip-Flop IC.
3. 7476 Dual J-K M/S Flip-Flop IC.
4. Connecting wire.
5. Digital logic Trainer.

Theory
Sequential Circuits:
A sequential circuit is a logical circuit, where the output depends on the present value of the
input signal as well as of combinational circuit and a storage element.

In memory elements we have two categories. One is latch and other one is flipflop. Basically,
latch
Latches:
Latches are basic storage elements that operate with signal levels (rather than signal transitions).
Latches
SR Latch:
The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates,
and two inputs labeled S for set and R for reset. The latch has two useful states. When output Q =
1 and Q’ = 0, the latch is said to be in the set state. When Q = 0 and Q’= 1, it is in the reset state.

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Outputs Q and Q’ are normally the complement of each other. However, when both inputs are
equal to 1 at the same state.
Following circuit shows the implementation of SR latch using NOR gate.

And, implementation of SR latch using NAND gate.

As, it can be seen that with use of NAND gate, previous state is retained at 1,1 position we can
make it to retain last data if Set and Reset inputs are first passed through not gate.
The SR latches with
D-Latch:
The D latch is the simple extension of the gated SR latch which removes the possibility of
invalid input states. When the enable line of the D latch is high, the output will always reflect the
logic level which is present at the D input. When the input of the D latch falls, the last state of
the D latch input is trapped and held in the latch. That is why it is also called as a transparent
latch. When enable is asserted, the latch is said to be transparent.

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JK- Latch:
JK latch is similar to RS latch. This latch consists of 2 inputs J and K as shown in the below
figure. The ambiguous state has been eliminated here: when the inputs of Jk latch are high, then
output toggles. The output feedback to inputs is the only difference we see here, which is not
there in the RS latch.

T-Latch:
T latch is formed when the inputs of the JK latch are shorted. When the input is high, then the
output toggles

Flipflops:

SR-Flipflop:
In flipflop, only clock input is added which can be positive edge triggered or negative edge
triggered. the circuit will work for positive edge triggered. And for negativeedge triggered the
circuitwork when it changes from 1 to 0.

D-Flipflop:
The D flip-flop is the modification of the SR flip flop which is shown in the figure. The i/p D
goes directly into the input S and the complement of the input D goes to the input R. The D input
is sampled during the existence of a clock pulse. If it is 1, then the flip-flop is switched to the set
state. If it is 0, then the flip-flop switches to the clear state.

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Task 1:
SR LATCH CIRCUIT AND IMPLEMENT IT USING NOR

S R Q Q’
1 0 1 0
0 0 1 0
0 1 0 1
0 0 0 1
1 1 0 0

TASK 2
D FLIP FLOP

CLK D Q Q’
0 0 Q Q’
0 1 Q Q’
1 0 0 1
1 1 1 0

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TASK 3
D FLIP FLOP TO T FLIP FLOP

INPUT OUTPUT OUTPUT D OUTPUT


T Qp Qn D
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0

Electronics Lab Page 6

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