Facilitator: Mr. D. I.

BYNITE

Topics covered:
Instruction Set Architecture
 Instruction execution and sequencing

❑ Recall the fetch/execute cycle of instruction execution.

❑ In order to complete a meaningful task, a number of
instructions need to be executed.
❑ During the fetch/execution cycle of one instruction, the
Program Counter (PC) is updated with the address of the
next instruction:
◆ PC contains the address of the memory location from which the
next instruction is to be fetched.
❑ When the instruction completes its fetch/execution cycle,
the contents of the PC point to the next instruction.
❑ Thus, a sequence of instructions can be executed to
complete a task.

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 Instruction execution and sequencing (contd..)

❑ Simple processor model

❑ Processor has a number of general purpose registers.
❑ Word length is 32 bits (4 bytes).
❑ Memory is byte addressable.
❑ Each instruction is one word long.
❑ Instructions allow one memory operand per instruction.
◆ One register operand is allowed in addition to one memory
operand.
❑ Simple task:
◆ Add two numbers stored in memory locations A and B.
◆ Store the result of the addition in memory location C.
Move A, R0 (Move the contents of location A to register R0)
Add B, R0 (Add the contents of location B to register R0)
Move R0, C (Move the contents of register R0 to location C)

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Instruction execution and sequencing (contd..)
Execution steps:
0 Move A, R0
Step I:
4 Add B, R0 -PC holds address 0.
8 Move R0, C -Fetches instruction at address 0.
-Fetches operand A.
-Executes the instruction.
-Increments PC to 4.
Step II:
-PC holds address 4.
A -Fetches instruction at address 4.
-Fetches operand B.
-Executes the instruction.
-Increments PC to 8.
B Step III:
-PC holds address 8.
-Fetches instruction at address 8.
-Executes the instruction.
C -Stores the result in location C.
Instructions are executed one at a time in order of increasing addresses.
“Straight line sequencing”
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 Instruction execution and sequencing (contd..)

❑ Consider the following task:

◆ Add 10 numbers.
◆ Number of numbers to be added (in this case 10) is stored in
location N.
◆ Numbers are located in the memory at NUM1, .... NUM10
◆ Store the result in SUM.
Move NUM1, R0 (Move the contents of location NUM1 to register R0)
Add NUM2, R0 (Add the contents of location NUM2 to register R0)
Add NUM3, R0 (Add the contents of location NUM3 to register R0)
Add NUM4, R0 (Add the contents of location NUM4 to register R0)
Add NUM5, R0 (Add the contents of location NUM5 to register R0)
Add NUM6, R0 (Add the contents of location NUM6 to register R0)
Add NUM7, R0
Add NUM8, R0
Add NUM9, R0
Add NUM10, R0
Move R0, SUM (Move the contents of register R0 to location SUM)

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 Instruction sequencing and execution (contd..)

❑ Separate Add instruction to add each number in a list,

leading to a long list of Add instructions.
❑ Task can be accomplished in a compact way, by using the
Branch instruction.

Move N, R1 (Move the contents of location N, which is the number

of numbers to be added to register R1)
Clear R0 (This register holds the sum as the numbers are added)
LOOP Determine the address of the next number.
Add the next number to R0.
Decrement R1 (Counter which indicates how many numbers have been
added so far).
Branch>0 LOOP (If all the numbers haven’t been added, go to LOOP)
Move R0, SUM

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 Instruction execution and sequencing (contd..)

❑ Decrement R1:
◆ Initially holds the number of numbers that is to be added
(Move N, R1).
◆ Decrements the count each time a new number is added
(Decrement R1).
◆ Keeps a count of the number of the numbers added so far.
❑ Branch>0 LOOP:
◆ Checks if the count in register R1 is 0 (Branch > 0)
◆ If it is 0, then store the sum in register R0 at memory location
SUM (Move R0, SUM).
◆ If not, then get the next number, and repeat (go to LOOP). Go
to is specified implicitly.
❑ Note that the instruction (Branch > 0 LOOP) has no explicit
reference to register R1.

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 Instructions execution and sequencing (contd..)

❑ Processor keeps track of the information about the results

of previous operation.
❑ Information is recorded in individual bits called “condition
code flags”. Common flags are:
◆ N (negative, set to 1 if result is negative, else cleared to 0)
◆ Z (zero, set to 1 if result is zero, else cleared to 0)
◆ V (overflow, set to 1 if arithmetic overflow occurs, else
cleared)
◆ C (carry, set to 1 if a carry-out results, else cleared)
❑ Flags are grouped together in a special purpose register
called “condition code register” or “status register”.
If the result of Decrement R1 is 0, then flag Z is set.
Branch> 0, tests the Z flag.
If Z is 1, then the sum is stored.
Else the next number is added.

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 Instruction execution and sequencing (contd..)

❑ Branch instructions alter the sequence of program execution

◆ Recall that the PC holds the address of the next instruction to
be executed.
◆ Do so, by loading a new value into the PC.
◆ Processor fetches and executes instruction at this new
address, instead of the instruction located at the location that
follows the branch.
◆ New address is called a “branch target”.
❑ Conditional branch instructions cause a branch only if a
specified condition is satisfied
◆ Otherwise the PC is incremented in a normal way, and the next
sequential instruction is fetched and executed.
❑ Conditional branch instructions use condition code flags to
check if the various conditions are satisfied.

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 Instruction sequencing and execution (contd..)

❑ How to determine the address of the next number?

❑ Recall the addressing modes:
◆ Initialize register R2 with the address of the first number
using Immediate addressing.
◆ Use Indirect addressing mode to add the first number.
◆ Increment register R2 by 4, so that it points to the next
number.

Move N, R1
Move #NUM1, R2 (Initialize R2 with address of NUM1)
Clear R0
LOOP Add (R2), R0 (Indirect addressing)
Add #4, R2 (Increment R2 to point to the next number)
Decrement R1
Branch>0 LOOP
Move R3, SUM

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 Instruction execution and sequencing (contd..)

❑ Note that the same can be accomplished using

“autoincrement mode”:

Move N, R1
Move #NUM1, R2 (Initialize R2 with address of NUM1)
Clear R0
LOOP Add (R2)+, R0 (Autoincrement)
Decrement R1
Branch>0 LOOP
Move R3, SUM

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 Stacks

❑ A stack is a list of data elements, usually words or bytes

with the accessing restriction that elements can be added or
removed at one end of the stack.
◆ End from which elements are added and removed is called the
“top” of the stack.
◆ Other end is called the “bottom” of the stack.
❑ Also known as:
◆ Pushdown stack.
◆ Last in first out (LIFO) stack.
❑ Push - placing a new item on the stack.
❑ Pop - Removing the top item from the stack.

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 Stacks (contd..)

❑ Data stored in the memory of a computer can be organized

as a stack.
◆ Successive elements occupy successive memory locations.
❑ When new elements are pushed on to the stack they are
placed in successively lower address locations.
◆ Stack grows in direction of decreasing memory addresses.
❑ A processor register called as “Stack Pointer (SP)” is used
to keep track of the address of the element that is at the
top at any given time.
◆ A general purpose register could serve as a stack pointer.

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 Subroutines

❑ In a program subtasks that are repeated on different data

values are usually implemented as subroutines.
❑ When a program requires the use of a subroutine, it
branches to the subroutine.
◆ Branching to the subroutine is called as “calling” the subroutine.
◆ Instruction that performs this branch operation is Call.
❑ After a subroutine completes execution, the calling program
continues with executing the instruction immediately after
the instruction that called the subroutine.
◆ Subroutine is said to “return” to the program.
◆ Instruction that performs this is called Return.
❑ Subroutine may be called from many places in the program.
◆ How does the subroutine know which address to return to?

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 Subroutines (contd..)

❑ Recall that when an instruction is being executed, the PC

holds the address of the next instruction to be executed.
◆ This is the address to which the subroutine must return.
◆ This address must be saved by the Call instruction.
❑ Way in which a processor makes it possible to call and return
from a subroutine is called “subroutine linkage method”.
❑ The return address could be stored in a register called as
“Link register”
❑ Call instruction:
◆ Stores the contents of the PC in a link register.
◆ Branches to the subroutine.
❑ Return instruction:
◆ Branch to the address contained in the link register.

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 Subroutines (contd..)

Memory Memory
location Calling program location Subroutine SUB •Calling program calls a subroutine,
whose first instruction is at address
1000.
200 Call SUB 1000 first instruction
•The Call instruction is at address
204 next instruction 200.
•While the Call instruction is being
Return executed, the PC points to the next
instruction at address 204.
•Call instructions stores address 204
in the Link register, and loads 1000
1000
into the PC.
•Return instruction loads back the
PC 204 address 204 from the link register
into the PC.

Link 204

Call Return

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 Subroutines and stack

❑ For nested subroutines:

◆ After the last subroutine in the nested list completes
execution, the return address is needed to execute the return
instruction.
◆ This return address is the last one that was generated in the
nested call sequence.
◆ Return addresses are generated and used in a “Last-In-First-
Out” order.
❑ Push the return addresses onto a stack as they are
generated by subroutine calls.
❑ Pop the return addresses from the stack as they are needed
to execute return instructions.

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 Assembly language

❑ Recall that information is stored in a computer in a binary

form, in a patterns of 0s and 1s.
❑ Such patterns are awkward when preparing programs.
❑ Symbolic names are used to represent patterns.
◆ So far we have used normal words such as Move, Add, Branch,
to represent corresponding binary patterns.
❑ When we write programs for a specific computer, the normal
words need to be replaced by acronyms called mnemonics.
◆ E.g., MOV, ADD, INC

❑ A complete set of symbolic names and rules for their use

constitute a programming language, referred to as the
assembly language.

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 Assembly language (contd..)

❑ Programs written in assembly language need to be translated

into a form understandable by the computer, namely, binary,
or machine language form.
❑ Translation from assembly language to machine language is
performed by an assembler.
◆ Original program in assembly language is called source program.
◆ Assembled machine language program is called object program.
❑ Each mnemonic represents the binary pattern, or OP code for
the operation performed by the instruction.
❑ Assembly language must also have a way to indicate the
addressing mode being used for operand addresses.
❑ Sometimes the addressing mode is indicated in the OP code
mnemonic.
◆ E.g., ADDI may be a mnemonic to indicate an addition operation
with an immediate operand.
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 Assembly language (contd..)

❑ Assembly language allows programmer to specify other

information necessary to translate the source program into
an object program.
◆ How to assign numerical values to the names.
◆ Where to place instructions in the memory.
◆ Where to place data operands in the memory.
❑ The statements which provide additional information to the
assembler to translate source program into an object
program are called assembler directives or commands.

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 Assembly language (contd..)
EQU:
Memory Addressing •Value of SUM is 200.
address or data
ORIGIN:
label Operation information
•Place the datablock at 204.
DATAWORD:
Assembler directives SUM EQU 200 •Place the value 100 at 204
ORIGIN 204 •Assign it label N.
N DA T AW ORD 100 •N EQU 100
NUM1 RESERVE 400 RESERVE:
ORIGIN 100 •Memory block of 400 words
Statements that ST AR T MO VE N,R1 is to be reserved for data.
generate MO VE #NUM1,R2
•Associate NUM1 with address
machine CLR R0
instructions LOOP ADD (R2),R0 208
ADD #4,R2 ORIGIN:
DEC R1 •Instructions of the object
BGTZ LOOP program to be loaded in memory
MOVE R0,SUM starting at 100.
Assembler directives RETURN RETURN:
END •Terminate program execution.
END:
•End of the program source text
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 Assembly language (contd..)
❑ Assembly language instructions have a generic form:
Label Operation Operand(s) Comment
❑ Four fields are separated by a delimiter, typically one or
more blank characters.
❑ Label is optionally associated with a memory address:
◆ May indicate the address of an instruction to be executed.
◆ May indicate the address of a data item.
❑ How does the assembler determine the values that
represent names?
◆ Value of a name may be specified by EQU directive.
• SUM EQU 100
◆ A name may be defined in the Label field of another
instruction, value represented by the name is determined by
the location of that instruction in the object program.
• E.g., BGTZ LOOP, the value of LOOP is the address of the
instruction ADD (R2) R0
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 Assembly language (contd..)

❑ Assembler scans through the source program, keeps track of

all the names and corresponding numerical values in a “symbol
table”.
◆ When a name appears second time, it is replaced with its value
from the table.
❑ What if a name appears before it is given a value, for
example, branch to an address that hasn’t been seen yet
(forward branch)?
◆ Assembler can scan through the source code twice.
◆ First pass to build the symbol table.
◆ Second pass to substitute names with numerical values.
◆ Two pass assembler.

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 Encoding of machine instructions

❑ Instructions specify the operation to be performed and the

operands to be used.
❑ Which operation is to be performed and the addressing
mode of the operands may be specified using an encoded
binary pattern referred to as the “OP code” for the
instruction.
❑ Consider a processor with:
◆ Word length 32 bits.
◆ 16 general purpose registers, requiring 4 bits to specify the
register.
◆ 8 bits are set aside to specify the OP code.
◆ 256 instructions can be specified in 8 bits.

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Encoding of machine instructions (contd..)
One-word instruction format.

8 7 7 10

OP code Source Dest Other info

Opcode : 8 bits.
Source operand : 4 bits to specify a register
3 bits to specify the addressing mode.
Destination operand : 4 bits to specify a register.
3 bits to specify the addressing mode.
Other information : 10 bits to specify other information
such as index value.

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Encoding of machine instructions (contd..)
What if the source operand is a memory location specified
using the absolute addressing mode?

8 3 7 14

OP code Source Dest

Opcode : 8 bits.
Source operand : 3 bits to specify the addressing mode.
Destination operand : 4 bits to specify a register.
3 bits to specify the addressing mode.

•Leaves us with 14 bits to specify the address of the memory location.

•Insufficient to give a complete 32 bit address in the instruction.
•Include second word as a part of this instruction, leading to a
two-word instruction.

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Encoding of machine instructions (contd..)

Two-word instruction format.

OP code Source Dest Other info

Memory address/Immediate operand

•Second word specifies the address of a memory location.

•Second word may also be used to specify an immediate operand.

•Complex instructions can be implemented using multiple words.

•Complex Instruction Set Computer (CISC) refers to processors
using instruction sets of this type.

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 Encoding of machine instructions (contd..)

❑ Insist that all instructions must fit into a single 32 bit word:
◆ Instruction cannot specify a memory location or an immediate
operand.
◆ ADD R1, R2 can be specified.
◆ ADD LOC, R2 cannot be specified.
◆ Use indirect addressing mode: ADD (R3), R2
◆ R3 serves as a pointer to memory location LOC.
❑ How to load address of LOC into R3?
◆ Relative addressing mode.

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 Encoding of machine instructions (contd..)

❑ Restriction that an instruction must occupy only one word

has led to a style of computers that are known as Reduced
Instruction Set Computers (RISC).
◆ Manipulation of data must be performed on operands already in
processor registers.
◆ Restriction may require additional instructions for tasks.
❑ However, it is possible to specify three operand instructions into a
single 32-bit word, where all three operands are in registers:

Three-operand instruction

OP code Ri Rj Rk Other info

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Thank You for Listening !

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