CC317 Digital System Design

Spring 2022
Lecture 8

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Algorithmic State
Machines (ASM)
 Algorithmic State Machines (ASM)
o The function of a state machine (or sequential circuit) can be represented by a state
table or a state diagram.
o What is wrong with state diagrams?
o Gets messy as states grow
o Decisions to move to different states is not present.

o Solution?
o A flowchart is a way of showing actions and control flow in an algorithm.
❑An Algorithmic State Machine (ASM) is simply a flowchart-like way to specify
state diagrams for sequential logic and, optionally, actions performed in a datapath.
❑While flowcharts typically do not specify “time”, an ASM explicitly specifies a
sequence of actions and their timing relationships.
 ASM Primitives
1.State Box ❑ The State Box is a rectangle, marked with the symbolic state name,
(a rectangle) containing register transfers and output signals activated when the
control unit is in the state.

(Input)
START
2.Scalar Decision Box ❑ The Scalar Decision Box is a diamond that describes the effects of a
(a diamond) specific input condition on the control. It has one input path and two
exit paths, one for TRUE (1) and one for FALSE (0).

00
01
Z, Q0
10
3.Vector Decision Box ❑ The Vector Decision Box is a hexagon that describes the effects of a
(a hexagon) specific n-bit (n > 2) vector of input conditions on the control. It has one
input path and up to 2n exit paths, each corresponding to a binary vector
value.
From Decision Box(es)

(Register transfers ❑ The Conditional Output Box is an oval with entry from a decision block
4.Conditional Output Box (oval). and outputs activated for the decision conditions being satisfied.
R ← 0
 State Box

(Symbolic Name) (Optional state code)

• State box – Represents one state in the ASM
IDLE 0000
• Equivalent to a node in a state diagram or a row in a state table. (Register transfers
or outputs)
❑ The symbolic name for the state marked outside the upper left top R←0
RUN
❑ An optional state code, if assigned, outside the upper right top

• Contains register transfer actions or output signals

• It is customary to write only the name of the signal that has to be asserted in the given state, e.g., z instead of z<=1.

• Also, it might be useful to write an action to be taken, e.g., count <= count + 1, and only later translate it to asserting
a control signal that causes a given action to take place (e.g., enable signal of a counter).

• Operations will take place at the end of the clock period

 State Box

❑ State name T3

❑ Binary code of T3 – 011

❑ Register operation R  0

❑ START – name of outputs signal

generated in this stage
 Scalar Decision Box
❑A diamond with:
❑ One input path (entry point). (False Condition) (True Condition)
0 (Input) 1
❑ One input condition, placed in the center of the box, that is tested.
START
❑ A TRUE exit path taken if the condition is true
(logic 1).

❑ A FALSE exit path taken if the condition is false

(logic 0).

❑indicates that a given condition is to be tested and the exit

path is to be chosen accordingly.

❑Shortcut notation: w means “is w equal to 1?”

 Vector Decision Box
A hexagon with:
❑One Input Path (entry point). (Binary Vector Values) (Binary Vector Values)
(Vector of Input
❑A vector of input conditions, placed in the center of 00
Conditions)
10

the box, that is tested. 01 Z, Q0

❑Up to 2n output paths. The path taken has a binary

vector value that matches the vector input condition
 Conditional Output Box
❑An oval with: From Decision Box(es)
❑One input path from a decision box or decision boxes.

❑One output path

(Register transfers
❑Register transfers or outputs that occur only if the or outputs)
R←0
conditional path to the box is taken. RUN

• The outputs depend on the state variables and inputs

• The condition that determines when such outputs are generated

is placed in a separate decision box
 Conditional Output Box
•In state T1

Output signal START generated

Status of input E checked

• If E = 1, R  0,

otherwise remains unchanged

• Conditional operation executed depending on result

of coming from decision box

 ASM Blocks
11

State
One state box along with all decision and conditional output boxes Entry Path
State Code
connected to it is called an ASM Block. * ***
❑ The ASM Block State State Box
Name
includes all items on the path from the current state to the same or State ASM
Output List
T F
Block
other states. Condition

❑ It has one entry path which leads directly to its state box, and one Condition Output
Box Box
or more exit paths. Conditional
Output List
❑ Each exit path must lead directly to a state, including the state box Exits to
other ASM Blocks
in itself.

❑ A path through an ASM block from its state box to an exit path is
called a link path.
 ASM Blocks

• An ASM block describes the operation of the system during the state T0
Initial state
time in which it is in the state associated with the block.
0
S
• The outputs listed in the state box are asserted.
1
A 0
• The conditions indicated in the decision boxes are evaluated F 0
T1
simultaneously to determine which link path is to be followed. AA+ 1

• If a conditional box is found in the selected path, then the outputs 0

A2
1

found in its output list are asserted. E 0 E1

3 ASM blocks
• Boolean expression may be written for each link path. The selected A3
0

link paths are those that evaluate to logic-1.CC T2 1

F1
ASM Blocks
 Example (1)

❖ Find the ASM chart corresponding to the following A

description
0 1
1. There are two states A, B
X
2. If in state A and input X is `0’ then the next state is A
B
3. If in state A and input X is `1’ then the next state is B Z=1

4. If in state B and input Y is `1’ then the next state is B

5. If in state B and input Y is `0’ then the next state is A 1 0

Y
6. Output Z is equal to `1’ while the circuit is in state B
 ASM for Odd Parity Checker

Example: Odd Parity Checker

Assert output whenever input bit stream has odd # of 1's
Even 0
Out ← 0

0
In = 1

1
Odd

Out ← 1 0

In = 1
1
From State Diagram to
ASM
 From State Diagram to ASM

A 00
S=0 Z=1

0 1
S
A B C
S=1
B 01
Z=0

C 10

0 1
Z
Control unit design
 Control unit design

I. One Flip-flop per State

A flip-flop is used to represent each states, only one of the flip flops
contains a 1 while the rest contains 0.

II. N- Flip-flop per State

The number of flip flops = (𝑙𝑜𝑔2 # state)

 One Flip-Flop per State
The method assign one flip-flop to each state and a simple set of transformation rules to
implement the circuit.

• First, starts with the ASM chart,

• Then replace:
1. A State Box with a flip-flop,
2. A Scalar Decision Box with a demultiplexer with 2 outputs,
3. A Vector Decision Box with a demultiplexer
4. Any Junction with an OR gate, and
5. Any Conditional Output with an AND gate (for a Mealy Machine!!)
 State Box Transformation Rules

Each state box replaced by a Flip-Flop

❑Entry point is connected to the flip-flop input depending the flip-flop type .

❑Exit point is connected to the flip-flop `Q’ output.

Entry

Entry
STATE
STATE
D Q

Exit
Exit
 Scalar Decision Box Transformation Rules

Each Decision box replaced by a Demultiplexer

❑Entry point is connected to "Enable" input od Demux.

❑The Condition is the "Select" input.

❑The Exit points are connected to the Demux outputs.

Entry

DEMUX
Entry EN D0 Exit 0
0 1 D1 Exit 1
X
X S

Exit 0 Exit 1
 Vector Decision Box Transformation Rules

Each Decision box replaced by a Demultiplexer

❑ Entry point is connected to "Enable" input od Demux.

❑ The Condition is the "Select" input.

❑ The Exit points are connected to the Demux outputs.

DEMUX
(Binary Vector Values) (Binary Vector Values)
Entry EN D0 Exit 0
00 (Vector of Input 10 D1
X1 A1 Exit 1
Conditions)
X0 A0 D2 Exit2
01 X1, X0 D3 Exit 3
 Junction Transformation Rules

❑When two or more entry points are joined then use an OR gate to connect these entry

❑The output of the OR gate represented the Exit point

Entry 1 Entry 2
Entry 1 Entry 2

Exit Exit
 Example 1
Design the logic circuit represented by ASM chart shown in Fig. 1
00
A

OR OR
0 1
S

01 D
D
B
Sol.
C
C
10
C

S Z DeMux
0
1
DeMux
Z

D
Fig. 1
C
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