Application Note 27

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Frequently Asked Questions on

DDR Applications
by Rakesh Bhatia

1) What is the DDR clock driver?

The DDR clock driver is a 2.5v driver designed to meet the Cycle to cycle jitter is the difference in the clock’s period
new technology needs of high-speed data transfers. The between 2 consecutive cycles and is expressed in units of
concept is that data is clocked on both the rising as well as +_ ps. This is because it can be either leading or lagging from
the falling edge of the clock. This results in double data rate the ideal output waveform.
(DDR) transfers. Typically, the PI6C857 DDR clock driver is
used in DIMM applications to distribute the system clock
to SDRAMs. t1 t2
t3

2) What specs should be carefully reviewed when Clock

selecting a DDR device?
Since the entire concept of using DDR devices depends on
clocking at the falling edge of the clock, the clock devices Jitter J1 = t2 - t1
used in DDR applications must be carefully selected. Jitter J2 = t3 - t2
Some of the specs that need to be reviewed are the half-
period jitter, the reference to SDRAM skew (Phase shift) in Figure 1. Cycle-to-Cycle Jitter = T2-T1, T3-T2
DIMM applications (and crosspoint delta). Of these, the
half-period jitter has gained increased importance due to the 4) What is the importance of threshold voltage
fact that data is clocked on the falling edge also. and crosspoint voltage?
In a typical DDR system that involves SDRAMs, the
3) What is half-period jitter and cycle to cycle jitter? commands are entered on a single ended clock and data
Half-Period Jitter is the measure of maximum change in a buffered is clocked on both positive and negative edges of
clock’s output transition from its ideal position during one- the clock. It becomes important that the difference between
half period. This type of jitter is considered in double data the threshold of the single ended clock and the threshold
rate (DDR) transfer applications. It is measured as: of the differential clock is within a certain spec. For the
differential clock this threshold is usually the crossover
Tjit (hper) = Thalfperiod – 1/2Fo, where Fo is the point. Comparatively, the threshold for the single ended
frequency of the input signal. Consider a 20Mhz clock and clock is at VDD/2. In an effort to synchronize and correlate
a 25.1ns half cycle, the half-period jitter will be measured as, these 2 threshold voltages, the crossover point spec is
defined as VDD/2 +-200mv.
Tjit(hper) = 25.1 –25 = 0.1ns (or 100ps)
Vdd

Yx, FBOUT
Crosspoint/Threshold
Yx, FBOUT for differential signal
(Vdd/2) +–0.2V
t half period n t n+1
half period
1
fO
1 Vdd
t jit(hper) = t half period n
2*fO
Threshhold for single
Figure 1. Half- Period Jitter. ended signal (Vdd/2)

Figure 3. Crosspoint and Threshold

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5) What does a typical DIMM application include? 8) Between the different technologies or standards avail-
The most common application for double data rate transfers is able such as PC133, DDR1, DDR2 and Rambus, what are
DIMM modules. These typically include a driver and a buffer. the key differences?
For high-end applications such as servers, a switch may also be Overall, most studies conducted on Rambus have proven it to have
used to reduce the load on the data bus. Some of the first industry’s a comparatively lower performance with respect to DDR. Other
DDR products include the PI6C857; a 1:10 clock driver with low skew aspects such as the difficulty to debug, price concerns have driven
and low jitter. The PI74SSTV16857 is a 14-bit registered buffer many different manufacturers to support DDR products. Some of the
designed for DDR memory applications. The PI2BV3867 switch is key differences are highlighted in Table 1.
typically used in x8 DDR memory modules and the PI2BV3877 is
typically used in the x4 DIMMs.

DDR DDR DDR DDR DDR

PI6CV857 DDR DDR DDR DDR
SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM

PI74SSTV
16857

PI2BV3867 PI2BV3867 PI2BV3867 PI2BV3867 PI2BV3867 PI74SSTV PI2BV3867 PI2BV3867 PI2BV3867 PI2BV3867
PI2BV3877 PI2BV3877 PI2BV3877 PI2BV3877 PI2BV3877 16857 PI2BV3877 PI2BV3877 PI2BV3877 PI2BV3877

Figure 4. A Typical DIMM Module Using Pericom Parts.

6) What is the difference between the PI6C850 and Table 1. Comparison Between Different Standards Available
the PI6C857? Parameter PC133 DDR1 DDR2 Rambus
The PI6C850 provides for output enable and functional control by Bus speed 133Mhz 266Mhz 532Mhz 800Mhz
using the I2C control interface. Using this feature, individual output Clock input Single ended Differential Differential Differential
pairs can be tri-stated. This feature is not offered in the PI6C857. 133Mhz 133Mhz 266Mhz 400Mhz
Also, the PI6C850 is typically used in motherboard applications, Vdd 3.3v 2.5v 1.8v 3.3v
whereas the PI6C857 is used in DIMMs. Both the PI6C850 and
PI6C857 are PLL based devices and have almost zero propagation 9) What is the Ref_in to SDRAM skew for PI6C857?
delay. The phase shift measured on a typical DIMM module from a major
manufacturer is approx. 87ps without any feedback capacitor.
7) How is the time delay from Reference clock input to With a feedback capacitor value of 3.3pf, this skew is measured to
SDRAM tuned? be approx. 4.3ps The Jedec spec on this parameter is 200ps.
The spec for time delay from the driver’s reference clock input to
clock at SDRAM is 100ps. This spec is met by Pericom’s PI6C857 Since the skew is measured between the differential Reference
without any external capacitor on a typical DIMM module. input pins of the 857-clock driver and the 120-ohm resistor of
However certain constraints such as trace length may cause this the differential output pins, there is a certain amount of trace length
parameter to exceed spec. Although actual values of the feedback involved. Variation in this trace length can cause the actual measured
capacitor will vary for different applications, a feedback capacitor of Ref_in to SDRAM skew to vary.
3.3pf is tested and recommended for DIMM applications. For more
details on terminations, please refer to Pericom’s application note A more important parameter is the skew between the FBIN and clock
#22, Solution to current high-speed board design. reference pins. The PI6C857 meets the Jedec spec of 120ps on this
parameter; the actual measured value of this skew is approx. 60ps.

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10) How are the PI2BV3877 and PI2BV3867 different considered, i.e. a single-ended signal measurement is done, the
from other Pericom switches? potential error could be as high as 100ps per volt difference and the
The PI2BV3877 and PI2BV3867 switches were specifically designed data gathered will not be accurate. Since the phase error spec from
for DDR applications. Both switches offer very low capacitance and Jedec is close to 100ps (120ps at the time this document is written);
almost no propagation delay. The most common use of these an error of 100ps is outright unacceptable.
switches would be in server applications where multiple cards are
used. These switches provide for protection in hot swap applica- Although there are alternate ways suggested by some vendors,
tions by isolating the data buses. most of these require averaging readings and are therefore not
accurate.
11) How is the phase error measured in a DDR application?
Since the DDR clocks have differential inputs and differential 12) Where can additional data on DDR parts be found?
outputs, it becomes very important to measure the phase error on Pericom offers a complete DDR solution, which includes clock
differential signals. The phase error is measured from the crosspoint drivers, registers and switches. For datasheets or more information
of the input reference signals to the crosspoint of the output signals. on these products, please visit www.pericom.com.
For example , in the Pericom PI6C857 clock driver, the phase error is
measured from CK and CK/ input pins to FBIN and FBIN/ pins. Additional information and samples can be requested from the web
Therefore, all 4 probes of a typical oscilloscope are used. Consider site or by contacting Pericom marketing group:
Figure 5 below :
Sergis Mushell for clock products at 408-435-0800 xtn 301,
and Refugio Jones at 408-435-0800 xtn 266 for switches and buffers.

Jedec specs for DDR clocks can be found at www.jedec.org

References:

1. Tisani, Mohamad, “Solution to current High-Speed Board

Design.” Pericom Semiconductor Corp., AN22, 2000.
2. http://www.jedec.org/
3. http://www.inqst.com/
4. Yen, Mike, “Design guides of PC133/100 registered SDRAM
module.” Pericom Semiconductor Corp., AN20, 1999.

Figure 5: Measurement of phase error for

typical DDR application

Here, channel 1 and 2 represents the differential input reference

signal. The vertical scale is 1.00v/div and the horizontal scale is
100ps. If the crosspoints of both input and output signals are not

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