COMPUTER SYSTEM ARCHITECTURE

Dr Ganesan P, Professor / ECE

UNIT III: Basic Computer Organization and Design: Instruction codes,

computer registers, computer instructions, instruction cycle, timing and
control, memory reference instructions, input, output and interrupt.
Central Processing Unit: stack organization, instruction formats, addressing
modes, data transfer and manipulation, program control, reduced instruction set c
omputer (RISC).

Instruction Codes:

• The general-purpose digital computer is capable of executing various

microoperations and, in addition, can be instructed as to what specific
sequence of operations it must perform.
• The user of a computer can control the process by means of a program.
• Program:set of instructions that specify the operations, operands, and the
sequence by which processing has to occur.
• Instruction:a binary code that specifies a sequence of micro-operations for
the computer.
• Instruction Cycle:The computer reads each instruction from memory and
places it in a control register. The control then interprets the binary code of
the instruction and proceeds to execute it by issuing a sequence of micro-
operations.(Fetch –Decode-Execute)
• Instruction Code: group of bits that instruct the computer to perform specific
operation.
• Instruction code is usually divided into two parts: Opcode and
address(operand)
Operation Code (opcode):

group of bits that define the operation

Eg: add, subtract, multiply, shift, complement.

Address (operand):

specifies the location of operands (registers or memory words)

Memory words are specified by their address

Stored Program Organization:

The ability to store and execute instructions is the most important property of a
general-purpose computer. That type of stored program concept is called stored
program organization.

The simplest way to organize a computer is to have one processor register and
an instruction code format with two parts. The first part specifies the operation to be
performed and the second specifies an address.

The below figure shows the stored program organization

Instructions (programs) are stored in one program memory and data in data memory.

For a memory unit with 4096 words we need 12 bits to specify an address since
12
2 = 4096.
 If we store each instruction code in one 16-bit memory word, we have four bits for
the operation code (abbreviated opcode) and 12 bits to specify the address of an
operand.

Accumulator (AC):The accumulator is an 8-bit register that is a part of

arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform
arithmetic and logical operations. The result of an operation is stored in the
accumulator. The accumulator is also identified as register A.

Direct and Indirect Address

When the second part specifies the address of an operand, the instruction is
said to have a direct address.

When second part of the instruction designate an address of a memory word in which
the address of the operand is found such instruction have indirect address.

One bit of the instruction code can be used to distinguish between a direct and an
indirect address.

The instruction code format shown in Fig. It consists of a 3-bit operation code, a 12-
bit address, and an indirect address mode bit designated by I. The mode bit is 0 for
a direct address and 1 for an indirect address.

 A direct address instruction is shown in Fig. (b). It is placed in address 22 in

memory. The I bit is 0, so the instruction is recognized as a direct address
instruction. The opcode specifies an ADD instruction, and the address part is the
binary equivalent of 457. The control finds the operand in memory at address
457 and adds it to the content of AC.

 An indirect address instruction is shown in Fig. (c). The I bit is 1, so the

instruction is recognized as a indirect address instruction. Therefore, it is
recognized as an indirect address instruction. The address part is the binary
equivalent of 300. The control goes to address 300 to find the address of the
operand. The address of the operand in this case is 1350. The operand found in
address 1350 is then added to the content of AC.
Computer Registers
What is the need for computer registers?

The need of the registers in computer for

Instruction sequencing needs a counter to calculate the address of the next

instruction after execution of the current instruction is completed (PC).

Needs processor registers for manipulating data (AC and TR) and a register
for holding a memory address (AR).

These requirements dictate the register configuration shown in Figure. The registers are
also listed in Table together with a brief description of their function and the number of
bits that they contain.
 The data register (DR) holds the operand read from memory.
The accumulator (AC) register is a general purpose processing register.
The instruction read from memory is placed in the instruction register (IR).
The temporary register (TR) is used for holding temporary data during the processing.
The memory address register (AR) has 12 bits since this is the width of a memory address.
The program counter (PC) also has 12 bits and it holds the address of the next instruction to
be read from memory after the current instruction is executed.
Two registers are used for input and output.
• The input register (INPR) receives an 8-bit character from an input device.
• The output register (OUTR) holds an 8-bit character for an output device.
Computer Instructions:

The basic computer has three instruction code formats, as shown in Fig. Each
format has 16 bits.

The operation code (opcode) part of the instruction contains three bits and the
meaning of the remaining 13 bits depends on the operation code encountered.

A memory-reference instruction uses 12 bits to specify an address and one bit to

specify the addressing mode I. I is equal to 0 for direct address and to 1 for indirect
address.

The register-reference instructions are recognized by the operation code 1.11 with a 0
in the leftmost bit (bit 15) of the instruction. A register-reference instruction specifies an
operation on the AC register. So an operand from memory is not needed. Therefore, the
other 12 bits are used to specify the operation to be executed.

An input—output instruction does not need a reference to memory and is recognized

by the operation code 111 with a 1 in the leftmost bit of the instruction. The remaining
12 bits are used to specify the type of input—output operation.

The instructions for the computer are listed in Table


The symbol designation is a three-letter word and represents an abbreviation
intended for programmers and users.

The hexadecimal code is equal to the equivalent hexadecimal number of the binary
code used for the instruction.
Instruction Set Completeness:
A computer should have a set of instructions so that the user can construct machine
language programs to evaluate any function.
The set of instructions are said to be complete if the computer includes a sufficient
number of instructions in each of the following categories:
o Arithmetic, logical, and shift instructions
o Data Instructions (for moving information to and from memory and processor
registers)
o Program control or Brach
o Input and output instructions

Timing and Control:

The timing for all registers in the basic computer is controlled by a master
clock generator.

The clock pulses are applied to all flip-flops and registers in the system,
including the flip-flops and registers in the control unit.

The control signals are generated in the control unit and provide control
inputs for the multiplexers in the common bus, control inputs in processor
registers, and microoperations for the accumulator.

There are two major types of control organization:

o Hardwired control
o Microprogrammed control

The differences between hardwired and microprogrammed control are

Hardwired control Microprogrammed control
The control logic is implemented with The control information is stored in a
gates, flip-flops, decoders, and other control memory. The control memory
digital circuits. is programmed to initiate the required
sequence of microoperations.
The advantage that it can be optimized Compared with the hardwired control
to produce a fast mode of operation. operation is slow.
Requires changes in the wiring among Required changes or modifications can
the various components if the design be done by updating the
has to be modified or changed. microprogramin control memory.
The block diagram of the hardwired control unit is shown in Fig.

It consists of two decoders, a sequence counter, and a number of control logic
gates.

An instruction read from memory is placed in the instruction register (IR). It is
divided into three parts: The I bit, the operation code, and bits 0 through 11.

The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder. The
eight outputs of the decoder are designated by the symbols D0 through D7.

Bit 15 of the instruction is transferred to a flip-flop designated by the symbol I.

Bits 0 through 11 are applied to the control logic gates.

The 4-bit sequence counter can count in binary from 0 through 15.


The outputs of the counter are decoded into 16 timing signals T0 through
T15.
The sequence counter SC can be incremented or cleared synchronously.

The counter is incremented to provide the sequence of timing signals out of

the 4 x 16 decoder.

The timing diagram of Fig. shows the time relationship of the control signals.

The sequence counter SC responds to the positive transition of the clock.

Initially, the CLR input of SC is active. The first positive transition of the
clock clears SC to 0, which in turn activates the timing signal T0 out of the
decoder. T0 is active during one clock cycle.

SC is incremented with every positive clock transition, unless its CLR input is
active.

This produces the sequence of timing signals T0, T1, T2, T3, T4and so on, as
shown in the diagram.
Thelast three waveforms in above Fig. show how SC is cleared when D3T4 =
1.

Output D3 from the operation decoder becomes active at the end of timing
signal T2.

When timing signal T4 becomes active, the output of the AND gate that
implements the control function D3T4 becomes active.

This signal is applied to the CLR input of SC. On the next positive clock
transition (the one marked T4 in the diagram) the counter is cleared to 0.

This causes the timing signal T0 to become active instead of T5 that would
have been active if SC were incremented instead of cleared.


Instruction Cycle:

A program residing in the memory unit of the computer consists of a

sequence of instructions.

The program is executed in the computer by going through a cycle for each
instruction.

Each instruction cycle in turn is subdivided into a sequence of sub cycles or

phases.

The instruction cycle (also known as the fetch–decode–execute cycle,

or simply the fetch-execute cycle) is the cycle that the central
processing unit (CPU) follows from boot-up until the computer has
shut down in order to process instructions. It is composed of three main
stages: the fetch stage, the decode stage, and the execute stage.

In the basic computer each instruction cycle consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect
address.
 4. Execute the instruction.

Upon the completion of step 4, the control goes back to step 1 to fetch,
decode, and execute the next instruction.

1. Fetch Stage: The next instruction is fetched from the memory address that is
currently stored in the program counter and stored into the instruction register. At
the end of the fetch operation, the PC points to the next instruction that will be
read at the next cycle.
2. Decode Stage: During this stage, the encoded instruction presented in the
instruction register is interpreted by the decoder.
o Read the effective address: In the case of a memory instruction (direct or
indirect), the execution phase will be during the next clock pulse. If the
instruction has an indirect address, the effective address is read from main
memory, and any required data is fetched from main memory to be
processed and then placed into data registers (clock pulse: T3). If the
instruction is direct, nothing is done during this clock pulse. If this is an I/O
instruction or a register instruction, the operation is performed during the
clock pulse.
3. Execute Stage: The control unit of the CPU passes the decoded information as
a sequence of control signals to the relevant functional units of the CPU to
perform the actions required by the instruction, such as reading values from
registers, passing them to the ALU to perform mathematical or logic functions on
them, and writing the result back to a register.

Fetch and Decode:

Initially, the program counter PC is loaded with the address of the first
instruction in the program.
The sequence counter SC is cleared to 0, providing a decoded timing signal
T0.
The microoperations for the fetch and decode phases can be specified by the
following register transfer statements.
T0: AR PC
T1: IR M[AR], PC PC + 1
T2: D0 , . . . , D7 Decode IR(12-14),AR IR(0-11),I IR(15)

Determine the Type of Instruction:

The flowchart of fig shows the initial configurations for the instruction cycle
and also how the control determines the instruction cycle type after the
decoding.
Decoder output D7 is equal to 1 if the operation code is equal to binary 111.
If D7=1, the instruction must be a register-reference or input-output type.
If D7 = 0, the operation code must be one of the other seven values 000
through 110, specifying a memory-reference instruction. Control then inspects
the value of the first bit of the instruction, which is now available in flip-flop I.
If D7 = 0 and I = 1, indicates a memory-reference instruction with an indirect
address. So it is then necessary to read the effective address from memory.
If D7 = 0 and I = 0, indicates a memory-reference instruction with a direct
address.
If D7 = 1 and I = 0, indicates a register-reference instruction.
If D7 = 01and I = 1, indicates an input-output instruction.
The three instruction types are subdivided into four separate paths.
The selected operation is activated with the clock transition associated with
timing signal T3.

Register-Reference Instructions:
Register-reference instructions are recognized by the control when D7 = 1
and I=0.
These instructions use bits 0 through 11 of the instruction code to specify
one of 12 instructions. These 12 bits are available in IR (0-11).
The control functions and microoperations for the register-reference
instructions are listed in Table.
These instructions are executed with the clock transition associated with
timing variable T3.
Control function needs the Boolean relation D7I’T3, which we designate for
convenience by the symbol r.
By assigning the symbol Bi to bit i of IR, all control functions can be simply
denoted by rBi.
The first seven register-reference instructions perform clear, complement,
circular shift, and increment microoperations on the AC or E registers.
The next four instructions cause a skip of the next instruction in sequence
when a stated condition is satisfied. The skipping of the instruction is achieved by
incrementing PC once again.
The condition control statements must be recognized as part of the control
conditions.
The AC is positive when the sign bit in AC(15) = 0; it is negative when AC(15) =
1. The content of AC is zero (AC = 0) if all the flip-flops of the register are zero.
The HLT instruction clears a start-stop flip-flop S and stops the sequence
counter from counting.
Memory-Reference Instructions:
Table lists the seven memory-reference instructions.
The decoded output Di for i = 0, 1, 2, 3, 4, 5, and 6 from the operation decoder that
belongs to each instruction is included in the table.
The execution of the memory-reference instructions starts with timing signal T4.


AND to AC:
This is an instruction that performs the AND logic operation on pairs of bits
in AC and the memory word specified by the effective address.
The result of the operation is transferred to AC.
The microoperations that execute this instruction are:

ADD to AC:
This instruction adds the content of the memory word specified by the
effective address to the value of AC.
The sum is transferred into AC and the output carry Cout is transferred to the
E (extended accumulator) flip-flop.
The microoperations needed to execute this instruction are

LDA: Load to AC
This instruction transfers the memory word specified by the effective address
to AC.
The microoperations needed to execute this instruction are

STA: Store AC
This instruction stores the content of AC into the memory word specified by
the effective address.

BUN: Branch Unconditionally

This instruction transfers the program to the instruction specified by the
effective address.
The BUN instruction allows the programmer to specify an instruction out of
sequence and we say that the program branches (or jumps) unconditionally.
The instruction is executed with one microoperation:
BSA: Branch and Save Return Address
This instruction is useful for branching to a portion of the program called a
subroutine or procedure.
When executed, the BSA instruction stores the address of the next instruction
in sequence (which is available in PC) into a memory location specified by the
effective address.
The BSA instruction must be executed with a sequence of two
microoperations:

ISZ: Increment and Skip if Zero

This instruction increment the word specified by the effective address, and if
the incremented value is equal to 0, PC is incremented by 1 to skip the next
instruction in the program.
Since it is not possible to increment a word inside the memory, it is necessary
to read the word into DR, increment DR, and store the word back into memory.
This is done with the following sequence of microoperations:

Input-Output and Interrupt:

Instructions and data stored in memory must come from some input device.
Computational results must be transmitted to the user through some output
device.
To demonstrate the most basic requirements for input and output
communication, we will use as an illustration a terminal unit with a keyboard and
printer.

Input-Output Configuration:
The terminal sends and receives serial information.
Each quantity of information has eight bits of an alphanumeric code.
The serial information from the keyboard is shifted into the input register
INPR.
The serial information for the printer is stored in the output register OUTR.
These two registers communicate with a communication interface serially
and with the AC in parallel.
The input—output configuration is shown in Fig.

The input register INPR consists of eight bits and holds alphanumeric input
information.
The 1-bit input flag FGI is a control flip-flop.
The flag bit is set to 1 when new information is available in the input device
and is cleared to 0 when the information is accepted by the computer.
The output register OUTR works similarly but the direction of information
flow is reversed.
Initially, the output flag FGO is set to 1.
The computer checks the flag bit; if it is 1, the information from AC is
transferred in parallel to OUTR and FGO is cleared to 0.
The output device accepts the coded information, prints the corresponding
character, and when the operation is completed, it sets FGO to 1.

Input-Output Instructions:
Input and output instructions are needed for transferring information to and
from AC register, for checking the flag bits, and for controlling the interrupt
facility.
Input-output instructions have an operation code 1111 and are recognized by
the control when D7 = 1 and I = 1.
The remaining bits of the instruction specify the particular operation
The control functions and microoperations for the input-output instructions
are listed in Table


These instructions are executed with the clock transition associated with
timing signal T3.
Each control function needs a Boolean relation D7IT3, which we designate for
convenience by the symbol p.
The control function is distinguished by one of the bits in IR (6-11).
By assigning the symbol Bi to bit i of IR, all control functions can be denoted
by pBi for i = 6 though 11.
The sequence counter SC is cleared to 0 when p = D7IT3 = 1.
The last two instructions set and clear an interrupt enable flip-flop IEN.

Program Interrupt:
• Interrupt is an event that temporarily suspends the main program,
passes the control to a special code section, executes the event-related
function and resumes the main program flow where it had left off.
• Program interrupt refers to the transfer of program control from a
currently running program to another service program as a result of an
external or internal generated request.
The computer keeps checking the flag bit, and when it finds it set, it initiates
an information transfer.
While the computer is running a program, it does not check the flags.
When a flag is set, the computer is momentarily interrupted from the current
program.
The computer deviates momentarily from what it is doing to perform of the
input or output transfer.
It then returns to the current program to continue what it was doing before
the interrupt.
The interrupt enable flip-flop IEN can be set and cleared with two
instructions.
o When IEN is cleared to 0 (with the IOF instruction), the flags cannot
interrupt the computer.
o When IEN is set to (with the ION instruction), the computer can be
interrupted.
The way that the interrupt is handled by the computer can be explained by
means of the flowchart of Fig.
An interrupt flip-flop R is included in the computer. When R = 0, the
computer goes through an instruction cycle.
During the execute phase of the instruction cycle IEN is checked by the
control.
If it is 0, it indicates that the programmer does not want to use the
interrupt,so control continues with the next instruction cycle.
If IEN is 1, control checks the flag bits. If both flags are 0, it indicates that
neither the input nor the output registers are ready for transfer of information. In
this case, control continues with the next instruction cycle.
If either flag is set to 1 while 1EN = 1, flip-flop R is set to 1. At the end of the
execute phase, control checks the value of R, and if it is equal to 1, it goes to an
interrupt cycle instead of an instruction cycle.

Types of interrupts:
There are three major types of interrupts that cause a break in the normal
execution of a program.
They can be classified as
o External interrupts:
 These come from input—output (I/O) devices, from a timing device, from a
circuit monitoring the power supply, or from any other external source.
 Ex: I/O device requesting transfer of data, I/O device finished transfer of data,
elapsed time of an event, or power failure.
o Internal interrupts:
 These arise from illegal or erroneous use of an instruction or data.
 Internal interrupts are also called traps.
 Ex: interrupts caused by internal error conditions are register overflow, attempt
to divide by zero, an invalid operation code, stack overflow, and protection
violation.
Internal and external interrupts are initiated form signals that occur in
hardware of CPU.
o Software interrupts
 A software interrupt is initiated by executing an instruction.
 Software interrupt is a special call instruction that behaves like an interrupt
rather than a subroutine call.
CENTRAL PROCESSING UNIT
The main part of the computer that performs the bulk of data-processing
operations is called the central processing unit and is referred to as the CPU.
The CPU is made up of three major parts, as shown in Fig.

The register set stores intermediate data used during the execution of the
instructions.
The arithmetic logic unit (ALU) performs the required microoperations for
executing the instructions.
The control unit supervises the transfer of information among the registers
and instructs the ALU as to which operation to perform.

Stack Organization:
A stack or last-in first-out (LIFO) is useful feature that is included in the CPU
of most computers.
Stack is a storage device that stores information in such a manner that the
item stored last is the first item retrieved.
In the computer stack is a memory unit with an address register that can
count the address only.
The register that holds the address for the stack is called a stack pointer
(SP). It always points at the top item in the stack.
The two operations that are performed on stack are the insertion and
deletion.
• The operation of insertion is called PUSH.
• The operation of deletion is called POP.
These operations are simulated by incrementing and decrementing the stack
pointer register (SP).

Register Stack:
A stack can be placed in a portion of a large memory or it can be organized as
a collection of a finite number of memory words or registers.
The below figure shows the organization of a 64-word register stack.

The stack pointer register SP contains a binary number whose value is equal
to the address of the word is currently on top of the stack. Three items are placed
in the stack: A, B, C, in that order.
In above figure C is on top of the stack so that the content of SP is 3.
For removing the top item, the stack is popped by reading the memory word
at address 3 and decrementing the content of stack SP.
Now the top of the stack is B, so that the content of SP is 2.
Similarly for inserting the new item, the stack is pushed by incrementing SP
and writing a word in the next-higher location in the stack.
In a 64-word stack, the stack pointer contains 6 bits because 26 = 64.
Since SP has only six bits, it cannot exceed a number greater than 63 (111111
in binary).
When 63 is incremented by 1, the result is 0 since 111111 + 1. = 1000000 in
binary, but SP can accommodate only the six least significant bits.
Then the one-bit register FULL is set to 1, when the stack is full.
Similarly when 000000 is decremented by 1, the result is 111111, and then
the one-bit register EMTY is set 1 when the stack is empty of items.
DR is the data register that holds the binary data to be written into or read
out of the stack.

PUSH:
The push operation is implemented with the following sequence of
microoperations:


The stack pointer is incremented so that it points to the address of next-
higher word.
A memory write operation inserts the word from DR the top of the stack.
If SP reaches 0, the stack is full of items, so FULL is to 1.
This condition is reached if the top item prior to the last push way location 63
and, after incrementing SP, the last item is stored in location 0.
Once an item is stored in location 0, there are no more empty registers in the
stack, so the EMTY is cleared to 0.

POP:
A new item is deleted from the stack if the stack is not empty (if EMTY = 0).
The pop operation consists of the following sequence of min operations:

Memory Stack:
In the above discussion a stack can exist as a stand-alone unit. But in the CPU
implementation of a stack is done by assigning a portion of memory to a stack
operation and using a processor register as stack pointer.
The below figure shows a portion computer memory partitioned into three
segments: program, data, and stack.
 

The program counter PC points at the address of the next instruction in
program.
The address register AR points at an array of data.
The stack pointer SP points at the top of the stack.
 The three registers are connected to a common address bus, and either one
can provide an address for memory.
o PC is used during the fetch phase to read an instruction.
o AR is used during the execution phase to read an operand.
o SP is used to push or pop items into or from stack.
As shown in above Fig. the initial value of SP is 4001 and the stack grows with
decreasing addresses.
Thus the first item stored in the stack is at address 4000, the second item is
stored at address 3999, and the last address that can be used for the stack is
3000.
A new item is inserted with the push operation as follows:

The stack pointer is decremented so that it points at the address of the next
word.
A memory write operation inserts the word from DR into the top of stack. A
new item is deleted with a pop operation as follows:

The top item is read from the stack into DR. The stack pointer is then
decremented to point at the next item in the stack.
Most computers do not provide hardware to check for stack overflow (full
stack) or underflow (empty stack). The stack limits can be checked by using
processor registers:
• one to hold the upper limit (3000 in this case)
• other to hold the lower limit (4001 in this case).
After a push operation, SP compared with the upper-limit register and after a
pop operation, SP is a compared with the lower-limit register.
Instruction Formats:
The format of an instruction is usually depicted in a rectangular box
symbolizing the bits of the instruction as they appear in memory words or in a
control register.
The bits of the instruction are divided into groups called fields.
The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to be perform
2. An address field that designates a memory address or a processor
register.
3. A mode field that specifies the way the operand or the effective address
is determined.
Most computers fall into one of three types of CPU organizations:
1. Single accumulator organization.
2. General register organization.
3. Stack organization.

Single Accumulator Organization:

In an accumulator type organization all the operations are performed with
an implied accumulator register.
The instruction format in this type of computer uses one address field.
For example, the instruction that specifies an arithmetic addition defined by
an assembly language instruction as
ADD X
Where X is the address of the operand. The ADD instruction in this case
results in the operation
AC AC +M[X]. AC is the accumulator register and M[X] symbolizes the memory
word located at address X.

General register organization:

The instruction format in this type of computer needs three register address
fields.
Thus the instruction for an arithmetic addition may be written in an assembly
language as
ADD R1, R2, R3
to denote the operation R1R2 + R3
Stack organization:
The stack-organized CPU has PUSH and POP instructions which require an
address field.
Thus the instruction PUSH X will push the word at address X to the top of the
stack.
The stack pointer is updated automatically.
The instruction ADD in a stack computer consists of an operation code only
with no address field.
This operation has the effect of popping the two top numbers from the stack,
adding the numbers, and pushing the sum into the stack.

• Instructions are categorized into different formats with respect to the

operand fields in the instructions.
1.Three Address Instructions
2.Two Address Instruction
3.One Address Instruction
4.Zero Address Instruction
5.RISC Instructions

Three Address Instructions:

Three-address instruction formats can use each address field to specify either
a processor register or a memory operand.
The program assembly language that evaluates X = (A+B) * (C+D) is shown
below, together with comments that explain the register transfer operation of
each instruction.

The symbol M [A] denotes the operand at memory address symbolized by A.

Two Address Instructions:

Two-address instructions formats use each address field can specify either a
processor register or memory word.
The program to evaluate X = (A+B) * (C+D) is as follows
The MOV instruction moves or transfers the operands to and from memory
and processor registers.

One Address Instructions:

One-address instructions use an implied accumulator (AC) register for all
data manipulation.
For multiplication and division there is a need for a second register. But for
the basic discussion we will neglect the second register and assume that the AC
contains the result of all operations.
The program to evaluate X=(A+B) * (C+D) is

All operations are done between the AC register and a memory operand.
T is the address of a temporary memory location required for storing the
intermediate result.

Zero Address Instructions:

A stack-organized computer does not use an address field for the
instructions ADD and MUL.
The PUSH and POP instructions, however, need an address field to specify the
operand that communicates with the stack.
The following program shows how X = (A+B) * (C+D) will be written for a
stack-organized computer. (TOS stands for top of stack).
The name "zero-address” is given to this type of computer because of the
absence of an address field in the computational instructions.

RISC Instructions:
The instruction set of a typical RISC processor is use only load and store
instructions for communicating between memory and CPU.
All other instructions are executed within the registers of CPU without
referring to memory.
LOAD and STORE instructions that have one memory and one register
address, and computational type instructions that have three addresses with all
three specifying processor registers.
The following is a program to evaluate X=(A+B)*(C+D)

The load instructions transfer the operands from memory to CPU register.
The add and multiply operations are executed with data in the register
without accessing memory.
The result of the computations is then stored memory with a store in
instruction.
Addressing Modes
 The term addressing modes refers to the way in which the operand (data) of
an instruction is specified. The addressing mode specifies a rule for
interpreting or modifying the address field of the instruction before the
operand is actually executed.
Computers use addressing mode techniques for the purpose of
accommodating one or both of the following provisions:
o To give programming versatility to the user by providing such facilities
as pointers to memory, counters for loop control, indexing of data, and
program relocation.
o To reduce the number of bits in the addressing field of the instruction
Most addressing modes modify the address field of the instruction; there are
two modes that need no address field at all. These are implied and immediate
modes.

Implied Mode:
In this mode the operands are specified implicitly in the definition of the
instruction.
For example, the instruction "complement accumulator" is an implied-mode
instruction because the operand in the accumulator register is implied in the
definition of the instruction.
All register reference instructions that use an accumulator are implied mode
instructions.

Immediate Mode:
In an immediate-mode instruction has an operand rather than an address
field.
Immediate-mode instructions are useful for initializing registers to a constant
value.
In this, an immediate number is a part of the instruction.
Register Mode:
In this mode the operands are in registers that reside within the CPU.
The particular register is selected from a register field in the instruction.

Register Indirect Mode:

In this mode the instruction specifies a register in CPU whose contents give
the address of the operand in memory.
In other words, the selected register contains the address of the operand
rather than the operand itself.

Direct Address Mode:

In this mode the effective address is equal to the address part of the
instruction.
The operand resides in memory and its address is given directly by the
address field of the instruction.

Indirect Address Mode:

In this mode the address field of the instruction gives the address where the
effective address is stored in memory.
The effective address in these modes is obtained from the following
computation:
Effective address =address part of instruction + content of CPU register
The CPU register used in the computation may be the program counter, an
index register, or a base register.

Relative Address Mode:

In this mode the content of the program counter is added to the address part
of the instruction in order to obtain the effective address.
 Relative addressing is often used with branch-type instructions when the
branch address is in the area surrounding the instruction word itself.

Indexed Addressing Mode:

In this mode the content of an index register is added to the address part of
the instruction to obtain the effective address.
Effective address = address part of instruction + content of index
register
An index register is a special CPU register that contains an index value.
Base Register Addressing Mode:
In this mode the content of a base register is added to the address part of the
instruction to obtain the effective address.
Effective address=address part of instruction + content of base register
This is similar to the indexed addressing mode except that the register is now
called a base register instead of an index register.

Data Transfer and Manipulation:

Most computer instructions can be classified into three categories:
1. Data transfer instructions 2. Data manipulation instructions 3. Program
control instructions
Data Transfer Instructions:
Data transfer instructions move data from one place in the computer to
another without changing the data content.
The most common transfers are between memory and processor registers,
between processor registers and input or output, and between the processor
registers themselves.
Table gives a list of eight data transfer instructions used in many computers.



The load instruction has been used mostly to designate a transfer from
memory to a processor register, usually an accumulator.
The store instruction designates a transfer from a processor register into
memory.
The move instruction has been used in computers with multiple CPU registers
to designate a transfer from one register to another and also between CPU
registers and memory or between two memory words.
The exchange instruction swaps information between two registers or a
register and a memory word.
The input and output instructions transfer data among processor registers
and input or output terminals.
The push and pop instructions transfer data between processor registers and
a memory stack.

Data Manipulation Instructions:

Data manipulation instructions perform operations on data and provide the
computational capabilities for the computer.
The data manipulation instructions in a typical computer are usually divided
into three basic types:
1. Arithmetic instructions
2. Logical and bit manipulation instructions
3. Shift instructions

1. Arithmetic instructions
The four basic arithmetic operations are addition, subtraction, multiplication
and division.
Most computers provide instructions for all four operations.
A list of typical arithmetic instructions is given in Table.

The increment instruction adds 1 to the value stored in a register or memory

word.
The decrement instruction subtracts 1 from a value stored in a register or
memory word.
The add, subtract, multiply, and divide instructions may be use different
types of data.
2. Logical and bit manipulation instructions
Logical instructions perform binary operations on strings of bits store,
registers.
They are useful for manipulating individual bits or a group of that represent
binary-coded information.
Some typical logical and bit manipulation instructions are listed in Table.

The clear instruction causes the specified operand to be replaced by 0’s.

The complement instruction produces the 1's complement by inverting all
bits of the operand.
The AND, OR, and XOR instructions produce the corresponding logical
operations on individual bits of the operands.
The logical instructions can also be used to performing bit manipulation
operations.
Bit manipulations instructions are included in above table perform the
operations on individual bits such as a carry can be cleared, set, or
complemented. Another example is a flip-flop that controls the interrupt facility
and is either enabled or disabled by means of bit manipulation instructions.

Shift Instructions:
Shifts are operations in which the bits of a word are moved to the left or
right.
The bit shifted in at the end of the word determines the type of shift used.
Shift instructions may specify logical shifts, arithmetic shifts, or rotate-type
operations.
In either case the shift may be to the right or to the left.
Table lists four types of shift instructions.
SHLA and SHL

SHR

SHRA
Rotate

Program Control:
Program control instructions specify conditions for altering the content of the
program counter.
The change in value of the program counter as a result of the execution of a
program control instruction causes a break in the sequence of instruction
execution.
This instruction provides control over the flow of program execution and a
capability for branching to different program segments.
Some typical program control instructions are listed in Table .

Branch and jump instructions may be conditional or unconditional.

An unconditional branch instruction causes a branch to the specified address
without any conditions.
The conditional branch instruction specifies a condition such as branch if
positive or branch if zero. The following table illustrates the conditional
branch instructions

The skip instruction does not need an address field and is therefore a zero-
address instruction.
A conditional skip instruction will skip the next instruction if the condition is
met. This is accomplished by incrementing program counter.
The call and return instructions are used in conjunction with subroutines.
The compare instruction forms a subtraction between two operands, but the
result of the operation not retained. However, certain status bit conditions are set
as a result of operation.
Similarly, the test instruction performs the logical AND of two operands and
updates certain status bits without retaining the result or changing the operands.
The rotate instructions produce a circular shift. Bits shifted out at one of the
word are not lost as in a logical shift but are circulated back into the other end.
The rotate through carry instruction treats a carry bit as an extension of the
register whose word is being rotated.
Thus a rotate-left through carry instruction transfers the carry bit into the
rightmost bit position of the register, transfers the leftmost bit position into the
carry, and at the same time, shift the entire register to the left.

3. Shift Instructions:
Shifts are operations in which the bits of a word are moved to the left or
right.
The bit shifted in at the end of the word determines the type of shift used.
Shift instructions may specify logical shifts, arithmetic shifts, or rotate-type
operations.
In either case the shift may be to the right or to the left.
Table 8-9 lists four types of shift instructions.

The logical shift inset to the end bit position.

The end position is the leftmost bit position for shift rights the rightmost bit
position for the shift left.
Arithmetic shifts usually conform to the rules for signed-2's complement
numbers.
The arithmetic shift-right instruction must preserve the sign bit in the
leftmost position.
The sign bit is shifted to the right together with the rest of the number, but
the sign bit itself remains unchanged.
This is a shift-right operation with the end bit remaining the same.
The arithmetic shift-left instruction inserts 0 to the end position and is
identical to the logical shift-instruction.
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The rotate instructions produce a circular shift. Bits shifted out at one of the
word are not lost as in a logical shift but are circulated back into the other end.
The rotate through carry instruction treats a carry bit as an extension of the
register whose word is being rotated.
Thus a rotate-left through carry instruction transfers the carry bit into the
rightmost bit position of the register, transfers the leftmost bit position into the
carry, and at the same time, shift the entire register to the left.

Reduced Instruction Set Computer:

A computer with large number instructions is classified as a complex
instruction set computer, abbreviated as CISC.
The computer which having the fewer instructions is classified as a reduced
instruction set computer, abbreviated as RISC.

CISC Architecture

 CISC architectures directly use the memory, instead of a register file. The
above figure shows the architecture of CISC with micro programmed control
and cache memory.
 This architecture uses cache memory for holding both data and instructions.
Thus, they share the same path for both instructions and data.
 CISC has instructions with variable length format. Thus, the number of clock
cycles required to execute the instructions may be varied.
 Instructions in CISC are executed by micro program which has sequence of
microinstructions.
Examples of CISC processor
1. IBM 370/168 2. Intel 80486 3. VAX 11/780

CISC Characteristics:
A large number of instructions--typically from 100 to 250 instructions.
Some instructions that perform specialized tasks and are used
infrequently.
A large variety of addressing modes—typically from 5 to 20 differ modes.
Variable-length instruction formats
Instructions that manipulate operands in memory

RISC (Reduced Instruction Set Computer) Architecture

 Although CISC reduces usage of memory and compiler, it requires more
complex hardware to implement the complex instructions.
 In RISC architecture, the instruction set of processor is simplified to reduce
the execution time. It uses small and highly optimized set of instructions
which are generally register to register operations.
 The speed of the execution is increased by using smaller number of
instructions .This uses pipeline technique for execution of any instruction.
 The figure shown below is the architecture of RISC processor, which uses
separate instruction and data caches and their access paths also different.
There is one instruction per machine cycle in RISC processor.

 The pipelining technique allows the processor to work on different steps of

instruction like fetch, decode and execute instructions at the same time.
Below is image showing execution of instructions in pipelining technique.
  Generally, execution of second instruction is started, only after the
completion of the first instruction. But in pipeline technique, each
instruction is executed in number of stages simultaneously.
 When the first stage of first instruction is completed, next instruction is
enters into the fist stage. This process continuous until all the instructions
are executed.

RISC Characteristics:
Relatively few instructions
Relatively few addressing modes
Memory access limited to load and store instructions
All operations done within the registers of the CPU
Fixed-length, easily decoded instruction format
Single-cycle instruction execution
Hardwired rather than microprogrammed control
A relatively large number of registers in the processor unit
Efficient instruction pipeline
Examples of RISC processors
This architecture include alpha, AVR, ARM, PIC, PA-RISC, and power architecture.
Advantages of RISC Architecture
• The performance of RISC processors is often two to four times than that of
CISC processors because of simplified instruction set.
• This architecture uses less chip space due to reduced instruction set.
• The per-chip cost is reduced by this architecture that uses smaller chips
consisting of more components on a single silicon wafer.
• RISC processors can be designed more quickly than CISC processors due to
its simple architecture.
• The execution of instructions in RISC processors is high due to the use of
many registers for holding and passing the instructions as compared to CISC
processors.

Best Wishes

Dr Ganesan P, Professor / ECE

Vidya Jyothi Institute of Technology