INSTRUCTION SET

Instruction Set
 There are over a hundred instructions in the instruction set
for the 8086 CPU; there are also instructions designed
especially for the more advanced processors.
 8086 supports 8 types of instructions:
 Data Transfer Instructions
 Arithmetic Instructions
 Logical Instructions
 String manipulation Instructions
 Program Execution Transfer Instructions (Branch &
Loop Instructions)
 Process Control Instructions
 Iteration Control Instructions
 Interrupt Instructions
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 DAA
 The DAA (decimal adjust after addition) instruction converts the binary
result of an ADD or ADC operation to packed decimal format.
 The value to be adjusted must be in AL.
 If lower nibble of AL > 9 or AF = 1 then : AL=AL+6 & AF = 1
 else if upper nibble of AL > 9 or CF = 1 then : AL = AL + 60h & CF = 1

 For example: Let AL = 59 BCD, and BL = 35 BCD, result should be 94.

 ADD AL, BL AL = 8EH; lower nibble > 9, add 06H to AL
 DAA AL = 94 BCD, CF = 0

Example-2:
 Let AL = 88 BCD, and BL = 49 BCD
 ADD AL, BL AL = D1H; AF = 1, add 06H to AL
 DAA AL = D7H; upper nibble > 9, add 60H to AL
AL = 37 BCD, CF = 1
AH=AH+1

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 Subtraction Instructions
 Following figure shows set of instruction provided for implementing
subtraction:

Allowed operands for DEC Allowed operands for

Allowed operands for SUB and instruction. NEG instruction.
SBB instructions.
 SUB Instruction
Example: SUB AX, BX
where AX contains 8000h, BX contains 0001h

8000h
- 0001h
7FFFh = 0111 1111 1111 1111b
SF = 0 because the MSB is 0.
PF = 1 because there are 8 (even number) one bits in the low byte.
ZF = 0 because the result is nonzero.
CF = 0 because a smaller unsigned number is being subtracted from a
larger one.
OF = 1 because a positive number is being subtracted from a negative
one (like adding two negatives), and the result is positive.

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 SBB Instruction
 The subtract with borrow (SBB) instruction is similar to SUB,
however it also subtracts the contents of the carry flag.
 (D)←(D)-(S)-(CF)

 Example: Assuming that the contents of registers BX and CX are

123416 and 012316, respectively, and the carry flag is 0, what is
the result of executing the following instruction?
 SBB BX, CX
Solution:
The instruction implements the operation (BX)-(CX)-(CF) → (BX)
Therefore, (BX) = 1234H-0123H-0 = 1111H
The carry flag remains cleared since no borrow is needed.

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 NEG Instruction
 Negate. Makes operand negative (two's complement).
 Invert all bits of the operand
 Add 1 to inverted operand

• MOV AX, -5
AX= -5= FFFBh, none of the flags are affected
• NEG AX, AX=8000h
8000h = 1000 0000 0000 0000
2’s complement = 1000 0000 0000 0000
= 8000h
CF=1, OF=1, PF=1, ZF=0, SF=1

The CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The

OF, SF, ZF, AF, and PF flags are set according to the result
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 DEC Instruction
This instruction subs 1 to the destination.
Destination may be register or memory location.
It does not effects carry flag.

MOV AL, 255 ; AL = 0FFh (255 or -1)

DEC AL ; AL = 0FEh (254 or -2)
RET
 AAS
 ASCII Adjust after Subtraction. Corrects result in AH and AL after
subtraction when working with BCD values.
 Algorithm:
 If low nibble of AL > 9 or AF = 1 then: AL=AL-6, AH=AH-1, AF=1, CF=1
 else : AF=0, CF=0
 In both the cases Clear the Higher Nibble of AL.
 Example: Case-I
 Suppose AL contains 38H, and BL contains 35H, what will be the
out put for the following instructions:

Code UN LN HEX Comments

MOV AL,38H 0011 1000 38H AL=38H
MOV BL,35H 0011 0101 35H BL=35H
SUB AL, BL 0000 0011 03H AL=03H
AAS 0000 0011 03H AL=03H
ADD AL, 30 0011 0011 33H AL=33H
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 AAS
 Case-II:
 Suppose AL contains 35H, and BL contains 38H, what will be the
out put for the following instructions:

Code UN LN HEX Comments

MOV AL,35H 0011 0101 35H AL=35H
MOV BL,38H 0011 1000 38H BL=38H
SUB AL, BL 1111 1101 FDH AL=FDH
LN>9 (-) 0110 06H AL=06H
1111 0111 F7H AL=F7H
AH AL AAS 0000 0111 07H AL=07H
FF 07 The answer should be -3, but we get FF07H, which is the
10’s complement of 3.

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 AAS
 Case-III: Subtract ‘4’ from ‘15’.
 Suppose AX contains 3135H, and BL contains 34H, what will be the
out put for the following instructions:

Code AH AL Comments
MOV AX,3135H 00110001 00110101 AX=3135H
MOV BX,34H 00000000 00110100 BL=0034H
SUB AL, BL 00110001 00000001 AX=3101H
LN<0
AH AL AAS 00110001 00000001 AX=3101H
31H 01H OR AX,3030 00110001 00110001 AX=3131H

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 DAS
 Decimal adjust After Subtraction. Corrects the result of subtraction of
two packed BCD values.
 Algorithm:
 If low nibble of AL > 9 or AF = 1 then: AL = AL - 6 & AF = 1
 Else If upper nibble of AL > 9h or CF = 1 then: AL = AL - 60h & CF = 1
 Case-I: Subtract AL = 86 BCD, from BL = 57 BCD

Code UN LN HEX Comments

MOV AL,86 BCD 1000 0110 86H AL=86H
MOV BL,57BCD 0101 0111 57H BL=57H
AH AL
SUB AL, BL 0010 1111 2FH AL=2FH
00H 29H
LN>9 (-) 0110 06H AL=06H
0010 1001 29H AL=29H
DAS 0010 10001 29H AL=29H

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 DAS
 Case-II: Subtract AL = 49 BCD, from BL = 72 BCD

Code UN LN HEX Comments

MOV AL,49 BCD 0100 1001 49H AL=49H
MOV BL,72BCD 0111 0010 72H BL=72H
SUB AL, BL 1101 0111 D7H AL=D7H
UN>9 0110 0000 60H
0111 0111 77H AL=77H
AH AL DAS 0111 0111 77H AL=77H
31H 01H The answer should be -23, but we get 77H, which is the
10’s complement of 23.

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Multiplication & Division Instructions
 Following figure shows set of instruction provided for implementing
multiplication and division:
Mnemonic Meaning Format Operation Flags affected
MUL Multiply MUL S (AL) • (S8) → (AX) OF, CF
(unsigned) (AX) • (S16) → (DX),(AX) SF, ZF, AF, PF undefined

DIV Division DIV S (1) Q((AX)/(S8)) → (AL) R((AX)/(S8)) → OF, SF, ZF, AF, PF, CF
(unsigned) (AH)
(2) Q((DX,AX)/(S16)) → (AX) Undefined
R((DX,AX)/(S16)) → (DX) If Q is FF16
in case (1) or FFFF16 in case (2), then
type 0 interrupt occurs
IMUL Multiply (AL) • (S8) → (AX) OF, CF
(signed) (AX) • (S16) → (DX),(AX) SF, ZF, AF, PF undefined
IDIV Division (1) Q((AX)/(S8)) → (AL) OF, CF
(signed) R((AX)/(S8)) → (AH) SF, ZF, AF, PF undefined
(2) Q((DX,AX)/(S16)) → (AX) OF, SF, ZF, AF, PF, CF
R((DX,AX)/(S16)) → (DX) undefined
f Q is positive and exceeds 7FFF16 or if Q is
negative and becomes less than 800116, then
type 0 interrupt occurs
Multiplication & Division Instructions
Mnemonic Meaning Format Operation Flags affected

AAM Adjust AL for AAM Q((AL)/10) → (AH) SF, ZF, PF

multiplication R((AL)/10) → (AL) OF, AF,CF undefined
AAD Adjust AX for AAD (AH) • 10 (AL) → (AL) SF, ZF, PF
division 00 → (AH) OF, AF, CF undefined
CBW Convert byte to CBW (MSB of AL) → (All bits of AH) None
word
CWD Convert word to CWD (MSB of AX) → (All bits of DX) None
double word

Allowed operands.
 Integer Multiplication
• Contrary to addition, the multiplication operation depends on the
interpretation:
 no interpretation: FFh x 2h = ??
 unsigned interp.: 255 x 2 = 510
 signed interpret.: -1 x 2 = -2

• We thus have two different multiplication instructions:

MUL source ;for unsigned multiplication
IMUL source ;for signed multiplication

• Where source must be either mem or reg

 Source is the “multiplier” and the “multiplicand” is in an A_
register

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 MUL Instruction
 The instruction performs unsigned multiplication.
 If source is of 8 bits, it will multiply with AL and result will
be stored in AX register.
 If source is of 16 bits, it will multiply with AX and result
will be stored in DX-AX registers.
 Algorithm:
 when operand is a byte: AX = AL * operand.
 when operand is a word: (DX ,AX) = AX * operand

 Syntax
 MUL Register
 MUL memory

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 IMUL Instruction
 The instruction performs signed multiplication.
 If source is of 8 bits, it will multiply with AL and result will
be stored in AX register.
 If source is of 16 bits, it will multiply with AX and result
will be stored in DX-AX registers.
 Algorithm:
 when operand is a byte: AX = AL * operand.
 when operand is a word: (DX ,AX) = AX * operand

 Syntax
 IMUL Register
 IMUL memory

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 MUL & IMUL Instruction
Example:
MOV AL, 200 ; AL = 0C8h
MOV BL, 4
MUL BL ; AX = 0320h (800)

Example:
MOV AL, -2
MOV BL, -4
IMUL BL ; AX = 8

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 MUL & IMUL Instruction
 The 2’s-complement signed data contents of AL equal 1 and the contents of CL
are 2. What result is produced in AX by executing the following instructions?

MUL CL
and
IMUL CL
Solution
As binary data, the contents of AL and CL are:
(AL)=-1 (as 2’s complement)= 111111112 =FF16
(CL)=-2 (as 2’s complement)= 111111102 = FE16
Executing the MUL instruction gives
(AX)=111111112 =111111102 =11111101000000102 =FD0216
The second instruction multiplies the two numbers as signed numbers to generate
the signed result. That is,
(AX)=-116 ×-216
=216 =0002H
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 Examples of MUL and IMUL
• Say that AX = 1h and BX = FFFFh, then:

– Instruction Result DX AX CF/OF

MUL BX 65535 0000 FFFF 0
IMUL BX -1 FFFF FFFF 0

• Say that AX = FFFFh and BX = FFFFh, then:

– Instruction Result DX AX CF/OF

MUL BX 4294836225 FFFE 0001 1
IMUL BX 1 0000 0001 0
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Examples of MUL and IMUL (cont.)
• AL = 30h and BL = 4h, then:
– Instruction Result AH AL CF/OF
MUL BL 192 00 C0 0
IMUL BL 192 00 C0 1

• AL = 80h and BL = FFh, then

– Instruction Result AH AL CF/OF

MUL BL 32640 7F 80 1
IMUL BL 128 00 80 1
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 Exercise 1
• Give the hexadecimal content of AX and the values of CF
and OF immediately after the execution of each instruction
below

– IMUL AH ;when AX = 0FE02h

– MUL BH ;when AL = 8Eh and BH = 10h

– IMUL BH ;when AL = 9Dh and BH = 10h

– IMUL AX,0FFh;when AX = 0FFh

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 Integer Division
• Notation for integer division:
– Ex: 7 ¸ 2 = (3, 1) not_equal to 7 / 2 = 3.5
– dividend ¸ divisor = (quotient, remainder)

• We have 2 instructions for division:

– DIV divisor ;unsigned division
– IDIV divisor ;signed division
• The divisor must be reg or mem
• Convention for IDIV: the remainder has always the same sign
as the dividend.
– Ex: -5 ¸ 2 = (-2, -1) ; not: (-2, 1)

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 DIV Instruction
 The instruction performs unsigned division.
 It divides a word by byte and a double word by word.
 If divisor is of 8 bits, it will divides with AX and result of quotient will
be there in AL register and reminder will be stored in AH register.
 If divisor is of 16 bits, it will divides with DX-AX double word and
result of quotient will be there in AX register and reminder will be
stored in DX register.
 Algorithm:
 When operand is a byte:
 Syntax
 AL = AX / operand
 DIV Register
 AH = remainder (modulus)
 When operand is a word:  DIV memory
 AX = (DX AX) / operand
 DX = remainder (modulus)

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 IDIV Instruction
 The instruction performs signed division.
 It divides a word by byte and a double word by word.
 If divisor is of 8 bits, it will divides with AX and result of quotient will
be there in AL register and reminder will be stored in AH register.
 If divisor is of 16 bits, it will divides with DX-AX double word and
result of quotient will be there in AX register and reminder will be
stored in DX register.
 Algorithm:
 When operand is a byte:
 Syntax
 AL = AX / operand
 IDIV Register
 AH = remainder (modulus)
 When operand is a word:  IDIV memory
 AX = (DX AX) / operand
 DX = remainder (modulus)

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 DIV and IDIV Instruction
Example:
MOV AX, 203 ; AX = 00CBh
MOV BL, 4
DIV BL ; AL = 50 (32h), AH = 3
RET

Example:
MOV AX, -203 ; AX = 0FF35h
MOV BL, 4
IDIV BL ; AL = -50 (CEh), AH = -3 (FDh)
RET

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 Examples of DIV and IDIV
• DX = 0000h, AX = 0005h, BX = FFFEh:

– Instruction Quot. Rem. AX DX

DIV BX 0 5 0000 0005
IDIV BX -2 1 FFFE 0001

• DX = FFFFh, AX = FFFBh, BX = 0002h:

– Instruction Quot. Rem. AX DX

IDIV BX -2 -1 FFFE FFFF
DIV BX DIVIDE OVERFLOW

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 Examples of DIV and IDIV (cont.)
• AX = 0007, BX = FFFEh:
– Instruction Quot. Rem. AL AH
DIV BL 0 7 00 07
IDIV BL -3 1 FD 01

• AX = 00FBh, BX = 0CFFh:
– Instruction Quot. Rem. AL AH
DIV BL 0 251 00 FB
IDIV BL DIVIDE OVERFLOW
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 Exercise 2
• Give the hexadecimal content of AX immediately
after the execution of each instruction below or
indicate if there is a divide overflow

– IDIV BL ; when AX = 0FFFBh and BL = 0FEh

– IDIV BL ; when AX = 0080h and BL = 0FFh

– DIV BL ; when AX = 7FFFh and BL = 08h

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 CBW Instruction
 Convert sign byte (AL) into sign word (AX).
 The CBW instruction copies the sign bit (D7) of AL register into AH
register. If high bit of AL = 1 then: AH = 255 (0FFh) Else : AH = 0

Example:
MOV AL, 60H ; AL = 01100000=+96
CBW ; AX=00000000 01100000=+96
; AH=00000000 AL=01100000

Example:
MOV AL, 80H ; AL = 10000000=-128
CBW ; AX=11111111 1000000=FF80H-128
; AH=11111111 AL=10000000

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 CWD Instruction
 Convert sign word (AX) into sign double word (DX-AX).
 The CWD instruction copies the sign bit (D15) of AX register into DX
register. If High bit of AX=1 then : DX = 65535 (0FFFFh) else : DX = 0

Example:
MOV AX, 0104H ; AX = 0000 0001 0000 0100=+260
CWD ; AX=0000 0001 0000 0100=0104h
; DX=0000 0000 0000 0000=0000h

Example:
MOV AX, 8002H ; AX = 1000 0000 0000 0010=-32766
CWD ; AX=1000 0000 0000 0010=8002h
; DX=1111 1111 1111 1111=FFFFh

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 Example
 What is the result of executing the following sequence of instructions?
MOV AL, 0A1H
CBW
CWD
Example:
The first instruction loads AL with A1H. This gives
(AL)=A116=101000012
Executing the second instruction extends the most significant bit of AL, 1, into
all bits of AH. The result is
(AH)=111111112=FF16 Or (AX)=11111111101000012=FFA116
This completes conversion of the byte in AL to a word in AX.
The last instruction loads each bit of DX with the most significant bit of AX.
This bit is also 1. Therefore, we get
(DX)= 11111111111111112= FFFF16
Now the word in AX has been extended to a double word.
(AX) =FFA116
(DX)=FFFF16
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AND, OR, XOR, and NOT Instructions

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 NOT Instructions

This instruction performs 1’s compliment of

destination and stores answer in destination.
Destination can be register or memory
location.
Does not effect any flag register.
Format: NOT AL
If AL= 47H=0100 0111
After execution of instruction,
AL=1011 1000=B8H
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 AND Instructions
This instruction performs logic AND operation
between source and destination.
Destination can be register or memory location.
Source can be register or memory location or data.
AND AL, BL
If AL= 47H=0100 0111 and BL=36H=0011 0110
After execution of instruction,
AL=0000 0110=06H
 PF, SF, and ZF affected, CF=OF=0 and AF is
undefined
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 Check a Specific Bit Status
For example, you want to check the status of 7th
bit in a 16-bit register, how to do that?
AND instruction?
AND AX, 0080H
If 7th bit is zero, zero flag will be set otherwise
zero flag will be reset to zero.
Any problem with this instruction?
 Yes, it changes the destination register.

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 TEST Instructions
This instruction performs logic AND operation between
source and destination.
Result is not stored anywhere. It only updates flag
register without changing destination.
Destination can be register or memory location.
Source can be register or memory location or data.
For example, if you are required to check the status of 7th
bit in a 16-bit register, you can write
TEST AX, 0080H;
ZF will be set if 7th bit in AX is zero, ZF will be zero if
7th bit in AX is 1.
 Only ZF is updated, keeping AX unchanged.
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 OR Instructions
This instruction performs logic OR operation between
source and destination.
Destination can be register or memory location.
Source can be register or memory location or data.
OR AL, BL
If AL= 47H=0100 0111 and BL=36H=0011 0110
After execution of instruction,
AL=0111 0111=77H
 PF, SF, and ZF affected, CF=OF=0 and AF is
undefined
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 XOR Instructions
This instruction performs logic XOR operation
between source and destination.
Destination can be register or memory location.
Source can be register or memory location or data.
XOR AL, BL
If AL= 47H=0100 0111 and BL=36H=0011 0110
After execution of instruction,
AL=0111 0001=71H
 PF, SF, and ZF affected, CF=OF=0 and AF is
undefined
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 MASK Operations
To modify only selective bits in destination, we
construct a source bit pattern known as mask.
To choose mask use the following properties

B and 1 B (unchanged)
B and 0 0 (clear)
B OR 1 1 (set)
B OR 0 B (Unchanged)
B XOR 0 B (unchanged)
B XOR 1 B’ (Complement)

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 MASK Operations-Clear
The AND instruction
 It may be used to clear specific destination bits while
preventing others
 A 0 mask bit clear the corresponding destination bit.
 A 1 mask bit preserves the corresponding destination
bit.
For example: Clear the sign bit of AL while leaving
the others bits unchanged
 Solution: AND AL, 7FH
 Where, 7FH(0111 1111) is the mask.

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 MASK Operations-Set
The OR instruction
 It may be used to set specific destination bits while
preventing others
 A 1 mask bit sets the corresponding destination bit.
 A 0 mask bit preserves the corresponding destination
bit.
For example: Set the MSB and LSB of AL while
preserving the other bits.
 Solution: OR AL, 81H
 Where, 81H(1000 0001) is the mask.

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 MASK Operations-Complement
The XOR instruction
 It may be used to complement specific destination
bits while preventing others
 A 1 mask bit complements the corresponding
destination bit.
 A 0 mask bit preserves the corresponding destination
bit.
For example: Change the sign bit of DX.
 Solution: XOR DX, 8000H
 Where, 8000H (1000 0000 0000 0000) is the
mask.
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