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DE LAB Question Bank

The document contains 58 questions related to digital logic design and implementation of various digital circuits using logic gates and ICs such as flip-flops, counters, multiplexers, decoders. The questions cover topics such as design of different radix adders, magnitude comparators, multiplexer-based implementations of full adders and subtractors, various counter circuits including asynchronous, synchronous, BCD and other mod-n counters, converters between binary and gray codes, shift registers, and more.

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Malayalam Tech
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76 views2 pages

DE LAB Question Bank

The document contains 58 questions related to digital logic design and implementation of various digital circuits using logic gates and ICs such as flip-flops, counters, multiplexers, decoders. The questions cover topics such as design of different radix adders, magnitude comparators, multiplexer-based implementations of full adders and subtractors, various counter circuits including asynchronous, synchronous, BCD and other mod-n counters, converters between binary and gray codes, shift registers, and more.

Uploaded by

Malayalam Tech
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DIVISION OF ELECTRONICS, SOE, CUSAT

DIGITAL LAB QUESTION BANK


1. Design a 4-bit radix 7 adder
2. Implement a radix 5 adder
3. Design a radix 12 adder
4. Implement a single digit radix 9 adder
5. Design a radix 11 adder
6. Design and setup a circuit to check whether the 2 digit BCD number is divisible by 9
7. Design and setup a circuit to check whether the 2 digit BCD number is divisible by 3
8. Design a magnitude comparator that compares two 3-bit numbers using IC 7483
9. Setup a circuit to evaluate z=4x+3y where x & y are 3-bit numbers
10. Setup a circuit to find z=2x+3y where x & y are 3-bit numbers
11. Setup a 16:1 mux using 4:1 mux tree given 74153 ICs
12. Implement a full adder using 8:1 multiplexer(minimum numbers)
13. Implement a full adder using 4:1 multiplexer(minimum numbers)
14. Implement a full subtractor using 8:1 multiplexer(minimum numbers)
15. Implement of full adder using 3:8 decoder and additional gates
16. Implement a full subtractor using 3:8 decoder IC
17. Setup a 3-bit binary to gray code converter using decoder IC
18. Setup a 3-bit gray to binary code converter using decoder IC
19. Design a 3 bit gray code to binary code converter using decoder and encoder
20. Setup a synchronous circuit that generates the following sequence….01110….
21. Design a logical circuit for three platforms in a railway station. A train should be
routed to the platform A if it is empty, else to platform B, else to platform C. If all the
platforms are occupied, give red signal to incoming train.
22. Implement a 10 line BCD priority encoder
23. Setup a 3 bit asynchronous gray code counter.
24. Setup an asynchronous sequential circuit to generate the following bit pattern and the
waveform.
01001011
25. Setup an asynchronous sequential circuit to generate the following bit pattern and the
waveform.
11101
26. Setup a burglar alarm that produces sound when a burglar is sensed and to get reset
only on pressing reset button.(using JK flip flop)
27. Setup an asynchronous single digit BCD counter and XS3 counter with a mode
control input M.
M=0, BCD counter
M=1,XS3 counter
28. Set up an asynchronous 3-bit binary/gray counter with a mode control input. When
M=0, it counts binary and when M=1, it counts gray.
29. Design a 4-bit asynchronous programmable mod N counter in which n may vary
from 0 to 15
30. Setup a four key musical organ that produces four different tones corresponding to
each key (hint: use 3 bit counter and 4:1 MUX IC).
31. setup asynchronous counter circuit that produces the following sequence 0--1--1--1--
0.
32. Design and set up 3-bit synchronous gray code counter
33. Design and set up a synchronous counter that counts the sequence 2,0,5,3,7 use JK
flip flop.
34. Design and setup a synchronous counter that counts the sequence 2-0-5-3-7. Use JK
flip flop for MSB (Q2), SR flip flop for Q1, and D flip flop for LSB (Q0).
35. Convert a D flip flop to JK flip flop
36. Set up a counter that counts 04-53 using 7490IC.
37. Set up a counter that counts 09-46 using 7490IC.
38. Set up a counter that counts 00-59 ( seconds counter)
39. Set a counter that counts 00-23 hr using 7490
40. To design a 24 hour digital clock using counters (00:00:00-23:59:59)
41. Set up a circuit to for a cascading mod 40 counter using 7490 and 7493 IC.
42. To set up a MOD 40 parallel counter using ICs 7490 and 7493.
43. Set up a mode 30 cascadecounter using 7490 and 7492.
44. To design and set up a mod 48 cascade counter using 7492 and 7493 ICs.
45. To design a mod 24(6*4)counter using 7492 & 7493.
46. Set up a mode 30 parallel counter (7490 & 7492).
47. Design a circuit to check whether the given four bit number is divisible by three
using 8:1 mux
48. To setup an asynchronous counter that count 1,3,3,6,5,2 and repeat the sequence.
49. Design a 3 bit binary code to gray code converter using decoder and encoder.
50. Implement a 3-bit synchronous Jonson’s counter.
51. Set up a 2 digit BCD counter using 7490 .Display the out put in 7- segment LED
Display
52. Set up an adder/subtractor circuit using 7483
53. Set up a single digit BCD adder using 7483
54. Function implementation using MUX IC (74151/74153)
55. Full adder/ subtractor using NAND/NOR gates only
56. Set up a MOD- n / MOD-2n counter using mode bit.
57. Set up a 4-bit parallel-in-serial-out shift register .
58. Set up a JK MASTER SLAVE circuit using NAND gates only.

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