TN-40-41: Adding ECC With DDR4 x16 Components

Introduction

Technical Note
Adding ECC to a Data Bus with DDR4 x16 Components

Introduction
Systems with lower density memory requirements use x16 DRAM components to save space, cost and power.
System designers who also have high data integrity requirements may want to implement ECC using an extra 8-
bit data path, making for some awkward combinations of components on the data bus. DDR4 creates additional
challenges caused by the different number of bank groups on x8 and x16 components. This technical note
provides guidance for adding ECC on a single-rank, point-to-point DDR4 data bus when using x16 components.
Note: All tables in this technical note are based on current production DDR4 devices available at the time of
publishing: 8Gb Rev. R (1α Z41C) and 16Gb Rev. F (1α Z42B). Component area is based on package size only and
does not include board area needed for signal routing.

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Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
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information discussed herein is provided on an "as is" basis, without warranties of any kind.
 TN-40-41: Adding ECC With DDR4 x16 Components
Important Notes and Warnings

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 TN-40-41: Adding ECC With DDR4 x16 Components
DDR4 Bus Configurations

DDR4 Bus Configurations

The most common data widths for adding ECC to data paths are x32 and x64. Table 1 shows the three
lowest densities that can be configured on a single-rank 32-bit DDR4 bus; Table 2 shows the same
information for a 64-bit DDR4 bus. The lowest density is always achieved using x16 components, but
there are two ways to configure the next highest density. Figures 1 and 2 outline how the components
are connected for each bus width.
Table 1: DDR4 Single-Rank x32 Bus Configuration Options
Configuration Density Component Area IDD7 @ 3200 MT/s
8Gb x16 (2 pcs) 2GB 195 mm2 (Rev. R) 450 mA
16Gb x16 (2 pcs) 4GB 195 mm2 (Rev. F) 400 mA
8Gb x8 (4 pcs) 4GB 330 mm2 (Rev. R) 620 mA
16Gb x8 (4 pcs) 8GB 330 mm2 (Rev. F) 668 mA
32Gb x16 DDP (2 pcs) 8GB 195 mm2 (Rev. F) 668 mA

Figure 1: x32 Bus Configuration Diagrams

a) With x16 Components

x16 x16

8 8 8 8

x32 Controller

b) With x8 Components

x8 x8 x8 x8

8 8 8 8

x32 Controller

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 TN-40-41: Adding ECC With DDR4 x16 Components
DDR4 Bus Configurations

Table 2: DDR4 Single-Rank x64 Bus Configuration Options

Configuration Density Component Area IDD7 @ 3200 MT/s
8Gb x16 (4 pcs) 4GB 390 mm2 (Rev. R) 900 mA
16Gb x16 (4 pcs) 8GB 390 mm2 (Rev. F) 800 mA
8Gb x8 (8 pcs) 8GB 660 mm2 (Rev. R) 1240 mA
16Gb x8 (8 pcs) 16GB 660 mm2 (Rev. F) 1336 mA
32Gb x16 DDP (4 pcs) 16GB 390 mm2 (Rev. F) 1336 mA

Figure 2: x64 Bus Configuration Diagrams

a) With x16 Components

x16 x16 x16 x16

8 8 8 8 8 8 8 8

x64 Controller

b) With x8 Components

x8 x8 x8 x8 x8 x8 x8 x8

8 8 8 8 8 8 8 8

x64 Controller

The tables above show that when there is a choice between x16 and x8 components, the x16
configuration has clear advantages in board area and power consumption over the same density x8
configuration. In addition, the controller has fewer loads on the command/address/clock signals
when using true x16 components. The reduced loading can help with layout, signal integrity and even
controller power for driving these signals. Note that the x16 DDP components will present the same
command/address/clock signal loading and power as using x8 components, but will provide an
advantage in board area.

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 TN-40-41: Adding ECC With DDR4 x16 Components
Adding ECC

Adding ECC
As mentioned in the introduction, the system requirements for some applications require an
additional level of data integrity and confidence, and this is commonly addressed using ECC. For 32-
and 64-bit data paths, ECC protection is provided by adding an extra 8 bits, making buses that are 40-
bits and 72-bits wide, respectively. (It is beyond the scope of this document to discuss the
implementation and merits of specific ECC schemes.)
There are several challenges when adding ECC to a DDR4 bus. The ECC component must be selected
to match the addressing used by the other components on the bus. Because x16 DDR4 components
have only two bank groups and x8 components have four bank groups, it is not possible to use a x8
component of half the density (as could be done for DDR3 designs). The addressing for a x8 DDR4
component forces the ECC device to be the same density as the x16 component, and half of the
density goes unused in the form of two extra bank groups.
The alternative is to use a x16 component for ECC. To make the row and column addressing match
the data components, the ECC component must have the same density. Using the same density x16
component has the advantage of simplifying the BOM somewhat (all DDR4 devices are identical), but
it does result in an unused byte lane on the ECC component.
We will examine both options.
ECC With an Additional x16 Component
As mentioned above, using an additional x16 component for ECC simplifies the DRAM portion of the
BOM because the same component is used for all placements on the bus, but it has disadvantages as
well. Compared to a x8 ECC component, the x16 power will be slightly higher and it will use a bit more
board space. In addition, there is an unused byte lane that must be terminated. The following figure
shows a high-level diagram of adding a x16 component for ECC.
Figure 3: Adding a x16 Component for ECC
a) x32 Data Path

x16 x16 x16

8 8 8 8 8 8

NC
x40 Controller

b) x64 Data Path

x16 x16 x16 x16 x16

8 8 8 8 8 8 8 8 8 8

NC
x72 Controller

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 TN-40-41: Adding ECC With DDR4 x16 Components
Adding ECC

When using a x16 component for ECC, the lower byte lane (DQ[7:0]) must be used for the ECC bits.
DDR4 memory is capable of per-DRAM addressability (PDA), and this function is used during the
DDR4 device initialization sequence for VREFDQ calibration. PDA is enabled by DQ0, so the lower byte
lane must be used and connected to the controller.
The unused upper byte lane should be terminated as follows:
• DQ[15:8] can be left floating (ODT will terminate to VDDQ)
• UDM_n/UDBI_n should be terminated to VDDQ (allows DM or DBI to be enabled)
• UDQS_t should be terminated to VDDQ
• UDQS_c should be terminated to VSSQ
Figure 4 shows the details of these connections.
Figure 4: DDR4 x16 Component Connected as ECC Device

DQ[15:8] Float
UDM_n/UDBI_n VDD
UDQS_t
UDQS_c
Controller

DQ[7:0]
LDM_n/LDBI_n
LDQS_t
LDQS_c

ECC With an Additional x8 Component

Using an additional x8 component for ECC results in slightly lower power and will use slightly less
board space than a x16 component. In addition, there is no unused byte lane to terminate. But,
matching the address configuration of the x16 data components begins with a x8 ECC component of
the same density as the x16, with half of the bank groups disabled. Figure 5 shows a high-level
diagram of adding a x8 component for ECC.

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 TN-40-41: Adding ECC With DDR4 x16 Components
Adding ECC

Figure 5: Adding a x8 Component for ECC

a) x32 Data Path

x16 x16 x8

8 8 8 8 8

x40 Controller

b) x64 Data Path

x16 x16 x16 x16 x8

8 8 8 8 8 8 8 8 8

x72 Controller

Half of the bank groups are disabled by tying BG1 to VSSQ, as shown in Figure 6. This enables
command/address parity. Because the unused BG1 input on the x16 devices is treated as a zero, the
parity generated by both the x16 and the x8 devices will be the same.
Figure 6: DDR4 x8 Component Connected as ECC Device

BG1
Controller

DQ[7:0]
DM_n/DBI_n
DQS_t
DQS_c

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 TN-40-41: Adding ECC With DDR4 x16 Components
Considerations for Using DDR4 x16 DDP

Considerations for Using DDR4 x16 DDP

The DDR4 standard includes a special configuration for a x16 dual die package (DDP). This device
contains two x8 die connected as a single rank. Although more expensive than two discrete x8 DDR4
packages, the DDP occupies considerably less board area. This makes it an excellent option where
higher density is needed, but board space is constrained. Because the DDP uses x8 die, BG1 is
required on the x16 DDP package. (A second ZQ is also required on the board; for suggestions on
designing a board that accepts both standard x16 DDR4 and DDP x16 DDR4 devices, see TN-40-40:
DDR4 Point-to-Point Design Guide.)
When adding ECC to a data bus using x16 DDP devices, the most economic choice is to use an
additional discrete x8 component for the ECC device. No special connections are needed, as all
devices use BG1, and all DQ signals (byte lanes) are used. Figure 7 shows an overview for adding ECC
when using x16 DDP devices.
Figure 7: Adding ECC to x16 DDP Components
a) x32 Data Path

x16 DDP x16 DDP

x8 x8 x8 x8
x8
die die die die SDP

8 8 8 8 8

x40 Controller

b) x64 Data Path

x16 DDP x16 DDP x16 DDP x16 DDP

x8 x8 x8 x8 x8 x8 x8 x8
x8
die die die die die die die die SDP

8 8 8 8 8 8 8 8 8

x72 Controller

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 TN-40-41: Adding ECC With DDR4 x16 Components
DDR4 Bus with ECC

DDR4 Bus with ECC

Tables 3 and 4 compare the key parameters for the various options of adding ECC to DDR4 buses of
various densities. Table 3 shows these results for a x32 data path (x40 total bus width), and Table 4
shows them for a x64 data path (x72 total bus width).
Table 3: Key Parameters for x32 DDR4 Data Path With ECC
x32 Data Bus with ECC Density Component Area IDD7 @ 3200 MT/s
Using x8 ECC Component
8Gb x16 (2 pcs + 8Gb x8 ECC) 2GB 277.5 mm2 (Rev. R) 605 mA
16Gb x16 (2 pcs + 16Gb x8 4GB 277.5 mm2 (Rev. F) 567 mA
ECC)
8Gb x8 (5 pcs) 4GB 412.5 mm2 (Rev. R) 775 mA
16Gb x8 (5 pcs) 8GB 412.5 mm2 (Rev. F) 835 mA
32Gb x16 DDP (2 pcs + 16Gb 8GB 277.5 mm2 (Rev. F) 835 mA
x8 ECC)
Using x16 ECC Component
8Gb x16 (3 pcs) 2GB 292.5 mm2 (Rev. R) 675 mA
16Gb x16 (3 pcs) 4GB 292.5 mm2 (Rev. F) 600 mA

Table 4: Key Parameters for x64 DDR4 Data Path With ECC
x64 Data Bus with ECC Density Component Area IDD7 @ 3200 MT/s
Using x8 ECC Component
8Gb x16 (4 pcs + 8Gb x8 ECC) 4GB 472.5 mm2 (Rev. R) 1055 mA
16Gb x16 (4 pcs + 16Gb x8 8GB 472.5 mm2 (Rev. F) 967 mA
ECC)
8Gb x8 (9 pcs) 8GB 742.5 mm2 (Rev. R) 1395 mA
16Gb x8 (9 pcs) 16GB 742.5 mm2 (Rev. F) 1503 mA
32Gb x16 DDP (4 pcs + 16Gb 16GB 472.5 mm2 (Rev. F) 1503 mA
x8 ECC)
Using x16 ECC Component
8Gb x16 (5 pcs) 4GB 487.5 mm2 (Rev. R) 1125 mA
16Gb x16 (5 pcs) 8GB 487.5 mm2 (Rev. F) 1000 mA

As the tables show, using x16 data components with a x8 component for ECC results in the lowest
power and the least board area. Using a x16 component for ECC simplifies the BOM (and thus the
procurement process) at the cost of small increases in power and board area, plus a slight added
complexity in terminating an unused byte lane.
The x16 DDP provides the same density and power as using all x8 components, but at the same
component area as the standard x16 with the x8 ECC component. Thus, you get twice the density in
the same board area.

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 TN-40-41: Adding ECC With DDR4 x16 Components
Write CRC

Write CRC
System designers who wish to use the DDR4 write CRC feature as a debug or verification tool should
check that the DRAM used for ECC is suitable. While older generations of Micron DRAMs may not
support the write CRC feature when using a x16 as an ECC part, Micron's latest generations of DDR4
x16 (8Gb Die Rev E and Rev R, 16Gb Die Rev B, E, and F) will manage the write CRC correctly for the
lower byte as long as the upper DQ/DQS pins are floating.

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 TN-40-41: Adding ECC With DDR4 x16 Components
Conclusion

Conclusion
There are several viable choices for adding ECC to low-density DDR4 buses. The optimal choice for
any design will be the balance of power, board space and BOM complexity (including additional
terminations for unused signals on the byte lane). The guidelines presented here will help the
designer find the implementation with the right balance for their needs.

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 TN-40-41: Adding ECC With DDR4 x16 Components
Revision History

Revision History
Rev. B – 3/23
• Updated Write CRC section
• Updated Tables 1-4
Rev. A – 3/18
• Initial release

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