OPA1637

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SBOSA00B – DECEMBER 2019 – REVISED AUGUST 2020
SBOSA00B – DECEMBER 2019 – REVISED AUGUST 2020

OPA1637 High-Fidelity, Low-Noise, Fully-Differential, Burr-Brown™ Audio

Operational Amplifier

1 Features 3 Description
• Low input voltage noise: 3.7 nV/√Hz at 1 kHz The OPA1637 is a low-noise, low total harmonic
• Low THD + N: –120 dB at 1 kHz distortion (THD), fully differential, Burr-Brown™ Audio
• Low supply current: 950 µA at ±18 V operational amplifier that easily filters and drives fully
• Input offset voltage: ±200 µV (maximum) differential, audio signal chains.
• Input bias current: 2 nA (maximum) The OPA1637 also converts single-ended sources to
• Low bias current noise: 400 fA/√Hz at 10 Hz differential outputs required by high-fidelity analog-to-
• Gain-bandwidth product: 9.2 MHz digital converters (ADCs). Designed for exceptional
• Differential output slew rate: 15 V/µs low noise and THD, the bipolar super-beta inputs yield
a very low noise figure at very-low quiescent current
• Wide input and output common-mode range
and input bias current. This device is designed for
• Wide single-supply operating range: 3 V to 36 V audio circuits where low power consumption is
• Low supply current power-down feature: < 20 µA required along with excellent signal-to-noise ratio
• Overload power limit (SNR) and spurious-free dynamic range (SFDR).
• Current limit
The OPA1637 features high-voltage supply capability,
• Package: 8-pin VSSOP allowing for supply voltages up to ±18 V. This
• Temperature range: –40°C to +125°C capability allows high-voltage differential signal chains
2 Applications to benefit from the improved headroom and dynamic
range without adding separate amplifiers for each
• Professional audio mixer or control surface polarity of the differential signal. Very-low voltage and
• Professional microphones and wireless systems current noise enables the OPA1637 for use in high-
• Professional speaker systems gain configurations with minimal impact to the audio
• Professional audio amplifier signal noise.
• Soundbar The OPA1637 is characterized for operation over the
• Turntable wide temperature range of –40°C to +125°C, and is
• Professional video camera available in an 8-pin VSSOP package.
• Guitar and other instrument amplifier Device Information (1)
• Data aquisition (DAQ) PART NUMBER PACKAGE BODY SIZE (NOM)
OPA1637 VSSOP (8) 3.00 mm × 3.00 mm

(1) For all available packages, see the package option

addendum at the end of the datasheet.

RF1 100
1k
70
50
Voltage Noise Density (nV/—Hz)

CF1
3.3 nF C2
RISO1
1 µF 30
75
RI1 INPUT_A
5V 49 5V 20
± TPA3251
PCM1795 IOUTL/R+ ± 3.5 V + CDF
Class D 10
C5 OPA1637 10 nF
Audio DAC IOUTL/R± ± ADC
Amplifier
1 µF + PD C3 7
1 µF
GND 5
±10 V RI2 ±10 V 5 V INPUT_B
49 RISO2 3
75
CF2
RF2
3.3 nF
2
1k GND

1
Low-Noise, Low-Power, Fully-Differential Amplifier 100m 1 10 100
Frequency (Hz)
1k 10k 100k

Gain Block and Interface

D022

Low Input Voltage Noise

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Table of Contents
1 Features............................................................................1 8.4 Device Functional Modes..........................................17
2 Applications..................................................................... 1 9 Application and Implementation.................................. 18
3 Description.......................................................................1 9.1 Application Information............................................. 18
4 Revision History.............................................................. 2 9.2 Typical Applications.................................................. 22
5 Pin Configuration and Functions...................................3 10 Power Supply Recommendations..............................27
6 Specifications.................................................................. 4 11 Layout........................................................................... 27
6.1 Absolute Maximum Ratings........................................ 4 11.1 Layout Guidelines................................................... 27
6.2 ESD Ratings............................................................... 4 11.2 Layout Example...................................................... 27
6.3 Recommended Operating Conditions.........................4 12 Device and Documentation Support..........................28
6.4 Thermal Information....................................................4 12.1 Device Support....................................................... 28
6.5 Electrical Characteristics.............................................5 12.2 Documentation Support.......................................... 28
6.6 Typical Characteristics................................................ 8 12.3 Receiving Notification of Documentation Updates..28
7 Parameter Measurement Information.......................... 15 12.4 Support Resources................................................. 28
7.1 Characterization Configuration................................. 15 12.5 Trademarks............................................................. 28
8 Detailed Description......................................................16 12.6 Electrostatic Discharge Caution..............................28
8.1 Overview................................................................... 16 12.7 Glossary..................................................................28
8.2 Functional Block Diagram......................................... 16 13 Mechanical, Packaging, and Orderable
8.3 Feature Description...................................................17 Information.................................................................... 28

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2020) to Revision B (August 2020) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed front page application diagram to show correct label and value for RF1 ............................................ 1
• Changed Figure 7-1 to show correct labels...................................................................................................... 15
• Changed Figure 9-5 to show correct label and value for RF1 .......................................................................... 22
• Changed Figure 9-8 negative rail from 0 V to –5 V.......................................................................................... 24

Changes from Revision * (December 2019) to Revision A (May 2020) Page

• Changed device status from advanced information (preview) to production data (active) ................................ 1

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5 Pin Configuration and Functions

IN- 1 8 IN+

VOCM 2 7 PD

VS+ 3 6 VS-

OUT+ 4 5 OUT-

Figure 5-1. DGK Package, 8-Pin VSSOP, Top View

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
IN– 1 I Inverting (negative) amplifier input
IN+ 8 I Noninverting (positive) amplifier input
OUT– 5 O Inverting (negative) amplifier output
OUT+ 4 O Noninverting (positive) amplifier output
Power down.
PD = logic low = power off mode.
PD 7 I PD = logic high = normal operation.
The logic threshold is referenced to VS+.
If power down is not needed, leave PD floating.
VOCM 2 I Ouput common-mode voltage control input
VS– 6 I Negative power-supply input
VS+ 3 I Positive power-supply input

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Single supply 40 V
VS Supply voltage
Dual supply ±20 V
IN+, IN–, Differential voltage(2) ±0.5 V
IN+, IN–, VOCM, PD, OUT+, OUT− voltage(3) VVS– – 0.5 VVS+ + 0.5 V
IN+, IN− current –10 10 mA
OUT+, OUT− current –50 50 mA
Output short-circuit(4) Continuous
TA Operating Temperature –40 150 °C
TJ Junction Temperature –40 175 °C
Tstg Storage Temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins IN+ and IN– are connected with anti-parallel diodes in between the two terminals. Differential input signals that are greater
than 0.5 V or less than –0.5 V must be current-limited to 10 mA or less.
(3) Input terminals are diode-clamped to the supply rails (VS+, VS–). Input signals that swing more than 0.5 V greater or less the supply
rails must be current-limited to 10 mA or less.
(4) Short-circuit to VS / 2.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Single-supply 3 36
VS Supply voltage V
Dual-supply ±1.5 ±18
TA Specified temperature –40 125 °C

6.4 Thermal Information

OPA1637
THERMAL METRIC(1) DGK (VSSOP) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 181.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 68.3 °C/W
RθJB Junction-to-board thermal resistance 102.8 °C/W
ψJT Junction-to-top characterization parameter 10.6 °C/W
ψJB Junction-to-board characterization parameter 101.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

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6.5 Electrical Characteristics

at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = 0 V, input common mode voltage (VICM) = 0 V, RF = 2
kΩ, V PD = VVS+, RL = 10 kΩ(1) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY RESPONSE
SSBW Small-signal bandwidth VO (2) = 100 mVPP, G = –1 V/V 7 MHz
GBP Gain-bandwidth product VO = 100 mVPP, G = –10 V/V 9.2 MHz
FBP Full-power bandwidth VO = –1 VPP, G = –1 V/V 2.5 MHz
SR Slew rate G = –1, 10-V step 15 V/µs
0.1% of final value, G = –1 V/V, VO = 10-V step 1
Settling time µs
0.01% of final value, G = –1 V/V, VO= 10-V step 2
–120 dB
Differential input, f = 1 kHz, VO = 10 VPP
0.0001 %
–115 dB
Single-ended input, f = 1 kHz, VO = 10 VPP
Total harmonic distortion and 0.00018 %
THD+N
noise –112 dB
Differential input, f = 10 kHz, VO = 10 VPP
0.00025 %
–107 dB
Single-ended input, f = 10 kHz, VO = 10 VPP
0.00045 %
Differential input, f = 1 kHz, VO = 10 VPP –126
HD2 Second-order harmonic distortion dB
Single-ended input, f = 1 kHz, VO = 10 VPP –120
Differential input, f = 1 kHz, VO = 10 VPP –131
HD3 Third-order harmonic distortion dB
Single-ended input, f = 1 kHz, VO = 10 VPP –119
Overdrive recovery time G = 5 V/V, 2x output overdrive, dc-coupled 3.3 µs
NOISE
f = 1 kHz 3.7
nV/√ Hz
en Input differential voltage noise f = 10 Hz 4
f = 0.1 Hz to 10 Hz 0.1 µVPP
f = 1 kHz 300
fA/√ Hz
ei Input current noise, each input f = 10 Hz 400
f = 0.1 Hz to 10 Hz 13.4 pAPP
OFFSET VOLTAGE
20 ±200
VIO Input-referred offset voltage µV
TA = –40°C to +125°C ±250
Input offset voltage drift TA = –40°C to +125°C 0.1 ±1 µV/°C
0.025 ±0.5
PSRR Power-supply rejection ratio µV/V
TA = –40°C to +125°C ±1
INPUT BIAS CURRENT
0.2 ±2
IB Input bias current nA
TA = –40°C to +125°C ±4
Input bias current drift TA = –40°C to +125°C 2 ±15 pA/°C
Input offset current 0.2 ±1
IOS nA
TA = –40°C to +125°C ±3
Input offset current drift TA = –40°C to +125°C 1 ±10 pA/°C

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6.5 Electrical Characteristics (continued)

at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = 0 V, input common mode voltage (VICM) = 0 V, RF = 2
kΩ, V PD = VVS+, RL = 10 kΩ(1) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE
Common-mode voltage TA = –40°C to +125°C VVS– + 1 VVS+ – 1 V
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V 140
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V 126 140
CMRR Common-mode rejection ratio
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V dB
120
TA = –40°C to +125°C
INPUT IMPEDANCE
Input impedance differential
VICM = 0 V 1 || 1 GΩ || pF
mode
OPEN-LOOP GAIN
VS = ±2.5 V, VVS– + 0.2 V < VO < VVS+ – 0.2 V 115 120
VS = ±2.5 V, VVS– + 0.3 V < VO < VVS+ – 0.3 V,
110 120
TA = –40°C to +125°C
AOL Open-loop voltage gain dB
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V 115 120
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V,
110 120
TA = –40°C to +125°C
OUTPUT
VS = ±2.5 V ±100

Output voltage difference from VS = ±2.5 V, TA = –40°C to +125°C ±100

mV
supply voltage VS = ±18 V ±230
VS = ±18 V, TA = –40°C to +125°C ±270
ISC Short-circuit current ±31 mA
Differential capacitive load, no output Isolation
CLOAD Capacitive load drive 50 pF
resistors, phase margin = 30°
ZO Open-loop output impedance f = 100 kHz (differential) 14 Ω
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL
VS = ±2.5 V VVS– + 1 VVS+ – 1
Input Voltage Range
VS = ±18 V VVS– + 2 VVS+ – 2
Small-signal bandwidth from
VVOCM= 100 mVPP 2
VOCM pin
MHz
Large-signal bandwidth from
VVOCM = 0.6 VPP 5.7
VOCM pin
VVOCM = 0.5-V step, rising 3.5
Slew rate from VOCM pin V/µs
VVOCM = 0.5-V step, falling 5.5
DC output balance VVOCM fixed midsupply (VO = ±1 V) 78 dB
VOCM input impedance 2.5 || 1 MΩ || pF
VOCM offset from mid-supply VOCM pin floating 2 mV

VOCM common-mode offset VVOCM = VICM, VO = 0 V ±1 ±6

mV
voltage VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C ±10
VOCM common-mode offset
VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C ±20 ±60 µV/°C
voltage drift
POWER SUPPLY
0.95 1.2
IQ Quiescent operating current mA
TA = –40°C to +125°C 1.6

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6.5 Electrical Characteristics (continued)

at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = 0 V, input common mode voltage (VICM) = 0 V, RF = 2
kΩ, V PD = VVS+, RL = 10 kΩ(1) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER DOWN
VVS+ –
V PD(HI) Power-down enable voltage TA = –40°C to +125°C V
0.5
VVS+ –
V PD(LOW) Power-down disable voltage TA = –40°C to +125°C V
2.0
PD bias current V PD = VVS+ – 2 V 1 2 µA
Powerdown quiescent current 10 20 µA
Turn-on time delay VIN = 100 mV, time to VO = 90% of final value 10 µs
Turn-off time delay VIN = 100 mV, time to VO = 10% of original value 15 µs

(1) RL is connected differentially, from OUT+ to OUT–.

(2) VO refers to the differential output voltage, VOUT+ – VOUT–.

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6.6 Typical Characteristics

at VS = ±18 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, VOUT = 2 VPP, G = 1 V/V, and V PD = VS
+ (unless otherwise noted)

100 5000
Input-Referred Voltage Noise (nV/—Hz)

70

Input-Referred Current Noise (fA/—Hz)

50 3000

2000
30
20
1000
10 700
7 500
5
300
3
200
2

1 100
100m 1 10 100 1k 10k 100k 0.1 0.5 2 3 5 10 20 100 1000 10000 100000
Frequency (Hz) Frequency (Hz) D014
D013

Figure 6-1. Input-Referred Voltage Noise vs Figure 6-2. Current Noise vs Frequency
Frequency
-90 0.1 -60
RL = 2 k: RL = 2 k:
Noise (dB)

Total Harmonic Distortion + Noise (dB)

Noise (%)

RL = 10 k: RL = 10 k:
-95
RL = 600 :
0.01 -80
-100
Total Harmonic Distortion
Total Harmonic Distortion

-105
0.001 -100
-110

-115 0.0001 -120

-120

1E-5 -140
-125 10m 100m 1 10
10 100 1k 10k 20k Output Amplitude (VRMS)
Frequency (Hz) D016
D015

f = 1 kHz, VS = ±15 V
VOUT = 3 VRMS, VS = ±15 V

Figure 6-3. Total Harmonic Distortion + Noise vs Figure 6-4. Total Harmonic Noise + Distortion vs
Frequency Amplitude
180 200 50
Gain
160 Phase 160 40
140 120
120 80 30

100 40
Gain (dB)

Gain (dB)
Phase (q)

20
80 0
10
60 -40
40 -80 0
20 -120 G=1
-10 G = 10
0 -160
G = 100
-20 -200 -20
1 10 100 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M
Frequency (Hz) D068 Frequency (Hz) D009

VS = ±15 V, CL = 50 pF VS = ±15 V, CL = 50 pF

Figure 6-5. Open Loop Gain vs Frequency Figure 6-6. Closed-Loop Gain vs Frequency

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180 0.09

Common-Mode Rejection Ratio (PV/V)

Common-Mode Rejection Ratio (dB)

160 0.08
140 0.07
120
0.06
100
0.05
80
0.04
60
0.03
40

20 0.02

0 0.01
10m 100m 1 10 100 1k 10k 100k 1M 10M -40 -25 -10 5 20 35 50 65 80 95 110 125
Frequency (Hz) Temperature (oC) D030
D011

VS = ±15 V

Figure 6-7. Common Mode Rejection Ratio vs Figure 6-8. Common Mode Rejection Ratio vs
Frequency Temperature
180 -0.01
PSRR

Power Supply Rejection Ratio (PV/V)

160 PSRR
Power Supply Rejection Ratio (dB)

140 -0.02
120

100
-0.03
80

60
-0.04
40

20

0 -0.05
10m 100m 1 10 100 1k 10k 100k 1M 10M -40 -25 -10 5 20 35 50 65 80 95 110 125
Frequency (Hz) Temperature (oC) D031
D012

VS = ±15 V

Figure 6-9. Power Supply Rejection Ratio vs Figure 6-10. Power Supply Rejection Ratio vs
Frequency Temperature
40 10000

35 5000
Open-Loop Output Impedance :
Maximum Output Voltage (VPP)

3000
30 2000
1000
25
500
20 300
200
15
100
10 50
5 30
20
0 10
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) D019 Frequency (Hz) D017

VS = ±15 V VS = ±15 V

Figure 6-11. Maximum Output Voltage vs Figure 6-12. Output Impedance vs Frequency
Frequency

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15 15

10 10
Amplifiers (%)

Amplifiers (%)
5 5

0 0
-200 -150 -100 -50 0 50 100 150 200 -200 -150 -100 -50 0 50 100 150 200
Input Offset Voltage (PV) D001
Input Offset Voltage (PV) D061

VS = ±1.5 V VS = ±18 V

Figure 6-13. Input Offset Voltage Histogram Figure 6-14. Input Offset Voltage Histogram
25 20

20
15
Amplifiers (%)

Amplifiers (%)

15
10
10

5
5

0 0
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -6 -4 -2 0 2 4 6
Offset Voltage Drift (PV/qC) D002
Common-Mode Input Offset Voltage (mV) D006

VS = ±15 V VS = ±18 V, VOCM = floating

Figure 6-15. Input Offset Voltage Drift Histogram Figure 6-16. Output Common Mode Voltage Offset
15 2
1.8
1.6
Quiescent Current (mA)

1.4
10
Amplifiers (%)

1.2
1
0.8
5
0.6 -40oC
0.4 25oC
85oC
0.2 125oC

0 0
-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 3 6 9 12 15 18 21 24 27 30 33 36
Common-Mode Input Offset Voltage (mV) D007
Supply Voltage (V) D045

VS = ±18 V, VOCM = 0 V

Figure 6-17. Output Common Mode Voltage Offset Figure 6-18. Quiescent Current vs Supply Voltage

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1.5 1.6
Vs = r1.5 V
1.4 Vs = r18 V
1.4
1.3
Quiescent Current (mA)

Quiescent Current (mA)

1.2
1.2
1.1 1

1 0.8
0.9
0.6
0.8
0.4
0.7
0.6 VS = r18 V 0.2
VS = r1.5 V
0.5 0
-50 -25 0 25 50 75 100 125 150 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Temperature (oC) D065 VS+ Delta from Power Down (V) D053

Figure 6-19. Quiescent Current vs Temperature Figure 6-20. Quiescent Current vs Power-Down
Delta from Supply Voltage
250 500
55oC
200 40oC 400
Input-Referred Offset Voltage (PV)

150 25oC 300

85oC
Input Bias Current (pA)

100 125oC 200

150oC
50 100
0 0
-50 -100
-100 -200
17 V 17 V IB
-150 -300
IB+
-200 -400 IOS
-250 -500
-18 -14 -10 -6 -2 2 6 10 14 18 -18 -14 -10 -6 -2 2 6 10 14 18
Input Common-Mode Voltage (V) D023
Input Common-Mode Voltage (V) D025

Figure 6-21. Input Offset Voltage vs Input Figure 6-22. Input Bias Current vs Input Common-
Common-Mode Voltage Mode Voltage
500 30
450 IB
IB+
400 IOS 28
350
Input Bias Current (pA)

Output Voltage (V)

300
250 26
200
150 24
100
50 40qC
22 125qC
0 25qC
-50 85qC
-100 20
3 6 9 12 15 18 21 24 27 30 33 36 0 5 10 15 20 25 30 35 40
Supply Voltage (V) D027
Output Current (mA) D028

Figure 6-23. Input Bias Current vs Supply Voltage Figure 6-24. Output Voltage vs Output Current

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-20 128
40qC
125qC 126
-22 25qC 124
85qC

Open-Loop Gain (dB)

122
Output Voltage (V)

-24 120
118

-26 116
114
25 qC
-28 112 85 qC
125 qC
110 40 qC
-30 108
-40 -35 -30 -25 -20 -15 -10 -5 0 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7
Output Current (mA) Output Voltage Delta from Supply Voltage, VS+/VS (V) D049
D029

Figure 6-25. Output Voltage vs Output Current Figure 6-26. Open-Loop Gain vs Ouput Delta From
Supply
20 20
RISO = 0 : RISO = 0 :
17.5 RISO = 25 : RISO = 25 :
RISO = 50 : RISO = 50 :
15 15
Overshoot (%)

Overshoot (%)

12.5

10 10

7.5

5 5

2.5

0 0
20 40 60 80 100 120 140 160 180 0 50 100 150 200 250 300 350 400
Capacitive Load (pF) D036 Capacitive Load (pF) D037

AV = 1 AV = 10

Figure 6-27. Small-Signal Overshoot vs Capacitive Figure 6-28. Small-Signal Overshoot vs Capacitive
Load Load
20 50
40
17 30
Short-Circuit Current (mA)

20
Slew Rate (V/Ps)

14 10 IOUT (sinking)
IOUT (sourcing)
0 IOUT (sourcing)
-10 IOUT (sinking)
11
-20
8 -30
Falling Edge
Rising Edge -40
5 -50
3 6 9 12 15 18 21 24 27 30 33 36 -25 -10 5 20 35 50 65 80 95 110 125
Supply Voltage (V) Temperature (oC) D048
D041

Figure 6-29. Output Slew Rate vs Supply Voltage Figure 6-30. Short-Circuit Current vs Temperature

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3 1.1
2.5 1.08
2
1.06
1.5
1.04
1
Voltage (V)

Voltage (V)
0.5 1.02
VOUT
0 VOUT 1
-0.5 0.98
-1
0.96
-1.5
-2 0.94
VVOCM
-2.5 0.92 (VOUT VOUT )/2
-3 0.9
Time (1 Ps/div) Time (5 Ps /div)
D044 D054

Figure 6-31. Large-Signal Step Response Figure 6-32. Output Common-Mode Step
Response, Rising
0.1
VVOCM VIN
0.08 (VOUT VOUT )/2 VOUT
VOUT
0.06
Voltage (50 mV/div)
0.04
Voltage (V)

0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
Time (5 Ps / div) Time (500 ns/div)
D055
D043

Figure 6-33. Output Common-Mode Step Figure 6-34. Small-Signal Step Response, Falling
Response, Falling
VOUT Delta to Final Value (250 PV/div)

+0.01
Settling
Threshold
Voltage (50 mV/div)

0.01%
VIN Input Settling
VOUT Transition Threshold
VOUT

Time (500 ns/div) Time (250 ns/div)

D042 D046

Figure 6-35. Small-Signal Step Response, Rising Figure 6-36. Output Settling Time to ±0.01%

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18 0.3 18 0.3
VPD
15 0.25 15 VOUT 0.2
Power-down Voltage, VPD (V)

Power-down Voltage, VPD (V)

Output Voltage, VOUT (V)

Output Voltage, VOUT (V)

12 0.2 12 0.1

9 0.15 9 0

6 0.1 6 -0.1

3 0.05 3 -0.2

0 0 0 -0.3

-3 VPD -0.05
-3 -0.4
VOUT
-6 -0.1 -6 -0.5
Time (1 Ps/div) Time (1 Ps/div)
D050 D051

Figure 6-37. Power-Down Time (PD Low to High) Figure 6-38. Power-Down Time (PD High to Low)

VIN VIN
VOUT VOUT
VOUT VOUT
Voltage (5 V/div)

Voltage (5 V/div)

Time (20 Ps/div) Time (20 Ps/div)

D039 D040

Figure 6-39. Output Negative Overload Recovery Figure 6-40. Output Positive Overload Recovery

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7 Parameter Measurement Information

7.1 Characterization Configuration
The OPA1637 provides the advantages of a fully differential amplifier (FDA) configuration that offers very low
noise and harmonic distortion in a single, low-power amplifier. The FDA is a flexible device, where the main aim
is to provide a purely differential output signal centered on a user-configurable, common-mode voltage that is
usually matched to the input common-mode voltage required by an analog-to-digital converter (ADC) or class-D
amplifier. The circuit used for characterization of the differential-to-differential performance is seen in Figure 7-1.
VIN±
RI RF
2k 2k VOUT+

RISO
± VVS+ 0
VIDIFF/2
+
VVOCM
± +
+ RL
+ OPA1637 CL VOUT
± RISO 10 k DNP
VCM ± ± + 0 ±
+ VIDIFF/2
RI
VVS± VPD
2k

RF VOUT±
2k
VIN+
All voltages except VIN and VOUT are
referenced to ground.

Figure 7-1. Differential Source to a Differential Gain of a 1-V/V Test Circuit

A similar circuit is used for single-ended to differential measurements, as shown in Figure 7-2.
VIN±
RI RF
2k 2k VOUT+

RISO
VVS+ 0

VVOCM
± +
+ RL
OPA1637 CL VOUT
± RISO 10 k DNP
+ 0 ±
RI VVS± VPD
2k
+
VIN ± RF VOUT±
2k
VIN+ All voltages except VOUT are
referenced to ground.

Figure 7-2. Single-Ended to Differential Gain of a 1-V/V Test Circuit

The FDA requires feedback resistor for both output pins to the input pins. These feedback resistors load the
output differentially only if the input common-mode voltage is equal to the output common-mode voltage set by
VOCM. When VOCM differs from the input common-mode range, the feedback resistors create single-ended
loading. The characterization plots fix the RF (RF1 = RF2) value at 2 kΩ, unless otherwise noted. This value can
be adjusted to match the system design parameters with the following considerations in mind:
• The current needed to drive RF from the peak output voltage to the input common-mode voltage adds to the
overall output load current. If the total load current (current through RF + current through RL) exceeds the
current limit conditions, the device enters a current limit state, causing the output voltage to collapse.
• High feedback resistor values (RF> 100 kΩ) interact with the amplifier input capacitance to create a zero in
the feedback network. Compensation must be added to account for this potential source of instability; see the
TI Precision Labs FDA Stability Training for guidance on designing an appropriate compensation network.

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8 Detailed Description
8.1 Overview
The OPA1637 is a low-noise, low-distortion fully-differential amplifier (FDA) that features Texas Instrument's
super-beta bipolar input devices. Super-beta input devices feature very low input bias current as compared to
standard bipolar technology. The low input bias current and current noise makes the OPA1637 an excellent
choice for audio applications that require low-noise differential signal processing without significant current
consumption. This device is also designed for analog-to-digital audio input circuits that require low noise in a
single fully-differential amplifier. This device achieves lower current consumption at lower noise levels than what
is achievable with two low-noise amplifiers. The OPA1637 also features high-voltage capability, which allows the
device to be used in ±15-V supply circuits without any additional voltage clamping or regulators. This feature
enables a direct, single amplifier for a 24-dBm differential output drive (commonly found on mixers and digital
audio interfaces) without any additional amplification.
8.2 Functional Block Diagram
VS+

OUT+
IN± ±
Low Noise +
Differential I/O
Amplifier ±
IN+ +
OUT±

VS±
VS+

5M

±
VCM
1 µA Error
Amplifier
+ VOCM
PD
5M

VS±

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8.3 Feature Description

8.3.1 Super-Beta Input Bipolar Transistors
The OPA1637 is designed on a modern bipolar process that features TI's super-beta input transistors. Traditional
bipolar transistors feature excellent voltage noise and offset drift, but suffer a tradeoff in high input bias current
(IB) and high input bias current noise. Super-beta transistors offer the benefits of low voltage noise and low offset
drift with an order of magnitude reduction in input bias current and reduction in input bias current noise. For
audio circuits, input bias current noise can dominate in circuits where higher resistance input resistors are used.
The OPA1637 enables a fully-differential, low-noise amplifier design without restrictions of low input resistance at
a power level unmatched by traditional single-ended amplifiers.
8.3.2 Power Down
The OPA1637 features a power-down circuit to disable the amplifier when a low-power mode is required by the
system. In the power-down state, the amplifier outputs are in a high-impedance state, and the amplifier total
quiescent current is reduced to less than 20 µA.
8.3.3 Flexible Gain Setting
The OPA1637 offers considerable flexibility in the configuration and selection of resistor values. Low input bias
current and bias current noise allows for larger gain resistor values with minimal impact to noise or offset. The
design starts with the selection of the feedback resistor value. The 2-kΩ feedback resistor value used for the
characterization curves is a good compromise among power, noise, and phase margin considerations. With the
feedback resistor values selected (and set equal on each side), the input resistors are set to obtain the desired
gain, with the input impedance also set with these input resistors. Differential I/O designs provide an input
impedance that is the sum of the two input resistors. Single-ended input to differential output designs present a
more complicated input impedance. Most characteristic curves implement the single-ended to differential design
as the more challenging requirement over differential-to-differential I/O.
8.3.4 Amplifier Overload Power Limit
In many bipolar-based amplifiers, the output stage of the amplifier can draw significant (several milliamperes) of
quiescent current if the output voltage becomes clipped (meaning the output voltage becomes limited by the
negative or positive supply voltage). This condition can cause the system to enter a high-power consumption
state, and potentially cause oscillations between the power supply and signal chain. The OPA1637 has an
advanced output stage design that eliminates this problem. When the output voltage reaches the VVS+ or VVS–
voltage, there is virtually no additional current consumption from the nominal quiescent current. This feature
helps eliminate any potential system problems when the signal chain is disrupted by a large external transient
voltage.
8.4 Device Functional Modes
The OPA1637 has two functional modes: normal operation and power-down. The power-down state is enabled
when the voltage on the power-down pin is lowered to less than the power-down threshold. In the power-down
state, the quiescent current is significantly reduced, and the output voltage is high-impedance. This high
impedance can lead to the input voltages (+IN and –IN) separating, and forward-biasing the ESD protection
diodes. See Section 9 for guidance on power-down operation.

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

Most applications for the OPA1637 strive to deliver the best dynamic range in a design that delivers the desired
signal processing along with adequate phase margin for the amplifier. The following sections detail some of the
design issues with analysis and guidelines for improved performance.
9.1.1 Driving Capacitive Loads
The capacitive load of an ADC, or some other next-stage device, is commonly required to be driven. Directly
connecting a capacitive load to the output pins of a closed-loop amplifier such as the OPA1637 can lead to an
unstable response. One typical remedy to this instability is to add two small series resistors (RISO) at the outputs
of the OPA1637 before the capacitive load. Good practice is to leave a place for the RISO elements in a board
layout (a 0-Ω value initially) for later adjustment, in case the response appears unacceptable.
For applications where the OPA1637 is used as an output device to drive an unknown capacitive load, such as a
cable, RISO is required. Figure 9-1 shows the required RISO value for a 40-degree phase-margin response. The
peak required RISO value occurs when CL is between 500 pF and 1 nF. As CL increases beyond 1 nF, the
bandwidth response of the device reduces, resulting in a slower response but no major degradation in phase
margin. For a typical cable type, such as Belden 8451, capacitive loading can vary from 340 pF (10-foot cable) to
1.7 nF (50-foot cable). Selecting RISO to be 100 Ω provides sufficient phase margin regardless of the cable
length. RISO can also be used within the loop feedback of the amplifier; however, simulation must be used to
verify the stability of the system.
100
90
Isolation Resistance, RISO (:)

80
70
60
50
40
30
20
10
0
100 p 1n 10 n 100 n
Load Capacitance, CL (F) D069

Figure 9-1. Required Isolation Resistance vs Capacitive Load for a 40° Phase Margin

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9.1.2 Operating the Power-Down Feature

The power-down feature on the OPA1637 allows the device to be put into a low power-consumption state, in
which quiescent current is minimized. To force the device into the low-power state, drive the PD pin lower than
the power-down threshold voltage (VVS+ – 2 V). Driving the PD pin lower than the power-down threshold voltage
forces the internal logic to disable both the differential and common-mode amplifiers. The PD pin has an internal
pullup current that allows the pin to be used in an open-drain MOSFET configuration without an additional pullup
resistor, as seen in Figure 9-2. In this configuration, the logic level can be referenced to the MOSFET, and the
voltage at the PD pin is level-shifted to account for use with high supply voltages. Be sure to select an N-type
MOSFET with a maximum BVDSS greater than the total supply voltage. For applications that do not use the
power-down feature, tie the PD pin to the positive supply voltage.

VS+

1 µA

To
PD
Enabled amplifier
core
MOSFET
THRESHOLD Powerdown
OPA1637
GND

Figure 9-2. Power-Down ( PD) Pin Interface With Low-Voltage Logic Level Signals

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When PD is low (device is in power down) the output pins will be in a high-impedance state. When the device is
in the power-down state, the outputs are high impedance, and the output voltage is no longer controlled by the
amplifier, but dependant on the input and load configuration. In this case, the input voltage between IN– and IN+
can drift to a voltage that may forward-bias the input protection diodes. Take care to avoid high currents flowing
through the input diodes by using an input resistor to limit the current to less than 10 mA. In Figure 9-3, the
OPA1637 is configured in a differential gain of 5 with 100-Ω input resistors. When the device enters power down,
the voltage between IN– and IN+ increases until the internal protection diode is forward-biased. In this case,
exceeding a voltage on VIN with RIN= 0 Ω of 2.5 V (diode forward voltage estimated at 0.5 V) results in a current
greater than 10 mA. To avoid this high current, select RIN so that the maximum current flow is less than 10 mA
when VIN is at maximum voltage.
500
100

RIN +10 V
VIN
±
High± Z
+
VOCM
±
High± Z
+ PD

RIN
±10 V

100
500

Figure 9-3. Path of Input Current Flow When PD = Low

9.1.3 I/O Headroom Considerations

The starting point for most designs is to assign an output common-mode voltage for the OPA1637. For ac-
coupled signal paths, this voltage is often the default midsupply voltage to retain the most available output swing
around the voltage centered at the VOCM voltage. For dc-coupled designs, set this voltage with consideration to
the required minimum headroom to the supplies, as described in the specifications for the VOCM control. For
precision ADC drivers, this VOCM output becomes the VCM input to the ADC. Often, VCM is set to VREF / 2 to
center the differential input on the available input when precision ADCs are being driven.
From target output VOCM, the next step is to verify that the desired output differential peak-to-peak voltage,
VOUTPP, stays within the supplies. For any desired differential VOUTPP, make sure that the absolute maximum
voltage at the output pins swings with Equation 1 and Equation 2, and confirm that these expressions are within
the supply rails minus the output headroom required for the RRO device.

VOUTPP
VOUTMIN = VOCM ±
4 (1)

VOUTPP
VOUTMAX = VOCM +
4 (2)

With the output headroom confirmed, the input junctions must also stay within the operating range. The input
range limitations require a maximum 1.0-V headroom from the supply voltages (VS+ and VS–) over the full
temperature range.

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9.1.4 Noise Performance

The first step in the output noise analysis is to reduce the application circuit to the simplest form with equal
feedback and gain setting elements to ground. Figure 9-4 shows the simplest analysis circuit with the FDA and
resistor noise terms to be considered.

enRg2 enRf2
RG RF

r
In+2

+
eno2
2 ±
In±

eni2
enRg2 enRf2
RG RF
r

r
Figure 9-4. FDA Noise Analysis Circuit

The noise powers are shown in Figure 9-4 for each term. When the RF and RG (or RI) terms are matched on
each side, the total differential output noise is the root sum squared (RSS) of these separate terms. Using NG ≡
1 + RF / RG, the total output noise is given by Equation 3. Each resistor noise term is a 4kT × R power (4kT =
1.6E-20 J at 290 K).

2 2
eo eniNG 2 iNRF 2 4kTRFNG (3)

The first term is simply the differential input spot noise times the noise gain. The second term is the input current
noise terms times the feedback resistor (and because there are two uncorrelated current noise terms, the power
is two times one of them). The last term is the output noise resulting from both the RF and RG resistors, at again,
twice the value for the output noise power of each side added together. Running a wide sweep of gains when
holding RF to 2 kΩ gives the standard values and resulting noise listed in Table 9-1. When the gain increases,
the input-referred noise approaches only the gain of the FDA input voltage noise term at 3.7 nV/√ Hz.
Table 9-1. Swept Gain of the Output- and Input-Referred Spot Noise Calculations
GAIN (V/V) RF (Ω) RG1 (Ω) AV EO (nV/√ Hz) EI (nV/√ Hz)
0.1 2000 20000 0.1 9.4 93.9
1 2000 2000 1 13.6 13.6
2 2000 1000 2 17.8 8.9
5 2000 402 4.98 29.5 5.9
10 2000 200 10 48.6 4.9

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9.2 Typical Applications

9.2.1 Current-Output Audio DAC Buffer to Class-D Amplifier
RF1
1k

CF1
3.3 nF C2
RISO1
1 µF
75
RI1 INPUT_A
5V 49 5V

± TPA3251
PCM1795 IOUTL/R+ ± 3.5 V + CDF
Class D
C5 OPA1637 10 nF
Audio DAC IOUTL/R± ± ADC
Amplifier
1 µF + PD C3
1 µF
GND
±10 V RI2 ±10 V 5 V INPUT_B
49 RISO2
75
CF2
RF2
3.3 nF
1k GND

Figure 9-5. Differential Current-to-Voltage Converter

9.2.1.1 Design Requirements

The requirements for this application are:
• Differential current-to-voltage conversion and filtering
• 1-kmho transimpedance gain
• 40-kHz Butterworth response filter
• 0-V dc common-mode voltage at DAC output
9.2.1.2 Detailed Design Procedure
This design provides current-to-voltage conversion from a current-output audio DAC into a voltage-input, class-D
amplifier. The order of design priorities are as follows:
• Select feedback-resistor values based on the gain required from the current-output stage to the voltage-input
stage. For this design, the full-scale, peak-to-peak output current of the PCM1795 ( IOUTL/R+ – IOUTL/R–) is ±4
mA. A gain of 1k gives a wide voltage swing of ±4 V, allowing for high SNR without exceeding the input
voltage limit of the TPA3251.
• After the gain is fixed, select the output common-mode voltage. The output common-mode voltage
determines the input common-mode voltage in this configuration. To set the nominal output voltage of the
PCM1795 to 0 V (which corresponds to the input common mode voltage of the OPA1637), shift the output
negatively from the desired common-mode input voltage by the gain multiplied by the dc center current value
of the PCM1795 (3.5 mA). In this case, –3.5 V satisfies the design goal.
• A bypass capacitor from the VOCM pin to ground must be selected to filter noise from the voltage divider.
The capacitor selection is determined by balancing the startup time of the system with the output common-
mode noise. A higher capacitance gives a lower frequency filter cutoff on the VOCM pin, thus giving lower
noise performance, but also slows down the initial startup time of the circuit as a result of the RC delay from
the resistor divider in combination with the filter capacitor.
• Select CF so that the desired bandwidth of the active filter is achieved. The 3-dB frequency is determined by
the reciprocal of the product of RF and CF.
• Use a passive filter on the output to increase noise filtering beyond the desired bandwidth. The passive filter
formed by RD1,2 and CDF adds an additional real pole to the filter response. If the pole is designed at the
same frequency as the active filter pole, the overall 3-dB frequency shifts to a lower frequency value, and the
step response is overdamped. A trade-off must be made to give optimal transient response versus increased
filter attenuation at higher frequencies. For this design, the second pole is set to 106 kHz.

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9.2.1.3 Application Curves

The simulated response of the current-to-voltage audio DAC buffer can be seen in Figure 9-6 and Figure 9-7.

90 0 1.2
Gain 1.05 VOUT
75 Phase -30 VIN
0.9
60 -60 0.75
0.6
45 -90
0.45
30 -120 0.3
Gain (dB)

Phase (q)

Voltage (V)
0.15
15 -150
0
0 -180 -0.15
-0.3
-15 -210
-0.45
-30 -240 -0.6
-0.75
-45 -270 -0.9
-60 -300 -1.05
100 1k 10k 100k 1M -1.2
Frequency (Hz) C105
0 20 40 60 80 100 120 140 160 180 200
Time (Ps)
Figure 9-6. Gain and Phase Response for Current-
C105

to-Voltage Buffer Figure 9-7. Transient Response for Current-to-

Voltage Buffer

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9.2.2 An MFB Filter Driving an ADC Application

A common application use case for fully-differential amplifiers is to easily convert a single-ended signal into a
differential signal to drive a differential input source, such as an ADC or class-D amplifier. Figure 9-8 shows an
example of the OPA1637 used to convert a single-ended, low-voltage signal audio source, such as a small
electret microphone, and deliver a low-noise differential signal that is common-mode shifted to the center of the
ADC input range. A multiple-feedback (MFB) configuration is used to provide a Butterworth filter response, giving
a 40-dB/decade rolloff with a –3-dB frequency of 30 kHz.
RF1
3.65 k

CF1
RI1 RG1
1 nF
732 604 RO1 RA1 CA1
20 100 47 pF

+5 V
VIN
±
+ CA2
6.2 nF VOCM FDA ADC
± 1 nF
+ PD

±5 V VS+
RO2 RA2 CA3
20 100 47 pF
RI2 RG2 CF2
732 604 RF2
1 nF
3.65 k

Figure 9-8. Example 30-kHz Butterworth Filter

9.2.2.1 Design Requirements

The requirements for this application are:
• Single-ended to differential conversion
• 5-V/V gain
• Active filter set to a Butterworth, 30-kHz response shape
• Output RC elements set by SAR input requirements (not part of the filter design)
• Filter element resistors and capacitors are set to limit added noise over the OPA1637 and noise peaking
9.2.2.2 Detailed Design Procedure
The design proceeds using the techniques and tools suggested in the Design Methodology for MFB Filters in
ADC Interface Applications application note. The process includes:
• Scale the resistor values to not meaningfully contribute to the output noise produced by the OPA1637.
• Select the RC ratios to hit the filter targets when reducing the noise gain peaking within the filter design.
• Set the output resistor to 100 Ω into a 1-nF differential capacitor.
• Add 47-pF common-mode capacitors to the load capacitor to improve common noise filtering.
• Inside the loop, add 20-Ω output resistors after the filter feedback capacitor to increase the isolation to the
load capacitor.

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9.2.2.3 Application Curves

The gain and phase plots are shown in Figure 9-9. The MFB filter features a Butterworth responses feature very
flat passband gain, with a 2-pole roll-off at 30 kHz to eliminate any higher-frequency noise from contaminating
the signal chain, and potentially alias back into the audio band.

20 120
16 90
12 60
8 30

Gain (dB) 4 0

Phase (q)
0 -30
-4 -60
-8 -90
-12 -120
-16 Gain -150
Phase
-20 -180
100 1k 10k 100k
Frequency (Hz) C100

Figure 9-9. Gain and Phase Plot for a 30-kHz Butterworth Filter

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9.2.3 Differential Microphone Input to Line Level

Professional dynamic microphones typically feature low output impedance to minimize noise coupling on the
microphone cable. Interfacing the microphone with high-impedance circuitry typically requires the use of an
impedance conversion stage, often done with a transformer or discrete amplifiers. The flexibility of the OPA1637
allows the device to be configured with a low differential input impedance and 20 dB of gain, simplifying the
impedance conversion and gain stage into a single device. Figure 9-10 shows an example of a differential, low
input impedance, microphone level voltage (10 mV to 100 mV) amplifier to a line-level amplitude signal that also
has adjustable dc common-mode shift capability. This design example shows how the OPA1637 makes a great
choice for driving an ADC class-D amplifier.
RF1
Dynamic 750
Microphone
CF1
RG1
4.7 nF
75 RISO1
100

XLR +15
Cable
±
To ADC/
1
1

VIN +
3

VOCM FDA Class D Amplifier/

2

± XLR output
+ PD

-15 +15
RISO2
100
RG2 CF2
75 4.7 nF

RF2
750

Figure 9-10. Fully Differential, Low-Noise, 20-dB Microphone Gain Block With DC Shift

9.2.3.1 Application Curves

2.5
VOUT-
2 VOUT+
1.5
1
Output Voltage (V)

0.5
0
-0.5
-1
-1.5
-2
-2.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (ms) D075

VOCM = 0 V

Figure 9-11. Output Waveform of the Microphone Amplifier

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10 Power Supply Recommendations

The OPA1637 operates from supply voltages of 3.0 V to 36 V (±1.5 V to ±18 V, dual supply). Connect ceramic
bypass capacitors from both VS+ and VS– to GND.
11 Layout
11.1 Layout Guidelines
11.1.1 Board Layout Recommendations
• Keep differential signals routed together to minimize parasitic impedance mismatch.
• Connect a 0.1-µF capacitor to the supply nodes through a via.
• Connect a 0.1-µF capacitor to the VOCM pin if no external voltage is used.
• Keep any high-frequency nodes that can couple through parasitic paths away from the VOCM node.
• Clean the PCB board after assembly to minimize any leakage paths from excess flux into the VOCM node.
11.2 Layout Example
Connect IN+/IN± through
input resistors on the top
VIN layer. Maintain symmetry
between traces and
RIN RIN routing to minimize
common mode coupling.

Route the VOCM pin

connection through a via. IN± IN+
RF RF Connect the powerdown
Connect a 0.1 µF
pin through a via. If
capacitor to VOCM if no VOCM PD
powerdown is not
external voltage is used CCM needed, leave floating.
to set the output common VS+ VS±
mode voltage.
CBYPASS OUT+ OUT± CBYPASS

Connect bypass
capacitors through a via.
VOUT
Figure 11-1. Example Layout

Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 27

Product Folder Links: OPA1637
OPA1637
SBOSA00B – DECEMBER 2019 – REVISED AUGUST 2020 www.ti.com

12 Device and Documentation Support

12.1 Device Support
12.1.1 Development Support
• OPA1637 TINA-TI™ model
• TINA-TI Gain of 0.2 100kHz Butterworth MFB Filter
• TINA-TI 100kHz MFB filter LG test
• TINA-TI Differential Transimpedance LG Sim
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias
Current Op Amp with e-trim™ data sheet
• Texas Instruments, OPA161x SoundPlus™ High-Performance, Bipolar-Input Audio Operational Amplifiers
data sheet
• Texas Instruments, Design Methodology for MFB Filters in ADC Interface Applications application report
• Texas Instruments, Design for Wideband Differential Transimpedance DAC Output application report
• Texas Instruments, PCM1795 32-Bit, 192-kHz Sampling, Advanced Segment, Stereo Audio Digital-to-Analog
Converter data sheet
• Texas Instruments, TPA3251 175-W Stereo, 350-W Mono PurePath™ Ultra-HD Analog Input Class-D
Amplifier data sheet
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
Burr-Brown™ and TI E2E™ are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: OPA1637

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA1637DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1637

OPA1637DGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1637

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1637DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA1637DGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Jul-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA1637DGKR VSSOP DGK 8 2500 366.0 364.0 50.0
OPA1637DGKT VSSOP DGK 8 250 366.0 364.0 50.0

Pack Materials-Page 2
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