TECHNOLOGICAL UNIVERSITY OF THE PHILIPPINES VISAYAS

Capt. Sabi St., City of Talisay, Negros Occidental

College of Automation and Control

Office of the Dean

LEARNING MODULE

ECE 234: Electronics 2: Electronic

Circuit Analysis and Design

DEPARTMENT: MECHATRONICS ENGINEERING TECHNOLOGY

PREPARED BY:

CHARISSE S. JERUTA, MECE

2022

This module is a property of Technological University of the Philippines Visayas and intended
for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
 VISION

The Technological University of the Philippines shall be the premier state university
with recognized excellence in engineering and technology at par with leading universities in
the ASEAN region.

MISSION

The University shall provide higher and advanced vocational, technical, industrial,
technological and professional education and training in industries and technology, and in
practical arts leading to certificates, diplomas and degrees.
It shall provide progressive leadership in applied research, developmental studies in
technical, industrial, and technological fields and production using indigenous materials;
effect technology transfer in the countryside; and assist in the development of small-and-
medium scale industries in identified growth center. (Reference: P.D. No. 1518, Section 2)

QUALITY POLICY

The Technological University of the Philippines shall commit to provide quality

higher and advanced technological education; conduct relevant research and extension
projects; continually improve its value to customers through enhancement of personnel
competence and effective quality management system compliant to statutory and regulatory
requirements; and adhere to its core values.

CORE VALUES

T - Transparent and participatory governance

U - Unity in the pursuit of TUP mission, goals, and objectives
P - Professionalism in the discharge of quality service
I - Integrity and commitment to maintain the good name of the University
A - Accountability for individual and organizational quality performance
N - Nationalism through tangible contribution to the rapid economic growth of the
country
S - Shared responsibility, hard work, and resourcefulness in compliance to the
mandates of the university

This module is a property of Technological University of the Philippines Visayas and intended
for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
 ii

TABLE OF CONTENTS
Page Numbers
TUP Vision, Mission, Quality Policy, and Core Values………………………i
Table of Contents………………………………………………………………..ii
Course Description……………………………………………………….iii
Learning Outcomes………………………………………………………v
General Guidelines/Class Rules………………………………………….v
Grading System…………………………………………………………..vi
Learning Guide (Week No. 2) ………………….……………………….1
Topic/s……………………………………………………………..1
Expected Competencies……………………………………………1
Content/Technical Information ……………………………………1
Progress Check…… ……………………………………………….18
References………………………………………………………….19
Learning Guide (Week No. 3-4)…………………………………………...20
Topic/s……………………………………………………………..20
Expected Competencies…………………………………………….20
Content/Technical Information…………………………………….20
Progress Check…….……………………………………………….47
References………………………………………………………….48

This module is a property of Technological University of the Philippines Visayas and intended
for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
 iii

COURSE DESCRIPTION

This subject provides advance knowledge and understanding in electronics

amplifiers specially using BJT and FET. It also deals with frequency response of the system
and multi-stage amplifier, feedback system, differential amplifier and operational amplifier.

Course Requirement:

Students should:
1. Attend all lectures, practical activity and demonstrations.
2. Participate in all class discussions and laboratory experiment.
3. Complete all assignments, practical activity and submit all requirements on of before
due dates.

Note: Special Exam and quiz is given to those with medical certificate noted by the clinic
or letter of excuse signed by the parent or guardian.

Learning Plan:
Week Learning Methodologies
Content/ Topics Assessment Tools
Nos. Outcomes & Strategies
TUP Vision and Mission, Goals, Lecture/Discussi
and Quality Policy on

Mechatronics Engineering
Technology (BETMxT) Program
Educational Objectives and Power point
presentation, Recitation of TUPV
Program Outcomes Mission and Vision
Module
1 LO1 Course Overview using the Course
Syllabus

Course Outcomes and Learning

Outcomes

Introduction to electronic circuit

analysis and design.

Basic BJT Amplifiers: biasing Lecture/Discussi

schemes, load line concept, on Power point
analyses and design of CC, CE, and presentation, Quiz, Laboratory Activity
2 LO1
CB configuration Module

Activity
FET amplifiers: biasing of JFET Lecture/Demons
and MOSFET, analyze and design tration Power Quiz, Laboratory Activity
3-4 LO1
of common source, common drain point
and common gate amplifier presentation,

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for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
 iv

configuration Module

Activity

5 LO1 PRELIM EXAMINATION Written Exam

Lecture/Demons
tration Power
Power Amplifiers: Class A, B, C,
point
AB, D and S power amplifiers.
presentation, Quiz, Laboratory Activity
6 LO2
Module
Positive and Negative Feedback and
Oscillators
Activity

Frequency response amplifiers: Lecture/Demons

- low frequency response of BJT tration Power
and FET amplifiers point
Quiz, Laboratory Activity
LO3 - lower cut off frequency presentation,
7-8 - high frequency response of Module
BJT amplifiers
- wide band amplifiers Activity

9 LO2, LO3 MID-TERM EXAM Written Exam

Differential Amplifiers Lecture/Demons

- DC Bias tration Power
- AC Input Circuit point
- Common Mode presentation, Quiz, Laboratory Activity
10 LO4 Module
Project Making
Activity

Operational Amplifier
- Ideal vs. Practical
- Configuration Lecture/Demons
• inverting tration Power
• non-inverting point Quiz, Laboratory Activity
11-13 LO4 • voltage follower presentation,
- Negative Feedback Module Project Making
- Basic Op-Amp Circuit
• Comparator Activity
• Summing
• Integrator Differentiator

14 LO4 END-TERM EXAM Written Exam

This module is a property of Technological University of the Philippines Visayas and intended
for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
 v

LEARNING OUTCOMES

LO1. Explain the theory of operation of amplifier using BJT and FET.

LO2. Explain the relevance of both positive and negative feedback system and oscillators.

LO3. Analyze the frequency response of a system and multi-stage amplifier.

LO4. Analyze and design simple discrete amplifier circuits with BJT/FET/ Operational Amplifier.

GENERAL GUIDELINES/CLASS RULES

1. Make-up exams and quizzes will be given only with prior approval of the instructor
and under exceptional circumstances. For excused absences during the exam, the
university policy will be followed.

2. Students are not allowed to leave the classroom once the class has started, unless
extremely necessary. Students who leave the classroom without any valid reason will
be marked absent.

3. Students are expected to comply strictly with the university rule on dress code, class
tardiness and attendance.

4. Cell phones or any e-gadgets must be switched off or put in a silent mode during class
hours, except when allowed by the instructor for activities that require use of such
gadgets.

5. Homework’s or projects submitted later than the two-week allowance or more on

exceptional cases will not anymore be accepted. Students are expected to maintain
complete honesty and integrity in their academic work. Acts of academic dishonesty,
such as cheating, plagiarism, or inappropriately using the work of others to satisfy
course requirements, will not be tolerated and may result in failure of the affected
assignments and/or failure of this class.

Students with Special Needs:

A student with special medical needs is advised to inform the instructor as to

how he/she can best assist him/her. All information will be considered confidential.

This module is a property of Technological University of the Philippines Visayas and intended
for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
 vi

GRADING SYSTEM
The student will be graded according to the following:

Preliminary examination - 30%

Midterm examination - 30%
Final examination - 40%
_____________
100%

Final Grade = Prelim Weighted Score + Midterm Weighted Score + Final Weighted Score

The passing grade for this course is 5.0.

This module is a property of Technological University of the Philippines Visayas and intended
for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
 1

LEARNING GUIDE

Week No.: __2__

TOPIC/S:
Basic BJT Amplifiers
▪ Biasing schemes
▪ Load line concept
▪ Analyses and design of CC, CE, and CB configuration.

EXPECTED COMPETENCIES
After completing this learning guide, the students will be able to:

1. Differentiate the three BJT configurations,

2. Explain the operation of basic BJT amplifier, and
3. Explain the BJT biasing schemes.

CONTENT/TECHNICAL INFORMATION

Definition of Terms

Active Region
It represents the region under which the BJT operates as an amplifier.

Bipolar
It involves two carriers in conduction: both holes and free electrons.

Cut – off
It represents the region under which the BJT operates as a normally open
switch.

Configuration
It refers to how a BJT is connected with other components to operate in a
specific region of operation

Construction
It refers to how the inside or crystal structures of BJT are arranged, either

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for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
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PNP or NPN.

Common Base
BJT configuration where the base terminal is directly connected to or nearest to
the ground.

Common Collector
BJT configuration where the collector terminal is directly connected to or nearest
to the ground.
Common Emitter
BJT configuration where the emitter terminal is directly connected to or nearest
to the ground.

Forward Bias
Establish by connecting the positive terminal of the applied voltage source to
the P-type material and negative side of the to the N-type material.
Supports flow of charge in a device.

Reverse Bias
Establish by connecting the negative terminal of the applied voltage source to
the P-type material and positive side of the to the N-type material.
Turns off the device.

Majority Carrier
It refers to the free electrons for n-type and holes for p-type semiconductor
materials

Minority Carrier
It refers to the holes for n-type and free electrons for p-type semiconductor
materials

Saturation
It represents the region under which the BJT operates as a normally close
switch.

Transistor
Typically a three terminal device capable of amplifying weak signals.

Discussion

Construction

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for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
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Because of the discovery of the very first transistor, the point-contact transistor,
the advantages of using a three-terminal solid state device became well-known. In the
afternoon of December 23, 1947, scientists working at Bell Laboratories namely, John
Bardeen, Walter Brattain and William Shockley introduced to the world the very first
amplifying action. Four years after, Shockley, invented the first junction transistor. This
transistor presented some advantages over the existing vacuum tube which were previously
discussed. Without its discovery, miniaturization would not be possible.

Bipolar Junction Transistor (BJT) or sometimes referred to as junction transistor is

a three-terminal, two junctions, three layer semiconductor device. It is a current-controlled
device, thus the output current is controlled by the input current. Its three terminals are base
(B), emitter (E), and collector (C). It is consists of three extrinsic regions: either two p-types
and one n-type or two n-type and one p-type. The different material being the sandwiched
region. It is constructed either PNP and NPN. Usually the middle region receives the least
doping level, the thinnest among the three and is connected the base terminal. The outer
layers are connected to the emitter and collector terminals and constructed much greater than
the middle layer. The emitter region has the highest doping level and usually constructed as
the largest since it serves as the source of charges. Next to it is the collector. The name of the
regions serve its purpose. The emitter will emit or provide the charges needed for conduction.
The collector will collect or gather charges from the emitter region. And the base connects
the two regions so that charges can reach the collector side from the emitter. It is called a
bipolar device due to the fact that both electrons and holes contribute to the conduction
process. Figure 2.1 shows the construction of BJT likewise, its regions and respective
terminals.

Figure 2.1
BJT Construction, Regions and Terminals

a)NPN BJT b) PNP BJT

source:electronicdevicesbyfloyd

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for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
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Note:
The doping levels affects the level of
conductivity. Meaning the lower the doping level, the
higher the resistance, thus, the lower the current a
material can support, and vice versa.

The schematic symbol for each construction is illustrated in Figure 2.2. Likewise, the
terminals are also indicated. The arrow in the symbol defines the conventional emitter current
flow. For NPN, the arrow in the symbol is pointing away (not pointing in) from the base
while for PNP it is pointing in towards the base. From the figure, the base terminal is
connected to the vertical line that serves as the PN junctions that link the base to the collector
and base to the emitter. (but never collector directly connected to the emitter).

Figure 2.2
BJT Schematic Symbol

a) NPN BJT b) PNP BJT

source:electronicdevicesbyfloyd

Theory of Operation

Figure 2.3 shows the crystal structure of a PNP transistor. It is consists of two
junctions. One (J1) is between emitter and base, and the other one (J2) is between the
collector and the base. Recall that a diode is constructed using PN junction. If we slice the
base at the center, then what we have an equivalent circuit of two PN junction diodes with
cathodes connected back-to-back. Since we know already the diode basics, then it would be
best to explain the operation of BJT using this device. Note that for PNP, the conventional
emitter current flow is pointing in towards the base. Now, let us consider connecting a battery
VEE between the B-E diode. For the emitter region to emit charges, in this case, holes, we
should connect it to the positive side of the battery. For the base region to attract these holes

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for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
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which are minority carriers of the said region, we should connect it to the negative side of
VEE (Figure 2.4).

Figure 2.3
Crystal Structure of PNP BJT Cut in Two and its Equivalent Circuit

E
Depletion Region
J1 J2

B
Emitter (E) P N N P Collector (C)

Base (B)

C
a) Crystal Structure of PNP BJT b) Equivalent Circuit Diagonally Cut at the
Center

Note:
“Like charges repel each other; unlike charges
attract.” Therefore, positive terminal of the battery
will attract electrons while repelling holes. Oppositely,
the negative terminal of the battery will attract holes
while repelling electrons.

Figure 2.4
Forward Biasing PNP BJT B-E diode

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

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As VEE is connected as shown in Figure 2.4, B-E is forward biased. Note that the
threshold voltage at the junction (J1) is typically equal to 0.7V. Just like a conducting diode,
for as long as the magnitude of VEE ≥ VTH, its resistance will drop and it would be easy for
the majority carriers from the emitter region (P-type) in this case holes (encircled plus sign)
to cross the narrowed depletion region. The moment these carriers enter the base region (N-
type), they become minority carriers. Since the base region is connected to the negative side
of VEE, minority carriers from the said region are attracted towards the negative side of the
battery. There was an injection of majority carriers (holes) from emitter to base region. Or it
can be an injection of minority carriers to the base region. Therefore, minority carriers in the
base region is now the sum of base minority carriers and the injected majority carriers from
the emitter.

This time, we are going to connect a certain battery VCC between B-C diode. For the
collector region to gather minority carriers (holes) from the base, it should be connected to
the negative side of the said battery and the positive terminal to the base, as illustrated in
Figure 2.5. Note that B-C is reverse biased. Recall that for a reverse bias diode, resistance is
infinitely high for the majority carriers to cross the very wide depletion region. Oppositely,
minority carriers can freely enter the other region. The moment carriers are injected to the
base region, most of these minority carriers will pass through the junction (J2) and will enter
the collector region. Since the collector region is made of P-type material, holes from the
base become majority carriers once again. The negative terminal of the battery will draw
these carriers towards it and become collector current. A very small amount of carriers will
enter the base terminal and become base current since the doping level of the said region is
the lowest (Figure 2.6). Note that for NPN BJT, the same theory applies except for the
polarity of the batteries and the majority carriers involved (free electrons)as shown in Figure
2.7.

Figure 2.5
Reverse Biasing PNP BJT C-B diode

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

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Figure 2.6
Flow of Majority and Minority Carriers

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

Figure 2.7
Biasing PNP and NPN BJT Indicating Carrier Flows

a) PNP BJT Biasing b) NPN BJT Biasing

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

Figure 2.8 shows the crystal structure and the schematic symbol with conventional
branch current flows for NPN and PNP respectively. Notice that for NPN BJT, both collector
and base terminal currents (IC and IB) are entering the base while emitter terminal current (IE)
is leaving the base. However, for PNP BJT, both IC and IB are leaving the base while IE is
entering the base. Applying Kirchhoff’s Current Law (KCL) using either NPN or PNP at the
base region as the junction, we have:
IE = IB + IC

Either NPN or PNP, the fact is that the emitter conventional branch current, IE, is the
sum of the base branch current IB and collector branch current IC. Transistor is a device that

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transfers current from a low resistance to a high resistance region. Recall that the B-E is
forward biased (low resistance) while B-C is reverse biased (high resistance).

Figure 2.8
BJT Crystal Structure and Schematic Symbols with Conventional Branch Current

a)NPN BJT b)PNP BJT

source:electronicdevicesbyfloyd

Characteristic Curve

Unlike the previous devices discussed, BJT has two characteristic curve: one for the
input side, and the other one is the output. In our discussion we used B-E and B-C diodes.

Notice that the base terminal has been paired twice. It is said that the base terminal is
common to both side: with the emitter to provide carriers and with the collector at the other
side to collect carriers. Also the base is the terminal directly connected to or closest to the
ground. So for the following discussion we will be using common base although BJT
configuration is not limited to it only.

Note:

➢ capital letter subscript means DC value – IB, IC,

VE, VCB
➢ double letter subscript means voltage across,
the first letter is more positive than last – VBC
(base more positive than emitter), VBE, VCE
➢ Single letter subscript,
for current, it means branch current - IB, IE
for voltage, it means node or terminal voltage
with respect to the ground – VE (voltage
between emitter and the ground)

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Figure 2.9 shows the characteristic curve of the input side since it provides the
carriers injected to the collector, B-E diode. Throughout the analysis, NPN BJT is considered
here. The input terminal is the emitter for the base is neither the input nor output terminal
though it is part of both circuits. Likewise, for the output circuit, the collector is the output
terminal. We say, for common base, emitter is the input terminal and collector is the output
terminal. The curve relates input current IE to the input voltage VBE at different values of the
output voltage VCB. Note that VCB is used here for we made the collector terminal more
positive than the base. Recall that the input side or the B-E diode is forward biased.
Nonetheless, we have a curve of a diode in conduction region. The forward bias voltage
applied at the input side, that is the voltage between the base and emitter should be atleast
equal to greater than 0.7V. The moment this condition is met, there will be sufficient
injection of emitter carriers to the base, thus, the input circuit will conduct and input current
IE will rise exponentially. Notice that though the output voltage VCB is made to be varied, the
value of IE is unaffected of it. It is solely dependent upon VBE. If the BJT in turned on, it is
assumed that the value of VBE is approximately constant that is,

VBE ≈ 0.7V

Figure 2.9
Common Base Input Characteristic Curve

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

The output characteristic curve for common base is shown in Figure 2.10. It relates
the output current IC to the output voltage VCB at different values of the input current IE.
Regardless of whatever configuration used, there are three region of operations of BJT:

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active, cut-off and saturation. Active or linear region is employed in linear amplifiers. In this
region, B-E is forward biased and B-C is reversed biased.

At IE = 0 A, IC is equal to the reverse saturation current ICBO which is negligible. As

the value of the input current IE increases, the value of the output current IC increases almost
equal to the value of IE. Because the value IB is very small due to its doping level, usually in
microamperes, the value of the emitter current IE is approximately the same as the collector
current, IC:

IE ≈ IC

Figure 2.10
Common Base Output Characteristic Curve

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

The cut-off region is found below the zero crossing, that is, the region where IC is
zero. It can be achieved by reverse biasing both B-E and B-C junctions of a BJT.

The saturation region is found to the left of the active region, that is, VCB is zero or
equal to some negative values. Notice that in this region, you will find the exponential
increase of IC as VCB increases towards zero. That is, forward biasing both B-E and B-C

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junctions. Table 2.1 shows the summary of the region of operations and their respective
biasing required.

Table 2.1
Region of Operations and Biasing Required

Region of Operation B-E Biasing B-C Biasing Application

Active/ Linear Forward Bias Reverse Bias Amplifier
Cut-Off Reverse Bias Reverse Bias Switching
Saturation Forward Bias Forward Bias Switching

Common Base

For NPN and PNP to configure such, along with the biasing required for active
region, it is shown in Figure 2.11. Recall that the input circuit of common base is B-E and the
output side is the B-C. The input terminal of such configuration is the emitter that its input
current is the emitter conventional current, IE. The output terminal is the collector, and the
output current is IC. It is called as such due to the fact that the base terminal is “common” or
part of both the input and the output circuit and it is usually the terminal closest to if not
directly connected to the ground.

Figure 2.11
Common Base Configuration with Biasing for NPN and PNP BJT

a) NPN BJT b)PNP BJT

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

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Figure 2.12
Common Base Input Characteristic Curve

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

The input characteristic curve of common base relates the input current, IE, to the
input voltage VBE, at different values of the output voltage VCB (Figure 2.12). The forward
bias voltage between the base and emitter should be greater than 0.7 V. Note that VBE = 0.7
V. Ideally for NPN, we connect the positive terminal to the base and negative terminal of the
voltage source to the emitter. Once the input circuit conducts, it behaves like that of a typical
PN junction diode, thus, IE, then rise exponentially. The input impedance of common base is
very low, as seen in the vertical curve.

The output characteristic curve is illustrated in Figure 2.13. The curve depicts the
relationship between the output current IC and output voltage VCB at different levels of the
input current, IE. As seen in the curve, the input current IE controls the value of the output
current IC. At IE = 0 A, the value of IC is equal to ICBO, (reverse leakage current between the
base and collector when the emitter is open) which is negligible. As the value of IE increases,
the value of IC is increasing equally to it. That, for common base configuration, the value of
IC is approximately equal to the value of IE. Notice that the effect VCB to the output current is
almost negligible. The horizontal curve depicts a very high output impedance. For this
reason, common base is used for low to high impedance matching. The cut- off region is
located below IE = 0 and saturation region is to the left of VCB = 0. Active region is found
above cut-off and to the right of saturation region. The value of IC is solely dependent upon
the value of the input current IE. For such configuration, there is a constant value that relates

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the two current: alpha, α. Usually, the value of α is 0.90 to 0.998 (Boylestad & Nashelsky,
2014). Alpha is known as common base amplification factor.

α = IC / I E
IC = α I E

since IC ≈ IE
then, α ≈ 1

Figure 2.13
Common Base Output Characteristic Curve

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

Common Emitter

The next configuration is typically used as linear amplifier, the common emitter. It is
where the emitter is part of both the input and output circuit. The emitter terminal is usually
nearest to or directly connected to the ground. Such configuration is shown below in Figure
2.14 for both NPN and PNP BJT. Notice that the input side is still B-E circuit. The forward
bias is provided by a battery VBB. Its positive terminal is connected to the P-type base and
negative to the N-type emitter for NPN. Double letter “BB” subscript is used to denote that

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the input terminal is the base. The input current is IB. The output side is the combination of
collector and the emitter, collector being the output terminal with output current, IC. The
required bias is provided by the battery VCC. Take note also that whatever the configuration
used, the direction of the branch currents, IB, IC, IE are all the same for PNP and NPN. Also
either construction will give the same formula of

IE = IC + I B

Figure 2.14
Common Emitter Configuration with Biasing for NPN and PNP BJT

a) NPN BJT b) PNP BJT

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

The input characteristic curve shows the effect of input voltage VBE to the input
current IB at different levels of the output voltage VCE. For as long as the forward voltage is
greater than 0.7 V, the input side will provide an input current IB usually in µA. At different
values of the output voltage VCE, the input current is unaffected of it. The only parameter that
affects it is the input voltage, VBE (Figure 2.15).

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Figure 2.15
Common Emitter Input Characteristic Curve

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

Figure 2.16
Common Emitter Output Characteristic Curve

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

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In Figure 2.16, the output characteristic illustrates the relationship between the
output current IC and output voltage VCE at different levels of the input current IB. At IB = 0
A, IC is approximately zero. Notice that as the input current IB, increases, in µA, the output
current IC also increases in mA value. Also that the curve is not that horizontal as compared
to common base indicating that IB is affected by the change in VCE. Cut-off region is found
below IB = 0A and saturation is found to the left of VCE = 0. Active region is above cut=off
and to the right of saturation region. Common emitter forward current amplification factor, β
(beta) relates to output current IC to the input current IB. Its value ranges from 20 to 600
(Villamor, 2003).

β = IC / IB
IC = β I B

Note:
Whatever configuration it is, for linear amplifier
or active region:
B-E is Forward Biased
B-C is Reverse Biased

Common Collector

For common collector the collector terminal is common to both input and output
circuits. It is the terminal closest to or directly connected to the ground. The input set is base-
collector and the output circuit is collector-emitter. The input terminal is the base and the
output terminal is the emitter. Likewise, all branch currents are indicated with the required
biasing. Figure 2.17 shows such configuration.

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Figure 2.17
Common Collector Configuration with Biasing for NPN and PNP BJT

a) PNP BJT b) NPN BJT

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

The input characteristic curve of common collector is the same as the input
characteristic curve of common emitter (Figure 2.15), except that the input voltage is VBC and
the output current is IE (which is approximately equal to IC).

The output characteristic curve of common collector is the same as the common
emitter curve (Figure 2.16) except for its output current which is IE (IC in common emitter).
Nonetheless the curve is the same since IC and IE are approximately equal in value.

This configuration is commonly used in high to low impedance matching circuit.

IB and IE are related through γ (gamma) which is the ratio of output current, IE, to the input
current, IB, known as the common collector forward current amplification factor.

Note:
• The base terminal will always be the input
terminal unless the configuration is common base
where it is replaced by the emitter terminal.
• The collector terminal will always be the output
terminal unless the configuration is common
collector where it is replaced by the emitter
terminal.

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PROGRESS CHECK (Use extra sheet/s of paper to answer)

Name: ___________________________________________ Date: ____________________

I. Identification:
Write you answer on the space provided before each number.

_______________1. BJT configuration with an output current of IE and input current IB.
_______________2. A curve that relates the input current to the input voltage at different
levels of output voltage.
_______________3. It is a connection where the emitter is closest to or directly connected to
the ground.
_______________4. The output voltage for grounded collector.
_______________5. Visual representation depicting the relationship between the output
current to the output voltage at different levels of the input current.
_______________6. The output voltage of common base BJT.
_______________7. It is the sum of base current and collector current.
_______________8. It is the ratio of collector current to the base current.
_______________9. If the collector terminal is common or grounded, the output current is
equal to ____________.
_______________10. For PNP BJT configured as common emitter, the base terminal is to be
made _____________than the emitter.

II. Drawing:
Draw the BJT configurations required with biasing and current directions using BJT
schematic symbol.

1. Common Collector 2. Common Base 3. Common Emitter

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REFERENCES
Textbook/s :

Boylestad, R and Nashelsky, L (2018). Electronic Circuit and Devices, 11th Edition.
Pearson Education Limited

Floyd, T. (2018). Electronic Devices Conventional Current Version, 10 th Edition.

Pearson Education Limited

Kaushik, D. (n.d). Analog Electronics (Circuits and Devices). Dhanpat Rai Publishing
Company (P) Ltd.

Malvino, A. (2016). Electronic Principles, 8th Edition. McGraw-Hill Education

Villamor, R (2003). Guidebook in Electronics Engineering. HR Publishing

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LEARNING GUIDE

Week No.: __3-4_

TOPIC/S:
o FET amplifiers:
▪ Biasing of JFET and MOSFET
▪ Analyze and design of common source, common drain and common gate
amplifier configuration

EXPECTED COMPETENCIES
After completing this learning guide, the students will be able to:
1. explain the theory of operation of Junction Field Effect Transistor;
2. explain the theory of operation of Junction Field Effect Transistor; and
3. analyze and design common source, common drain and common gate amplifier
configuration.

CONTENT/TECHNICAL INFORMATION

Definition of Terms

Bipolar
Refers to a device that uses both electrons and holes in conduction

Channel
Either P or N type material where charges flow from source to drain

Field Effect
The principle of FET where charges are attracted without actual contact

Unipolar
Refers to a device that uses either electrons or holes in conduction

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Discussion

Bipolar Junction Transistor which was previously discussed was a current-controlled

device. Meaning, its output current, IC, is being controlled by its input current, IB. However,
Field Effect Transistor is typically a three terminal, voltage-controlled transistor. Its output
current is being controlled by its input voltage. If BJT is constructed either PNP or NPN, FET
is either N-Channel or P-Channel. Field Effect Transistor has two types: Junction Field Effect
Transistor (JFET) and Metal-Oxide Semiconductor Field Effect Transistor (MOSFET).
MOSFET can either be Depletion or Enhancement Mode type. Typical FET family is shown
in Figure 4.1. For this week, JFET and Depletion MOSFET are discussed.

Figure 4.1
Typical Field-Effect Transistor Family

Field Effect Transistor

(FET)

Junction Field Effect Metal-Oxide Semiconductor

Transistor Field Effect Transistor
(JFET) (MOSFET)

N-Channel P-Channel
JFET JFET

Enhancement Mode Depletion Mode

MOSFET MOSFET

N-Channel P-Channel N-Channel P-Channel

Enhancement Enhancement Depletion Depletion
Mode MOSFET Mode Mode Mode
MOSFET MOSFET MOSFET

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Junction Field Effect Transistor

Construction

The first type of FET is the Junction FET (JFET). Its terminals are the source (S), gate
(G), and drain (D). The name of its terminal suggests its purpose. Likewise, the current
directions are indicated (Figure 4.2).

Figure 4.2
JFET Schematic Symbols

a) N-Channel JFET b) P-Channel JFET

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

The source terminal provides the carriers, the drain collects the carriers or charges and
the gate controls – meaning, either turns off (close channel) or on (open channel) the device.
Figure 4.3 shows the construction an N-Channel JFET. Notice that majority of its
construction is made of the channel. The N-channel connects the drain (D) and the source (S)
through the ohmic contacts at its ends. There are two p-type regions which are internally
connected to the gate. Depletion regions exist between the channel and the p-type materials
under no bias. For P-Channel JFET, its channel is P-type and the regions connected to the
gate are n-type.

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Figure 4.3
Construction of an N-Channel Junction Field Effect Transistor

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

Theory of Operation

Recall that our goal is to let JFET conduct, that is, to send carriers from the source (S)
to the drain (D). Furthermore, to control the amount of charges flowing through the gate (G).
We can connect a certain battery VDD between the drain (D) and source (S), connecting its
negative terminal to the source so that it will excite and repel free electrons and positive
terminal of the battery to the drain so that it can attract carriers or free electrons from the
source. Meanwhile, we connect the gate terminal to the source (ground) to set voltage
between the gate and source, VGS = 0V as shown in Figure 4.4. We set the value of VDD to be
varied, to see the effect of it to the JFET. The voltage reverse biases the N-channel. Notice
that the width of the depletion region is non-uniform or unequal. The width is wider in the
upper portion, near the drain than the lower portion. The reason for it is that, the upper
portion of the channel receives more reverse bias than the lower part. Resistance is directly
proportional to the width of the depletion regions. More reverse bias means wider depletion
region and so does the value of resistance and vice versa. In effect, the width of the channel
skews. As the value of VDD is increased, the value of the reverse bias voltage between the
drain and source, VDS increases as well. And electrons flow from the source to the drain
through the N-channel, producing source current, IS. Since the gate terminal is grounded, it
follows that its current IG is zero which means drain current ID is equal to IS. Further increase

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Figure 4.4
JFET at VGS = 0V and VDS > 0V

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

in VDS due to VDD results in further increase in drain current but widening of depletion
regions causing the channel to narrow. Resistance will also increase reaching infinity. Until
such time that the reverse bias voltage between the drain to source will cause the two
depletion regions to almost touch each other that the channel would almost close. This value
of reverse bias is called pinch-off voltage, VP. This condition is called pinch-off. In this
condition, the value of the output drain current is maximum equal to its saturation level, IDSS
shown in Figure 4.5. The curve shows the relationship between the output current, ID to the
output voltage VDS at VGS = 0V.

Figure 4.5
Curve for VGS = 0V, VDS = VP, ID = IDSS

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

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Note:

IDSS is achieved when VGS = 0 and VDS > |VP| for

either P-Channel or N-Channel JFET

If we set the value of VDS to a certain value lower than VP, and allow the gate terminal
to control the charge flow, we connect a certain battery VGG between the gate and source.
Connecting the negative terminal to the gate and positive to the source, will reverse bias the
two p-type regions. It should be highlighted that IG should be zero at all times. The gate
terminal should not draw current rather control the amount of charges from source to the
drain (Figure 4.6). Increasing the value of VGG results in increase in reverse bias voltage
between the gate and source, VGS. It will result to widening of the depletion regions, wider in
upper portion than lower, thus narrowing the channel. Since VDS is held to a lower value than
the pinch-off voltage VP, ID will flow but less than the saturated drain current IDSS. Making
VGS more and more negative equal to the pinch-off value, VP, will cause the channel width to
become depleted, until such time that the depletion regions to touch each other, closing the
channel, making it impossible for carriers to cross from source to the drain.

Figure 4.6
N-Channel JFET VGS = -V, VDS > 0V

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

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Note:

The JFET is always operated with the gate-

source pn junction reverse-biased or the gate
terminal grounded to ensure that IG = 0 A all the
time.

And it is said that the JFET has been turned off. It is illustrated in the characteristic curve in
Figure 4.7, that making the value of VGS more negative while the value of VDS constant, will
result to decreasing ID value. The moment VGS equals the value of pinch-off voltage VP, ID is
zero. From VGS = 0V, ID = IDSS, up to VGS = VP, ID = 0A.

Figure 4.7
Curve of VGS=VP, VDS > 0V, ID = 0A

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

For P-Channel JFET the required biasing and the directions of current is opposite of
N-Channel JFET. It uses holes instead of free electrons in conduction as shown in Figure 4.8.

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Note:

In either N-Channel or P-Channel if VGS = VP

negative VP for N-Channel and positive for
positive for P-Channel, and VDS > 0V, then, ID =
0A

Figure 4.8
P-Channel JFET with Biasing and Output Characteristic Curve

a) P-Channel JFET Biasing b) P-Channel JFET Output Characteristic Curve

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

Using Shockley’s equation, the relationship between ID and VGS is seen, showing that
FET is a voltage-controlled device:

ID = IDSS ( 1 – VGS / VP)2

where
ID is the output drain current, mA

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IDSS is the drain saturation current, mA

VGS is the input gate to source voltage, V
VP is the pinch-off voltage, negative for N-Channel,
positive for P-Channel, V

Shockley’s equation can be represent graphically using the transfer curve shown in
Figure 4.9. By varying the value of VGS from 0 to VP, values of ID is made to be varied from a
value equal to IDSS to 0.

Figure 4.9
N-Channel JFET

VP 0.5VP 0.3VP

In the curve, it can be seen that if VGS is equal to VP, ID = 0. For VGS equal to half of pinch-
off voltage, VP, drain current, ID, is quarter of the drain saturation current, IDSS. The drain
current will be equal to half of the drain saturation current if VGS is equal to one third of the
pinch-off voltage value. Atleast four points is needed to plot the transfer curve of either N-
Channel of P-Channel. In summary, atleast 4 points is considered for the transfer curve.
Table 4.1 suggests four possible ordered pairs to be used:

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Table 4.1
Summary of Suggested Ordered Pairs Using Shockley’s Equation

Voltage between gate and source Output drain current

(VGS) Value (ID) value
0 IDSS
0.3 VP IDSS/2
0.5 VP IDSS/4
VP 0

Examples:

1. Trace the trasfer curve of an N-Channel JFET with VP = -6V and IDSS = 12 mA.

Answer:

Given:
N-Channel JFET
VP = -6V
IDSS = 12 mA

Required:
Transfer curve

Solution:

For VGS = 0V
ID = IDSS ( 1 – VGS / VP)2
ID = 12mA ( 1 – 0V / -6V)2
ID = 12mA ( 1 – 0 )2
ID = 12 mA
(0, 12) (do not include the unit) 1st ordered pair

For VGS = 0.3VP = 0.3(-6V) = - 1.8V

ID = IDSS ( 1 – VGS / VP)2
ID = 12mA ( 1 – -1.8V / -6V)2
ID = 12mA ( 1 – 3/10 )2
ID = 12mA (0.5)
ID = 6 mA
(-1.8, 6) 2nd ordered pair

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For VGS = 0.5VP = 0.5(-6V) = - 3V

ID = IDSS ( 1 – VGS / VP)2
ID = 12mA ( 1 – -3V / -6V)2
ID = 12mA ( 1 – 1/2 )2
ID = 12mA (0.25)
ID = 3 mA
(-3, 3) 3rd ordered pair

For VGS = VP = -6V

ID = IDSS ( 1 – VGS / VP)2
ID = 12mA ( 1 – -6V / -6V)2
ID = 12mA ( 1 – 1)2
ID = 12mA (0)
ID = 0 A
(-6, 0) 4th ordered pair

Figure 4.10
Transfer Curve of Example No.1

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

2. Trace the transfer curve of P-Channel JFET with IDSS = 4 mA and VP = 3V.

Answer:

Given:
P-Channel JFET

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VP = 3V
IDSS = 4 mA

Required:
Transfer curve

Solution:

For VGS = 0V
ID = IDSS ( 1 – VGS / VP)2
ID = 4 mA ( 1 – 0V / 3V)2
ID = 4 mA ( 1 – 0 )2
ID = 4 mA
(0, 4) (do not include the unit) 1st ordered pair

For VGS = 0.3VP = 0.3 (3V) = 0.9V

ID = IDSS ( 1 – VGS / VP)2
ID = 4 mA ( 1 – 0.9V / 3V)2
ID = 4 mA ( 1 – 3/10 )2
ID = 4 mA (0.5)
ID = 2 mA
( 0.9, 2) 2nd ordered pair

For VGS = 0.5VP = 0.5( 3V) = 1.5 V

ID = IDSS ( 1 – VGS / VP)2
ID = 4 mA ( 1 – 1.5V / 3V)2
ID = 4 mA ( 1 – 1/2 )2
ID = 4 mA (0.25)
ID = 1 mA
(1.5, 1) 3rd ordered pair

For VGS = VP = 3 V
ID = IDSS ( 1 – VGS / VP)2
ID = 4 mA ( 1 – 3V / 3V)2
ID = 4 mA ( 1 – 1)2
ID = 4 mA (0)
ID = 0 A

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(3, 0) 4th ordered pair

Figure 4.11
Transfer Curve for Example 2

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

Note:
We use the first quadrant for P-Channel and
second quadrant for the N-Channel JFET

Depletion Mode Metal-Oxide Semiconductor Field Effect Transistor (DMOSFET)

Construction

The name depletion defines the mode or region of operation. Figure 4.12 illustrates
the construction of an N-Channel D-MOSFET. A silicon P substrate acts as the foundation of
the device. Unlike JFET, MOSFET are not limited to three terminals only. There are
MOSFETs with substrate (SS) terminal as the fourth terminal although in most cases it is
internally connected to the source (S) terminal. In the construction, the drain (D) and the
source (S) are connected to the n-type semiconductor regions linked by the N-channel
through metal contacts. Likewise, the gate terminal is also connected to a mettalic contact
though insulated to the channel inside by a very thin insulator silicon dioxide (SiO2). This
insulator is a dielectric that sets up an opposing electric field within it when applied with a
voltage. This is the reason why in most cases IG will remain zero and that its input impedance
is very high. Thus, in Metal-Oxide Semiconductor FET, metal refers to the mettalic contacts

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that link the terminals to the device. Oxide for the dielectric that isolates the gate from the
channel, and semiconductor for the material of the base or foundation where the p or n-types
are embedded.

Note:

The gate is not physically or electrically connected to

the channel, Thus, IG is always zero and its input
impedance, Zi, is very high.

Figure 4.12
Basic Construction of an N-Channel Depletion MOSFET

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

For a P-Channel D-MOSFET, Figure 4.13 shows its illustration. Its substrate is made
of n-type. The regions where the drain and source terminals are connected are p-type. The
channel is p-type also. Since FET is unipolar, for N-channel, the carriers are free electrons
while for P-type, its holes. The schematic symbols of DMOSFET for both N-Channel and P-
Channel are given in Figure 4.14 with the substrate terminal either enternally connected to
the source or exposed. In the symbol, there is a gap between the gate ternminal and the
channel to denote that the channel is not physically connected to the gate. The arrow in the
symbol denotes the direction of the conventional substrate current should there be.

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Figure 4.13
Basic Construction of an P-Channel Depletion MOSFET

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

Figure 4.14
DMOSFET Schematic Symbol

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

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Theory of Operation

N-Channel Depletion MOSFET is given in Figure 4.15. A battery VDD is connected

across the drain (D) to source (S), making the drain terminal more positive than the source.
The substrate (SS) is connected to the source (S). In the illustration, the gate and source
terminals are connected to the ground which means VGS = 0V. There will be an attractioon
for free electrons from the source to the drain throught the channel. The same condition is
established as in JFET, where at gate-to-sourcev oltage equal to zero, the drain current is
equal to the saturation current IDSS.

Figure 4.15
N-Channel DMOSFET at VGS = 0V

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

If we are to plot the transfer curve of N-Channel DMOSFET, we will have the same
curve as an N-Channel JFET except that its operation is not merely limited to VGS = 0 V up to
VGS = VP. If we set VGS equal to a negative value, positive charges are developed at the
opposite side of the gate metal contact which is the channel, depleting its width. As a result,
the amount of free electrons from source to drain is decreased. Further increase in the
negative voltage between the gate and the source equal to its pinch-off voltage will result to
further decrease in the channel’s width until it closes, thus, its depletion is the mode or
region. In effect, drain current is reduced to zero. Recall that the gate is insulated, for ths
reason, MOSFET is also called as Insulated Gate Field-Effect Transistor. Since the gate has
no electrical connection to the channel, we can have positve VGS values for N-channel and
negative for VGS for P-Channel yet maintaining IG equal to zero. As a result, an opposite
effect in the width of the channel will take effect. Its width will be wider resulting in a drain

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current which is greater than the saturation current, IDSS (more drastic). In this operation, it is
said that the DMOSFET is operating in the enhancement more or region. In comparison,
JFET operates in depletion mode only but DMOSFET operates in both depletion an
enhancement modes or regions, as dipected in Figure 4.16. Shockley’s equation can still be
used in this device. For P-Channel DMOSFET it uses opposite polarities of battery as the N-
Channel and the drain current ID is due to hole flow, thus its direction is opposite as well.

Figure 4.16
N-Channel DMOSFET Transfer Curve and Characteristic Curve

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

Examples:

3. Plot the transfer curve of an N-Channel DMOSFET with an IDSS of 10 mA and VP = -4 V.

Answer:

Given:
N-Channel DMOSFET
VP = -4V
IDSS = 10 mA

Required:
Transfer curve

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Solution:

For the Depleton Mode (2nd Quadrant)

For VGS = 0V
ID = IDSS ( 1 – VGS / VP)2
ID = 10mA ( 1 – 0V / -4V)2
ID = 10mA ( 1 – 0 )2
ID = 10 mA
(0, 10) 1st ordered pair

For VGS = 0.3VP = 0.3(-4V) = - 1.2V

ID = IDSS ( 1 – VGS / VP)2
ID = 10mA ( 1 – -1.8V / -6V)2
ID = 10mA ( 1 – 3/10 )2
ID = 10mA (0.5)
ID = 5 mA
(-1.2, 5) 2nd ordered pair

For VGS = 0.5VP = 0.5(-4V) = - 2V

ID = IDSS ( 1 – VGS / VP)2
ID = 10mA ( 1 – -2V / -4V)2
ID = 10mA ( 1 – 1/2 )2
ID = 10mA (0.25)
ID = 2.5 mA
(-3, 2.5) 3rd ordered pair

For VGS = VP = -4V

ID = IDSS ( 1 – VGS / VP)2
ID = 10mA ( 1 – -4V / -4V)2
ID = 10mA ( 1 – 1)2
ID = 10mA (0)
ID = 0 A
(-4, 0) 4th ordered pair

For the Enhancement Mode (1st Quadrant)

For VGS = 1V
ID = IDSS ( 1 – VGS / VP)2
ID = 10mA ( 1 – 1V / -4V)2
ID = 10mA ( 1 + 1/4 )2

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ID = 10mA (1.5625)
ID = 15.625 mA
(1, 15.6) 5th ordered pair

Figure 4.17
Transfer Curve of Example 3

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

4. Plot the transfer curve of a P-Channel DMOSFET with VP = 6V and IDSS = 6mA

Answer:

Given:
P-Channel DMOSFET
VP = 6V

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IDSS = 6 mA

Required:
Transfer curve

Solution:

For the Depleton Mode (1st Quadrant)

For VGS = 0V
ID = IDSS ( 1 – VGS / VP)2
ID = 6 mA ( 1 – 0V / 6V)2
ID = 6 mA ( 1 – 0 )2
ID = 6 mA
(0, 6) 1st ordered pair

For VGS = 0.3VP = 0.3(6V) = 1.8 V

ID = IDSS ( 1 – VGS / VP)2
ID = 6 mA ( 1 – 1.8V / 6V)2
ID = 6 mA ( 1 – 3/10 )2
ID = 6 mA (0.5)
ID = 3 mA
(1.8, 3) 2nd ordered pair

For VGS = 0.5VP = 0.5(6V) = 3 V

ID = IDSS ( 1 – VGS / VP)2
ID = 6 mA ( 1 – 3V / 6V)2
ID = 6 mA ( 1 – 1/2 )2
ID = 6 mA (0.25)
ID = 1.5 mA
(3, 1.5) 3rd ordered pair

For VGS = VP = 6V
ID = IDSS ( 1 – VGS / VP)2
ID = 6 mA ( 1 – 6V / 6V)2
ID = 6 mA ( 1 – 1)2
ID = 6 mA (0)
ID = 0 A
(6, 0) 4th ordered pair

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For the Enhancement Mode (2nd Quadrant)

For VGS = -1V

ID = IDSS ( 1 – VGS / VP)2
ID = 6 mA ( 1 – -1V / 6V)2
ID = 6 mA ( 1 + 1/6 )2
ID = 6 mA (49/36)
ID = 8.167 mA
(-1, 8.2) 5th ordered pair

Figure 12.18
Tranfer Curve of Example 4

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

Ehnancement Mode Metal Oxide Semiconductor Field Effect Transistor (EMOSFET)

Construction

Figure 4.19 shows the basic construction of an N-Channel EMOSFET. A silicon

substrate is used as the base or foundation of the device, for N-Channel, it’s a p-type
substrate. The substrate terminal is either the fourth terminal or internally connected to the
source. Both drain and source are connected to n-doped regions through the metal contacts.
Though the gate is connected to a metal contact, however, it is being insulated by a silicon

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dioxide insulator. Its construction is the same as DMOSFET except for the absence of the
channel that connects the two n-doped regions. It is for this reason that EMOSFET is also
known as channeless MOSFET. For P-Channel, the substrate is n-type and the doped region
are p-type semiconductor materials.

Figure 4.19
Construction of N-Channel EMOSFET

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

Figure 4.20 shows the schematic symbols of EMOSFET both for N-Channel and P-
Channel. Unlike DMOSFET, the channel that connects the drain and source terminals is
represented by a broken line to denote its absence. There is a gap between the gate and the
channel for the gate is insulated. The arrow represents the substrate conventional current.
There are two schematic symbols for each construction: one is with the fourth terminal,
substrate (SS) and the other one is with substrate terminal internally connected to the source.

Figure 4.20
Schematic Symbols of EMOSFET

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

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Theory of Operation

Because of the absence of the channel, thefore, an Enhancement MOSFET do not

have depletion mode or region because there is no channel to be depleted in the first place.
To turn on an N-Channel EMOFET it is to be connected in the circuit shown in Figure 4.21.
A battery is to be connected between the drain to source, drain terminal more positive than
the source equal to its VDS. Then, We connect also a battery between the gate and source,
making the gate terminal more positive than the source. The substrate terminla is connected
to the source. Since the gate terminal is applied with positive potential, negative free
electrons are introduced to the opposite side of the insulator will repelling the holes from the
substrate. Increasing positively the value of VGS will result to an increase in the negative
charges concentrating near the insulator, thus further repulsion of the holes to go deeper in
the p subtrate. It will result to a depletion region void of holes. Until such time time that the
value of VGS will reach the value of the threshold voltage, VT, where these negative free
electrons near the silicon dioxide insulator are enough to form an N- channel that will support
charge flow from the source to the drain. Because of it, there will be a significant value of the
drain current, ID. Since there is no channel originally, it is said that a channel has been
enhanced to support charge flow.

Figure 4.21
Turning On an N-Channel EMOSFET

source:electronicdevicesandcircuittheorybyboylestadandnashelsky

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If we increase the value of VGS greater than the threshold voltage, drain current in increased
as well. Saturation is eventually reached if we set VGS contant and increase VDS. For P -
Channel EMOSFET uses negative voltages instead. And so we cannot use the shockley’s
equation to represent the relationship between the controlling input voltage VGS to the
controlled output current ID.

Note:
For VGS ≤ VT, ID = 0A
VGS > VT, ID > 0

VT is sometimes represented by VGS(th)

The transfer curve for N-Channel and P-Channel repectively is shown in Figure 12.22.

Figure 4.22
Transfer Curve of EMOSFET

VT + VGS - VGS VT

a) N-Channel b) P-Channel

To plot the transfer curve, we use the equation:

ID = k (VGS –VT)2

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k = ID(on) / (VGS(on) –VT)2

where:

ID is the output drain current, mA

k is a constant due function of the device’s construction
VGS is the gate-to-source input voltage, V
VT is the threshold voltage, V
ID(on) and VGS(on) are the values of each at a particular point
on the characteristics of the device

Note:

Use atleast five (5) ordered pairs to plot the

transfer curve of EMOSFET, starting at VGS = VT

Examples:

5. Solve for the drain current of an N-Channel EMOSFET for VGS = 5V when ID(on) =
500mA (minimum) at VGS = 10 V and VT = 1 V.

Answer:

Given:
VGS = 5V
ID(on) = 500mA
VGS(on) = 10V
VT = 1V
N-Channel EMOSFET

Required:
Transfer Curve

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Solution:

k = ID(on) / (VGS(on) –VT)2

k = 500 mA /(10V -1V)2
k = 6.17 mA/V2

ID = k (VGS –VT)2
ID = 6.17 mA/V2 (5V –1V)2
ID = 98.7 mA

6. Plot the transfer curve of an N-Channel EMOSFET with VT = 4V and k = 0.5 mA/V2

Answer:

Given:
k = 0.5 mA/V2
VT = 4V
N-Channel EMOSFET

Required:
Transfer Curve

Solution:

For VGS = VT = 4V
ID = k (VGS –VT)2
ID = 0.5 mA/V2 (4 V – 4V)2
ID = 0A
(4, 0) 1st ordered pair

For VGS = 5V
ID = k (VGS –VT)2
ID = 0.5 mA/V2 (5 V – 4V)2
ID = 0.5 mA
(5, 0.5) 2nd ordered pair

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For VGS = 6V
ID = k (VGS –VT)2
ID = 0.5 mA/V2 (6 V – 4V)2
ID = 2 mA
(6, 2) 3rd ordered pair

For VGS = 7V
ID = k (VGS –VT)2
ID = 0.5 mA/V2 (7 V – 4V)2
ID = 4.5 mA
(7, 4.5) 4th ordered pair

For VGS = 8V
ID = k (VGS –VT)2
ID = 0.5 mA/V2 (8 V – 4V)2
ID = 8 mA
(8, 8) 5th ordered pair

Figure 4.23
Transfer Curve of Example 6

Note:

For N-Channel EMOSFET, first quadrant

P-Channel EMOSFET, second quadrant

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PROGRESS CHECK (use extra sheet/s of paper to answer)

Name: ______________________________________________ Date:__________________

I. Show your complete solution. Label your graph completely.

1. Solve for k of an N-Channel EMOSFET if ID(on) is 3mA when VGS(on) is 10 V and VT = 2V.
(5 points)
2. Plot the transfer curve of number 1 using 5 ordered pair (15 points)

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REFERENCES

Textbook:

Boylestad, R and Nashelsky, L (2014). Electronic Circuit and Devices, 11th Edition.
Pearson Education Limited

Floyd, T. (2018). Electronic Devices Conventional Current Version, 10th Edition.

Pearson Education Limited

Kaushik, D. (n.d). Analog Electronics (Circuits and Devices). Dhanpat Rai Publishing
Company (P) Ltd.

Malvino, A. (2016). Electronic Principles, 8th Edition. McGraw-Hill Education

Villamor, R (2003). Guidebook in Electronics Engineering. HR Publishing

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for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.
 49

This module is a property of Technological University of the Philippines Visayas and intended
for EDUCATIONAL PURPOSES ONLY and is NOT FOR SALE NOR FOR REPRODUCTION.