ALTERA MAX + PLUS II TUTORIAL, PART I

EEC180A DIGITAL SYSTEMS I

UNIVERSITY OF CALIFORNIA, DAVIS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

OVERVIEW

This tutorial introduces the Altera MAX+PLUSII software to new users. This first part
illustrates the complete design flow for entering, debugging and downloading a simple design
example. There is particular emphasis on using the simulator to detect logic errors in the design.

A second tutorial will cover advanced topics such as creating symbols to use in hierarchical
designs, tri-state buses, and using memory modules. These topics will be important in the final
labs.

Text which is preceded by a bullet will provide step-by-step instructions for completing the
tutorial exercise. The remaining text will provide background information or explanation of the
steps being taken. All figures will be located at the end of the text.

STARTING MAX+PLUSII

Altera's MAX+plusII software runs on Windows or UNIX machines.

UNIX -

• Type setup maxplus2 to configure your environment. (This only needs to be done once.)
• Log out and log in or open a new X-window
• Type maxplus2 & to start the program.

WINDOWS -

• Double-click on the MAX+plusII icon on the Windows desktop or use the Start menu to
locate and start the MAX+plusII software.

CREATING A SCHEMATIC

You can open a new schematic in at least three ways:

• Select Graphics Editor from the MAX+plusII menu, or

Select New from the File menu and choose Graphics Editor file (.gdf) as the file type, or
Click on the far-left icon on the toolbar and select Graphics Editor file (.gdf) as the file type.

Your new file will be call Untitled-x, where x is some positive integer. You should give your
schematic a name and save it in your own working directory which is probably not the default
directory. This will let the maxplus2 software know where your files should be stored.

• Create a directory for yourself under C:\USR by using either the md command from a DOS
window or Windows Explorer. For example, you may want to save your files in a directory
such as C:\USR\YOUR_NAME. On a UNIX machine, create a subdirectory for your design
files using the UNIX mkdir command.

• Select Save As (File menu); Use the mouse to locate your working directory in the
Directories box. Once you have located the directory, give your blank schematic a name.
The .gdf extension will be added automatically. This directory will now become your default
directory for this session of maxplus2.
PLACING COMPONENTS

To view the component libraries,

• Double-click the left-mouse button (LMB) on the workspace, or

Select Enter Symbol from the Symbol pull-down menu.

The first directory listed will be your working directory. This is where symbols which you create
will be stored. At this point, you will not have any symbols in this directory.

The second directory is named prim and contains "Primitive" devices such as the basic logic
gates. To view the components available in the prim directory,

• Double-click the LMB on the prim directory in the Symbol Libraries box.

You should see an alphabetical list of the symbols contained in the prim library. You can also
double-click on the mf (Macrofunction) and the mega_lpm (Megafunctions/Library of
Parameterized Modules) directories. The mf library contains most of the standard 74-series
components which are described in various data books.

To place a component, you can type the symbol name in the Enter Symbol dialog box or you
can locate the specific symbol in one of the libraries and double-click the LMB on it.

• Bring up the Enter Symbol dialog box as described earlier and type 74163 as the Symbol
Name. Place the 74163 component in the center of your schematic page. You may want to
use the Fit in Window (View menu) option to locate the center of your schematic. Then you
can change back to Normal Size (View menu).

• Similarly place a 7447 component to the right of the 74163 as shown in Figure 1.

CONNECTING DEVICES

There are two ways you can connect pins on two devices. If "Rubberbanding" is on, a
connection can be made by moving a device so that a pin touches another pin. Once this occurs,
the pins are connected and moving the devices apart will show a wire or bus. If
"Rubberbanding" is off, a wire must be drawn between the two pins. This is done by moving the
cursor to the end of a pin until it changes from an arrow to a +. A wire can be drawn by dragging
the mouse from one pin to another with the LMB pressed.

• Turn Rubberbanding on using the Options menu or the icon on the left side of the screen.
(By placing the cursor over each icon, you can display the function of each icon button at the
bottom of the screen.) Now simply drag the 7447 until pin A touches pin QA of the 74163,
pin B touches pin QB, etc. Then move the 7447 back to the right of the 74163 so that the
wires are visible.

• Select the wire that connects RCO and LTN by clicking on it with the LMB. Press the Delete
key to delete this wire.

• Place a VCC component near the 7447 BIN pin as shown in Figure 1. Use the cursor to
connect wires from the LTN, RBIN, and BIN pins to the VCC symbol. Note that you should
see "connection dots" at a point where two wires are connected.

• Place and connect the following components as shown in Figure 1:

output
input
nand2
vcc
gnd
Note that you can use Copy and Paste (Edit menu) to place multiple instances of a component,
such as output or input pins.

Another way to make connections is by labeling wires or buses. If several wire segments have
the same name, it is as if the segments were connected together.

• To label a wire, select the wire using the LMB so that it is highlighted and then type the label
name. Do not move the text away from the wire or it will cease to be a label for the wire. To
check that a wire has a valid label, select the wire. If the label is valid, it should have a
highlighted box around it. Label the outputs of the 74163, QA-QD, as well as the inputs to
the NAND2 gate as shown in Figure 1.

Our goal is to design a modulo 100 counter which displays the decimal count values 0-99. You
have entered a design for a mod 10 counter for the least significant decimal digit. We can use
Cut & Paste to quickly design the circuit for the most significant digit.

• Select your entire circuit by clicking and dragging the LMB. Select Copy (Edit menu) to
copy the selected region. Click the LMB on a blank area above your circuit and select Paste
(Edit menu) to paste the copied selection onto your schematic. (You can use icons or short-
cut keys if you prefer.)

• Re-label the output signals of the new 74163 and the inputs of the NAND gate as shown in
Figure 2.

• Add the labels MLD and LLD to the outputs of the NAND gates as shown in Figure 2.
These labels will help in viewing these signals during simulation.

LABELING INPUTS AND OUTPUTS

We must label input and output pins for our circuit to compile properly.

• Label the output pins as shown in Figure 2 by double-clicking the LMB on PIN_NAME and
typing the desired name. Also, label the input pins /RESET and CLK as shown in Figure 2.

SETTING THE PROJECT

Altera uses the concept of a project to organize all the files associated with a specific design.
The project name should be the same as the name of the top-level design file.

• Select Set Project to Current File (File > Project menu) or use the appropriate icon on the
tool-bar to set the project name to the name of your file.

COMPILING A DESIGN

• Select Save & Check (File > Project menu) or the toolbar icon to save your file and check
for errors. If your design had an error, highlight the error message and press the LOCATE
button to view the location of the error in your design file.

Once your design checks without errors, you are ready to compile your design for simulation.
There are two types of simulation which you can perform on your design - functional and timing.
The processing for these two types of simulation is different. For functional simulation, all of
your original circuit nodes are preserved in the Simulator Netlist File (.snf). This makes it easier
to view specific nodes in your circuit and debug your design. The timing simulation is useful for
checking critical timing, such as setup and hold times, before your design is programmed into an
Altera Programmable Logic Device (PLD).

• With the Compiler tool open, select Functional SNF Extractor (Processing menu). (The
Timing SNF Extractor option must be turned off.) Also select Preserve All Node Name
 Synonyms (Processing Menu) so that the labels you used for wires will be preserved in the
.snf file.

• Press the Start button on the Compiler dialog box to compile your design for functional
simulation.

WAVEFORM EDITOR

In order to simulate the design, you will use the waveform editor to create input stimulus.

• Select the Waveform Editor (MAX+plusII menu).

• Select Enter Nodes from SNF (Node menu). Now we can choose which circuit nodes to
observe during simulation. The INPUTS and OUTPUTS boxes should be selected by
default. Press the LIST button to view the list of input and output nodes. You will want to
view all the input and output nodes in your simulation, so press the => button to copy the list
to the Selected Nodes & Groups box.

• Next turn off the INPUTS and OUTPUTS boxes and select the REGISTERED box and press
LIST. (Whenever you change the selection buttons, you must press LIST afterward to view
the updated list of nodes.) Copy all the register output nodes, M3-M0 and L3-L0, to the
Selected Nodes & Groups box by pressing => with the desired nodes highlighted.

• Turn off the REGISTERED box and select the COMBINATORIAL box and press LIST.
Highlight the MLD and LLD nodes and press => to copy them to the Selected Nodes box.
You have now entered all the nodes to be traced so press the OK button.

You should now see the selected circuit nodes with default waveforms (0 for the inputs /RESET
and CLK; Undefined ('X') for the other nodes.)

• Select End Time (File menu) and enter in 10 us to change the default length of the
simulation.

• Select the CLK signal by clicking the LMB on CLK. Then press the right mouse button
(RMB) and choose Overwrite > Clock. You can use the defaults for all the parameters and
press OK.

• Select the /Reset node and click on the "1" icon. The /RESET signal should become 1 (high)
for the entire waveform. Using the LMB click and drag from time 0 until the first falling
edge of the CLK signal. Then click the "0" icon so that the /RESET signal is low for the first
clock cycle.

• Select the four register outputs, M3-M0, by clicking and dragging the LMB. Then select
Enter Group (Node menu) and specify a group name such as M[3..0]. Specify groups for
the L3-L0 nodes, the MG-MA nodes, and the LG-LA nodes.

• Select Save & Simulate (File > Project menu). The waveform file should be the name of the
project with the .scf file extension, which will be added automatically. Your simulation
waveform should look similar to Figure 3, although your clock period and group names may
differ.

From Figure 3, we can see that this design does not correctly implement a modulo 100 counter.
Both the most significant digit and the least significant digit are changing at every clock cycle.
Also, the counters are counting 0-A instead of 0-9. Let's go back and fix our design.

• Change the M1 label to M0 and the L1 label to L0 at the inputs to the NAND gates. Also
replace the NAND2 gate of the least significant counter to an AND2 gate and a NOT gate as
shown in Figure 4. Connect the ENT and ENP pins of the most significant counter to the
output of the AND gate instead of VCC. This wire should be labeled TP.
• Select Save & Compile(File > Project menu). You should not have any errors.

• Open your waveform file (.scf) using the toolbar icon or by selecting Open (File menu).
Then select Insert Node (Node menu) and enter TP as the Node name.

• Select Save & Simulate (File > Project menu).

Hopefully, the simulation looks better now. The counter should count correctly up to 90.
However, the most significant counter then goes to 0 so that the next number is 01 instead of 91.
The problem is caused by the MLD signal. It should go low when the value of the most
significant counter and the least significant counter are both 9.

• Replace the NAND2 gate with a NAND3 gate and connect the TP signal to the third input as
shown in Figure 5.

• Select Save, Compile & Simulate (File > Project menu). You should not have any errors.
Press the OPEN SCF button to view your simulation result. Verify that your counter works
correctly now. Your simulation should look similar to the results shown in Figure 6.

ASSIGNING A DEVICE AND PIN NUMBERS

Once your design has successfully simulated, you can create a programming file and download it
to an Altera device. We will use the EPM7128SLC84-7 which is located on the Altera
Education Board.

• Open your top-level design file (.gdf) and select Device (Assign menu). Select MAX7000S
as the Device Family and EPM7128SLC84-7 as the Device.

The Education Board has specific pins connected from the EPM7128S device and the 7-segment
displays. You will need to assign these pin numbers to the appropriate output pins in your
design. We could let the software assign pins to the CLK and /RESET pins except that the CLK
pin would be assigned to the Global Clk (pin number 83) which is driven by a 25 MHz oscillator
on the Education Board. Since we need a slower clock to be able to see the output, we will
assign the CLK signal to the second global clock line, pin 2. The /RESET signal can be assigned
pin 1, which is a dedicated pin for the global clear function.

• Select Pin/Location/Chip (Assign menu). Type CLK in the Node Name box and 2 in the
Pin box and then press the Add button. You should now see the CLK pin assignment listed
in the Existing Pin Assignments box. Next type /RESET in the Node Name box and 1 in the
Pin box and again press the Add button.

• Add pin assignments to the 7-segment display output signals based on the following table.
You should see the pin number next to the input or output pin on your final schematic as
shown in Figure 7.

Display MSB Digit LSB Digit

Segment
a 58 69
b 60 70
c 61 73
d 63 74
e 64 76
f 65 75
g 67 77
decimal pt 68 79

COMPILATION FOR TIMING SIMULATION

Now that your design has passed the functional simulation, you can generate the programming
file and perform a timing simulation, if desired.

• Save and check your design. With the Compiler window open, select Timing SNF
Extractor (Processing menu). Then press the Start button to synthesize your design for the
Altera EPM7128S device. You should not get any errors, although you will probably get a
couple of warnings about timing characteristics being preliminary and about assigning pin
numbers. These warnings can be ignored.

You can run a timing simulation if you wish to see actual device delays. However, you will
notice that some of your internal node names have been optimized out of the .snf file and cannot
be simulated. This is why it is easier to use functional simulation for debugging your design.

ARCHIVING YOUR PROJECT

Once your design is complete and has been successfully verified through simulation, you should
archive your project.

• Select Archive (File > Project menu) to copy all the files associated with your project to a
separate directory. You can then maintain a copy of your final design files.

PROGRAMMING THE EDUCATION BOARD

The TA will help you set up the Education Board for programming with your circuit. The power
supply for the Education Board should be set between 8 and 10 V to provide the correct voltage
to the input of the 5V voltage regulator. You can connect the /RESET (pin 1) and CLK (pin 2)
inputs to switches on the Education Board or perhaps use a function generator to provide a 0-5V
square wave for the CLK signal.

If you did your design on a UNIX machine or some machine other than a lab PC, you should
transfer the .pof file to the lab PC. For example, you could transfer the file from a UNIX
machine using binary mode FTP. Then you will select Programmer (MAX+PLUSII menu) and
choose Select Programming File... (File menu) and specify the name of your .pof file.
 NAND2
L1 74163
L3 LDN
A 7447
L0 OUTPUT
B QA A OA PIN_NAME
L1 OUTPUT
C QB B OB PIN_NAME
VCC L2 OUTPUT
GND D QC C OC PIN_NAME
L3 OUTPUT
ENT QD D OD PIN_NAME
OUTPUT
ENP RCO VCC LTN OE PIN_NAME
INPUT OUTPUT
PIN_NAME CLRN RBIN OF PIN_NAME
OUTPUT
INPUT BIN OG PIN_NAME
PIN_NAME CLK
RBON
COUNTER
BCD TO 7SEG

FIGURE 1
 NAND2
M1 74163
MLD
M3 LDN
A 7447
M0 OUTPUT
B QA A OA MA
M1 OUTPUT
C QB B OB MB
VCC M2 OUTPUT
GND D QC C OC MC
M3 OUTPUT
ENT QD D OD MD
OUTPUT
ENP RCO VCC LTN OE ME
/RESET OUTPUT
CLRN RBIN OF MF
OUTPUT
CLK BIN OG MG
CLK
RBON
COUNTER
BCD TO 7SEG

NAND2
L1 74163
LLD
L3 LDN
A 7447
L0 OUTPUT
B QA A OA LA
L1 OUTPUT
C QB B OB LB
VCC L2 OUTPUT
GND D QC C OC LC
L3 OUTPUT
ENT QD D OD LD
OUTPUT
ENP RCO VCC LTN OE LE
INPUT OUTPUT
/RESET CLRN RBIN OF LF
OUTPUT
INPUT BIN OG LG
CLK CLK
RBON
COUNTER
BCD TO 7SEG

FIGURE 2
 Name: V 40.0ns 80.0ns 120.0ns 160.0ns 200.0ns 240.0ns 280.0ns 320.0ns 360.0ns 400.0ns 440.0ns 480.0ns 520.0ns 560.0ns
[I] /RESET
[I] CLK
[O] M7SEG 40 79 24 30 19 12 03 78 00 18 27 40 79 24
[O] L7SEG 40 79 24 30 19 12 03 78 00 18 27 40 79 24
[B] M[3..0] 0 1 2 3 4 5 6 7 8 9 A 0 1 2
[B] MLD
[B] L[3..0] 0 1 2 3 4 5 6 7 8 9 A 0 1 2
[B] LLD

FIGURE 3
 NAND2
M0 74163
MLD
M3 LDN
A 7447
M0 OUTPUT
B QA A OA MA
M1 OUTPUT
C QB B OB MB
M2 OUTPUT
GND D QC C OC MC
M3 OUTPUT
ENT QD D OD MD
TP OUTPUT
ENP RCO VCC LTN OE ME
/RESET OUTPUT
CLRN RBIN OF MF
OUTPUT
CLK BIN OG MG
CLK
RBON
COUNTER
BCD TO 7SEG

AND2
L0 NOT 74163
LLD
L3 LDN
A 7447
L0 OUTPUT
B QA A OA LA
L1 OUTPUT
C QB B OB LB
VCC L2 OUTPUT
GND D QC C OC LC
L3 OUTPUT
ENT QD D OD LD
OUTPUT
ENP RCO VCC LTN OE LE
INPUT OUTPUT
/RESET CLRN RBIN OF LF
OUTPUT
INPUT BIN OG LG
CLK CLK
RBON
COUNTER
BCD TO 7SEG

FIGURE 4
 M0
NAND3
74163
M3 MLD
LDN
A 7447
M0 OUTPUT
B QA A OA MA
M1 OUTPUT
C QB B OB MB
M2 OUTPUT
GND D QC C OC MC
M3 OUTPUT
ENT QD D OD MD
TP OUTPUT
ENP RCO VCC LTN OE ME
/RESET OUTPUT
CLRN RBIN OF MF
OUTPUT
CLK BIN OG MG
CLK
RBON
COUNTER
BCD TO 7SEG

AND2
L0 NOT 74163
LLD
L3 LDN
A 7447
L0 OUTPUT
B QA A OA LA
L1 OUTPUT
C QB B OB LB
VCC L2 OUTPUT
GND D QC C OC LC
L3 OUTPUT
ENT QD D OD LD
OUTPUT
ENP RCO VCC LTN OE LE
INPUT OUTPUT
/RESET CLRN RBIN OF LF
OUTPUT
INPUT BIN OG LG
CLK CLK
RBON
COUNTER
BCD TO 7SEG

FIGURE 5
 Name: V 3.84us 3.88us 3.92us 3.96us 4.0us 4.04us 4.08us 4.12us 4.16us 4.2us 4.24us 4.28us 4.32
[I] /RESET
[I] CLK
[O] M7SEG 18 40
[O] L7SEG 12 03 78 00 18 40 79 24 30 19 12 03 78
[B] M[3..0] 9 0
[B] MLD
[B] L[3..0] 5 6 7 8 9 0 1 2 3 4 5 6 7
[B] LLD
[B] TP

FIGURE 6
 M0
NAND3
74163
M3 MLD
LDN
A 7447
M0 OUTPUT
B QA A OA MA FIG7@58
M1 OUTPUT
C QB B OB MB FIG7@60
M2 OUTPUT
GND D QC C OC MC FIG7@61
M3 OUTPUT
ENT QD D OD MD FIG7@63
TP OUTPUT
ENP RCO VCC LTN OE ME FIG7@64
/RESET OUTPUT
CLRN RBIN OF MF FIG7@65
OUTPUT
CLK BIN OG MG FIG7@67
CLK
RBON
COUNTER
BCD TO 7SEG

AND2
L0 NOT 74163
LLD
L3 LDN
A 7447
L0 OUTPUT
B QA A OA LA FIG7@69
L1 OUTPUT
C QB B OB LB FIG7@70
VCC L2 OUTPUT
GND D QC C OC LC FIG7@73
L3 OUTPUT
ENT QD D OD LD FIG7@74
OUTPUT
ENP RCO VCC LTN OE LE FIG7@76
FIG7@1 INPUT OUTPUT FIG7@75
/RESET CLRN RBIN OF LF
OUTPUT
BIN OG LG FIG7@77
FIG7@2 INPUT
CLK CLK
RBON
COUNTER
BCD TO 7SEG

FIGURE 7