® eAWA +Quie t_ oe + Final Qustion> Hardware Model of the 8086 inte Microprocessor CamScanner = bi92 4>s.uaall Si oa8088/8086 iw SM Aad ASL olan Micro-architecture of the 8088/8086 Microprocessor 3088/8086 PON Jp Internal architecture of the @8088/8086 microprocessorsgconta Ss wo 5 2 = s 8 1B € S Ss processing units: the Bus Interface Unit (BIU) and the Execution Unit (EU). | t employs parallel processing that means it is implemented with several ing units ata time. vemety @ @ ~~ Sketehiay pe ere System ous tecture of the 8088/8086 icroproce: . eeer ive : + Each unit has dedicated functions and both operate at the same time. aac : al ae || processing effectively makes the fetch and execution of instructions * In essence, this par: jd independent operations. oe Ee ~~ + This results in efficient use of the system bus and higher performance for 8088/8086 microcomputer systems. EE 390Bus Wwierface Unit BIU The bus interface unit is the 8088/8086’s connection to the outside _ world. By interface, it connects to external devices. a : : . PY CU nas giv The BIU is responsible for performing all external bus operations, such Spy) at as instruction fetching, reading and writing of data operands for memory, and inputting or outputting data for input/output peripherals. These information transfer takes place over the system bus. EE 390ete) SL a & DD) tt Clr DE BIU MDedieDird ~is ° This bus includes an 8-bit bidirectional data bus for the 8088{ 16 bits for the 8086), a 20-bit address bus, and the signals needed to control transfers over the DUS. ultdeodl’ BD aey @o * The BIU is not only responsible for performing bus operations, it also ° : Ze ate Ut Mb ded performs other functions related to ins On and data acquisition. “153, euing and address “+t ““generation ee . | . sev c * To implement these functions, the BIU contains the segment €5,05 5%) ES registers, the instruction pointer, the address generation adder, bus control logic, and an instruction queue. CamScanner 2 li92 4>g.uaallAddress bus (20 bits) Ax Accumulator register Bx: Base register cx tGurter agrter yemster Dx + Data rggtter Execution Uni ie SO cs: Code segmant sp: stack il secoent otek a ores aes | st | set oa 551 stack sagmact Bees noaae Cpr Gary Dems pr ies ae a Zt: Lastradion gatster Bs control -—— Instruction Queue | External bus T+ Bus Interface Unit (BIU) Microprocessors Figure: Internal architecture of the 8088/8086 microprocessors E390 CamScanner 3 li92 4>s.uaallBIU: Instruction Queue AS what isthe Cancion a& instiudien Queue By Vet * The BIU uses a mechanism known as an(nstruction queue}to implement a pipelined architecture. This queué&permits the 8088 to prefetch up to 4 bytes (6 bytes for the 8086) of instruction code. * Whenever the queue is not full - that is, it has room for at least 2 more bytes, BIU is free to look ahead in the program by prefetching the next sequential instructions. 2<— 2YweED re “Ye! ° Prefetched instructions are held in the first-in first-out (FIFO) queue. Whenever a byte is loaded at the input end of the queue, it is automatically shifted up through the FIFO to the empty location nearest the output. geiney! CamScanner 2 li92 4>s.uaallhak 15 the Sax ono EU? pe jn eels ete ESS) ev 2» The execution unit is responsible for decoding and executing instructions. * = elas It consists of the arithmetic logic unit (ALU), status and control flags, general- purpose registers, and temporary-operand registers. Sober pe rode 5 - The EU actesse: rom the output end of the instruction queue)and @ata}from the general-purpose registers or memory. It reads one instruction byte after the other from the output of the queue, decodes them. It generates data addresses if necessary, passes them to the BIU and requests it to perform the read or write operations to memory or 1/0, and performs the operation specified by the instruction. Ee 390 CamScanner 3 bi9 4 guaallwoRsaaEe eu (0000044 ae: Enterral marry sodressepace Coxe ugenant (ete byte) +—— ae o on Osta weart (ee bye + b Stace mpient (eek ee ° oF st FFF on Extra segrant (ean ered) FFF Fy Figure: Memory Segmentation and the 8088/8086 microprocessor £€ 390 CamScanner 3 li92 4>g.uaallInternal Registers bps eho? OF 16-bit internal registers + The instruction pointer (IP), Four data registers (AX, BX, CX, and DX), Two pointer registers (BP and SP), Two index registers (SI and DI), Four segment registers (CS, DS, SS, and ES). Flag register (FR) /Status_register (SR), with nine of its bits implemented as status and control flags. EFFEF (22) The memory address space is 1,048,576 bytes (Mbyte) in length, The I/O address space is 65,536 bytes (64Kbytes) in length. 4 FFF (2°) CamScanner 2 li92 4>g.uaall‘Accumutatocax [an [AL Ev Base register BX Counter CX Data DX Stack pointor Base pointer SIV ——s instruction pointer EV Source index Destination index, Code segment \ Data segment RLU e Stack segment Extra segment > EU ey Fig.11.6: Schematic diagram of intel 8086 registers BH BL cH cl DH DL SP BP 1p st DI cs. os Ss ES FLAGS, E390 General purpose registers Pointers Index registers Segment registers Status register 10 CamScanner 2 li92 4>g.uaallMemory Address Space and Data Organization Let us look at how information such as numbers. characters, and instructions is stored in memory. The figure shows how a word of data is stored in memory. Notice that the storage location at the lower address, 0072416, contains the value 000000103 = 0236, The contents of the next-higher-addressed storage location, 0072516 are 010101019 = 556 : wigan in These two bytes represent the word Address = Memory Memory Address = Memory 0101010100000010> = 5502;6 teeny) hence (ener _ cons, foro ]= [ee] | omc, | ar | ore gipemerean fA emefew om] Toa | | conn omni 9 i 60724 wha é Beit Fic oe < oeee ecio,= 024 (a) fb) 60125 oye ued fi wot, £-2loyten represen even address Cokes eiol elel ecco elo, = 5502 \¢ (aligned word) ato CamScanner 3 li92 4>g.uaallNy B's! Prfelpal oaks even address boundary um A oi OD oe FEA o vba) @ . aligned word oso! C5 yety 0g aH! si, we MO >wec po cil eds odd address boundary pv oY } A ne F F eu lyin) We 5 misaligned word ees Bude eb ch 02 & 51 pI retes To permit efficient use of memory. words of data can be stored at what are called even- or odd-addressed word boundaries. If this bit is 0. the word is at an even-address boundary-that is, a word at an even-address boundary corresponds to two consecutive bytes, with the least significant byte located at an even address. For example. the word in above figure has its least significant byte at address 0072416, Therefore. it is stored at an even-address boundary. A word of data stored at an even-address boundary. such as 00000;, , 000021, 00004,, and so on, is said to be an aligned word-that is, all aligned words are located at an address that is a multiple of 2. On the other hand, a word of data stored at an odd address boundary, such as 00001,, , 00003,,, 00005,¢ and~so-on, is called misaligned word. CamScanner 3 bi92 4>g.uaallCECA, Br bs? 2 Adaress c0008H Examples of aligned and misaligned data words. medi) Zelda words eu goth! os ae abigned words Physical Aogned memory | words Byte 8 Byte 7 a eee | f abu . Bye 5 es ee Byte 4 4 Byes | word a”. j wal Byte 1 1 ne Word _ J} Byte 0 ded J Misatigned words: £390 CED, 9, 458 ABIL MI CUD get erin | misaligned words CamScanner + Wis &suaallExample 2. 1 © What is the data word shown in Fig. 2- 4(b)?~ = ©@ Express the result in hexadecimal form, —~ @ sit stored at an even @) Is it an aligned or mis: Address 00725 ,, 00724, ela LOY EB eepadt ootac data word \ Vo wipes) LL Fal edb oot FE / A \ Jere wre 2 © => FDS AA Hh —@® - or odd-addressed word boundary? --Addess aligned word of data? Zeeee coco oO! 00F2ZB H ‘Memory Memory Address Memory (binary) (hexadicimal) (binary) 101 0101 55 (0000 0010 0.2 °. 1010 1010 (b) t | eelo tol h2 sB ward stered ia ad address boundary © misallgned word -»@) CamScanner 2 lise 4>g.uaallSOLUTION The most significant byte of the word is stored al address 0072C,,and equals 11111101, = FD 4, = FDH cant byte is stored at address 0072By¢ and is AA ig = AAH Bf oi Wen ether the two bytes give the word 11101 101010102 = FDAA 1, = FDAAH ———— S @ Expressing the address of the least significant byte in binary form give 0072BH = 0072B ,, = 00000000011100101011, — rightmost bit (LSB) is lo; 1. the word is stored at an odd- address boundary in memory; therefore. it is a misaligned word of data. CamScanner + li dualAddress Memory Memory Addre Memory (binary) (hexadecimal) thexadecim | 38 00008 AO Ce] 00%, [a] a © 5] come, [FF | ome oto 10 | eon, [coco wa | 00004, | 0110 101 ta to) (a) Storing a 32-bit pointer in memory. (b) An example. Double word eit Jot. cleo lee cose coos ile slot @ Pele ws SB Ac 0 0 65,, = 2BuC o0f5 4 © Doble wrd Aooo SSFF H 380 i“ 5 2 € s 8 1B € S Ssain 20 2=FFFFF = lougs76 Even though the 8088/8086 has a 1 Mbyte address space, not, all this memory jis active at one time. Actually, the [Mbytes of memory ar . CE APYAENS toy | . A segment represents_an_ independently addressable unit of memory consisting of 64K consecutive byte-wide storage locations. Each segment is assigned a base address that identifies its starting point-that is. its lowest address byte-storage loca Only four_of these 64Kbyte segments are_active a e: the code segment (CS), stack segment (SS). data segment (DS), and extra segment (ES). cs DS $s esi partitioned into 64Kbytes segment. PERE = BRIE 65 536 5 2 = s 8 DB € S 6Segments of Memory FEEFFH Code segment cs Stack segment ‘E000 ce os = Data C2£0n os | fare Es " ss “0h soasretes = sogmnt és “acon | L_____} 000% £390 CamScanner 2 li92 4>s.uaallFour segments (each 64 Kbytes) give a maximum of raeten 256Kbytes of active memory, Of this, 64Kbytes are for program storage (code), 64Kbytes are for a stack, and 128Kbytes are for data storage. The data segment (DS) register contains the value B. outa os Therefore, the second 64Kbyte segment of memory from the top, labeled B, acts as the current data- coun of? } —3 storage segment. CS selects segment E as the code segment. It is | this segment of memory from which wm «Th instructions of the program arc currently being fetched for execution. The stack segment (SS) register contains H, thereby selecting the 64Kbyte segment labelled as H for use as a stack, Finally, the extra segment (ES) register is loaded with value J such that segment of memory functions as a second 64Kbyte data storage segment. EE 390 CamScanner 3 li92 4>g.uaallSegment Registers Within the 1MB of memory 5; :, the 8086 defines four 64 K memory blocks: * lary space, = + cs $s Ds es CamScanner 3 li92 4>s.uaall Each of these blocks of memory is used differently by the processor. CS 4. The code segment holds the program instruction codes. va DS + Thedata segment holds the data of the program. Zeiebyas busy ES 4 Theextra sey: isan extra data segment (often used for shared data), “JAI SU! at SS od The stack segment is used fo store Interrupt and subroutine retum addresses. ATM opd ots pbuh Bie ‘There are faursegment registers CS, DS, ES and $$ and each of them defines the starting address, of the corresponding segment . M2 EFEF ZU FFEFE Each segment rogistor is 16 bits wide while the address bus js 20 bits wide. The BIU takes care of this by appending four Os to the low order bits of the segment register. oy sy tenis Segment register 0000 Se ee = a E390SS Of 2 byte is called its Physical Address. Logical Address. Base Address : Offset displacement of the memory location from the starting 2 segment. SEGMENT ase OGiC a: FE Voice, 2 seemed % ° 5 : ° [i 23 6 a] vmrsicasnoness —— TOMEWORY raphe ait ga m0 = CamScanner li92 4>g.uaallShifting left four positions and filling with zeros results in in the segment address 402% zy (Coneermaae forsee 00010010001101000000 , = 12340 1. Caer awe eae eee * The offset in binary form is oe 5 2 = s 8 a € S 6 are fimmarraronre Tree ayseuy * 0022 1 = 0000000000100010 a ° Adding the segment address and the offset gives aah, oer 12340 00010010001101000000, + adder > 0000000000100010, ‘#34, 6 = 00010010001101100010 » = 12362,6 = 12362H * This address calculation is done automaticall the 8088/8086 microprocessor each time a memory access is initiated.Pointer And Index Registers * The software model has four other general- purpose registers: two pointer registers and two index registers. They store what are called offset addresses. 2 pointers —> SS ‘SP and BP deal with the address of SS. sr. oP. Pr Siac pointer inter marae >? Sourcetabeg 2 index pamoinieht 7” Mov ax, [bp] instruction loads ax from the memory location specified by the contents of the BP register. This is an indirect addressing mode. Rather than using the value in BP, this instruction accesses to the memory location whose address appears in BP. Mov ax, [bp] indireck addressing tv ar gt BP reyster up CamScanner + li92 é>s.uaall2 indOR Date sxgmat lea sagnut *\Sland pi deal with address o: register during address calculation. Source indeX pila agnodk Ae * Slis used to point to memory locations in DS. By incrementing the ‘contents of SI one can easily access consecutive memory locations. pekailion \ndeX . . * Dl accesses the memory locations in ES. ox ——> 0S DI __.es CamScanner 3 li92 4>s.uaall* The index registers (SI, DI) are used to hold offset addresses for that access data stored in the data segment of memory and are automatically combined with the value in the DS or ES register during address calculation. structions In instructions that involve the indexed addressing, the source index (SI) register holds an offset address that identifies the location of a source operand in DS, and the destination index (Dl) register holds an offset for a destination operand in ES. Sl is used to point to memory locations in DS. By incrementing the contents of SI one can easily access consecutive memory locations. * There is a class of i ns called st the memory locations in ES. g Operations, that use DI to access 23 CamScanner li92 4>g.uaallCamScanner = li92 é>s.uaall Code Segment & Instruction Pointer (IP) s 16 bits in length and identifies the location of the next word of nstruction le to be fetched i cc ent_of memory. It KK > nol is the offset of the next word of instruction code instead of its actual address. IP and CS are both 16 bits in Jength, but a 20-bit addre: access memory. The value of the address is denoted as CS:IP. * If the data at any location has a cs: EP ve logical address specified as: H:42zi4 348AH : 4214H, then the number ence r 4214H is the IP value and 348A H is the value of CS. (fective address to * Therefore, Physical Address, =P == 348A0H+4214H = 38AB4HData Segment & Destination Index (DI) o£ Cbramples) The value of Data Segment Register (DS) is 2222H. To convert this 16-bit address into 20-bit, the BIU appends OH to the LSBs pian address. Then the starting address of the Data egment becomes * If the data at any location has a as logical address specified as: Son 2222H : OO16H, then the number : eS 0016H is the offset and 2222 H is the value of DS. physical cede wi, Therefore, Effective Address, EA = 22220 H +0016 H = 22236H S CamScanner 3 bi92 4>g.uaall é ¥ et? ayn os. rP > Kediv FE 390 25 g22rn? cold > Gragsicaleddees = 2111 0 _oo\ 6 227736 WStack Segment/Stack * The stack in the memory is used_for temporary storage of information such as data or addresses. For instance, When a call instruction is executed, the 8086 automatically pushes the current values in CS and IP onto the stack. a = stick sage Ee ~ . . tack + As part of the subroutine, the contents of other registers may oo also be saved on the stack by executing push instructions (e.g., pus St when the instruction PUSH SI is executed, it_causes_the contents of SI to be pushed onto the stack). 1. o : ., : . stack * Near the end of the subroutine, pop instruction are included to pop ss" pop values from the stack back into their corresponding internal registers (¢.g., POP SI causes the value at the top of the stack to be popped back into SI). sP >> the SP register is the stack pointer, used for stack operation like push and pop. ed a Freez sthe stack is known as a LIFO structure (last-in, first-out), meaning that the last uxre -©7 ~~ thing pushed on is the fist thing popped off. It's used, among other things, to implement the ability to call functions. CamScanner 3 li92 4>g.uaall+ SP contains an offset value that points to a storage location in the current stack segment. * The address obtained from the | contents of SS and SP (SS:SP) is the hysical addres ic last storage o€ation in the stack to which data were pushed. This memory address is known as the top of the’stack. At the micro computer's start-up, the value in SP is initialized to FFFE 2088/8086 sp H. Combining this value with the current value in ives the highest-addressed word loca ‘SS:FFFEH) that is, the bottom of the stack. nin ssisP SS: FFFE | semory } (word-wide) oettens of ee eta CamScanner 3 li92 4>g.uaall= ye Data transferred to and from the stack are word-wide, not byte-wide. Each time a word is to begushed onto the top of the stack,cthe value in SP is first automaticall c decremented | by two) and then the contents of the register are written into the stack part of memory. * the stack grows down in memory from the bottom of the stack, which corresponds to the physical address $S:FFFEH, toward the end of the stack which corresponds to the physical address obtained from SS and offset OOOOH (SS:0000H). * When a value is popped from the top of the stack, the reverse of tl The physical address defi * pushed unto the stack. Its contents are first po specific register within the 8088;then SP is automatica sequence occurs. SP points to the location of the last value incremented by twopThe ed off the stack and put into the ze to top of the stack then corresponds to the address of the previous value pushed onto =“ ~ the stack. 28 CamScanner 3 bi9 &>guaallData transferred to and from the stack are word-wide, not byte-wide. Each time a word is to he pushed onto the top of the stack, the value in SP is first automatically decremented by two, and then the contents of the register are written into the stack part of memory. the stack grows down in memory from the bottom of the stack, which corresponds to the physical address SS:FFFEH, toward the end of the stack which corresponds to the physical address obtained from SS and offset OOOOH (SS:0000H). When a value is popped from the top of the stack, the reverse of this sequence occurs. The physical address defined by SS and SP points to the location of the last value pushed ‘into the stack, Its contents are first popped off the stack and PUI into the specific register within the 8088; then SP is automatically incremented by two. The top of the stack then corresponds to the address of the previous value pushed onto the stack. CamScanner + li92 4>s.uaallcs: re “oir ( LPP. ss: 5P <—— 4a nakis the stack? write Suncions «2 stack? me_stack go What is a stack, and why is it needed? “x gc The stack is a section of rite memory (RAM)/used by the CPU to store information > temporarily. CPU needs this storage area since there are only limited mumber of registers How stacks are accessede=ol > SS (stack segment) and SP (stack pointer) must be loaded teacce33)stack in the memory. > Every register in the CPU (except segment registers and SP) can be stored in the stack and loaded from the stack. ASR XSE Pushing onto the stack =~, > Storing the CPU register in the stack is called a push. == Logical vs. iysical address of the stack Calculating the physical address for the stack, the same principle is applied as was used for the code and data segments. Physical address depends on the value of stack segment (SS) register and the stack pointer (SP). @) Calculate the physical address b) Calculate the lower range of the Sled, 35000+FFFE = 44FFE ¢— effedive address MenuaueS Seluting 4, 35000+0000 3k — ©) Calculate the upper range of the stack segment: 2° — 35000+FFFF Quit d) Show the logical address of the stack: 22am SeaOTEEE 4 a a CamScanner + li92 é>g.uaallSP=1236, AX=24B6, DI=85C2. @Q & PUSH AX PUSH DI PUSH DX. = | —- storing CPU register —>| Bs in tae Hae 24 ® START Aer PUSH AX USA Pel ladle Ol wes e =— Fe 390 w the contents of the stack as each — | 93 SF c c2 85 85 Bo_| BE 24 24 ne PUSH DI SPAQH > SPHIZ4 ip SPE? © Note that in 80x86 the lower byte of the register is stored to the lower address. Cate I ss. SP decrement lay 2 CamScanner 3 li92 4>g.uaallSS:1SFB feaiiss codentieg SS:SFC fstack in CPU SS:1SFD SS:ISFE \N SS:ISEF OEE 2 ss:1900 Er OPD0tn W980 Zi 7 Por CUI Sle Heer & SS:1SFA—> | START SP=18FA on F6 __| —> Da AG ate, > SPH8FE —_y sp=1900 we OX-2088 Se BX=FOOT jack and. \ S5:5¢ OMe remant by 2 Por fs Ie Ae se One <= 04 BA * *Ox* K CamScanner 3 li92 4>s.uaallSJaysisay ejeq CamScanner + lid a suella) Write the Ri 5 fall the dats registers i= & Jj akg Mapr “eUrtte ihe main usages o te data registers AX, Bx CX, DA piheysaecn Data Registers memory wt Registers oc Ee ©. ¢ data in internal registers instead of memory during processing is Cri Gree sds wre Registers * Normally, the data registers can be used as the source or destination of an operand during an arithmetic operation such as ADD, or a logic operation such as AND. Phe advantage of storin that theyéan be accessed much faster. 5 2 = s 8 DB € S 6 * However, forsome operations, an operand that is to be processed may be located in memory instead of the internal register. poco ens assert + In this case, an{index address is used)to identify the location of the operand in memory. °AX is the "accumulator"; some of the operations, such as MOL and DIV, require that one of the operands be in the accumulator. Some other operations, such as ADD and SUB, may be applied to any of the registers (that is, any of the eight general- and special-purpose registers) but are more efficient when working with the accumulator. All input/output operations must use accumulator register AL or AX for data. =Accumulator Base Word multiply, word divide, word 1/0 Byte multiply, byte divide, byte TJO, translate, decimal arithmetic Byte snultiply, byte divide Transtate String operations, loops Variable shift and rotate Word multiply, word divide, indirect /O = (b) (a) General-purpose data registers. (b) Dedicated register functions. Cd AY Sy mead) Obi ey £390 34 CamScanner 3 bi9 4 guaall“ voy [ex] , AX “ Memory localiin *BX is the "base" register; it is the only general-purpose register which may be used for direct addressing. For example, the instruction{MOV [BX], AX}causes the contents of AX to be stored in the memory location whose address is given in BX. a °CX is the "count" register. The looping instructions (LOOP, LOOPE, and LOOPNE), the shift and rotate“instructions (RCL, RCR, ROL, ROR, SHL, SHR, and SAR), and the string - instructions (with the prefixes REP, REPE, and REPNE) all use the count register to determine how many times they will repeat. °DX is the "data" register; it is used together with AX for the word- size MUL and DIV operations, and it can also nol mathe! port number for as are all of the other general-purpose registers. ££ 390 35 CamScanner + li92 é>s.uaallx Write the reset/seb conditions fr all statis flag AU Sr BAL Syke Status Register/Flag Register The logic state of these status flags indicate conditions that are produced as the result of executing an instruction-that is, after executing an instruction, such as ADD, specific flag bits are reset (logic 0) or set (logic 1) based on the result that is produced. a The 16 bits of the flag rezisters: See ee eee ore e[r[r[R [lo wpep>rlul*]>ul*]ule R= teserved SF= U= undefined 7F= OF= overflow flag AF= iary carry flag DF= direction flag PF= panty flag IF interupt flag CF carry flag TT= wap flag Let us first summarize the operation of these flags: L6G CF Rui . . 1. (The Carry Flag (CP) CF is set if there is a carry-out or a borrow-in for the most significant bit of the result during the execution of an instruction. Otherwise, CF is reset. Ms) dypzons\ ai Pn cl v4 \ B asfrmsidt orn @ SF Vvot ollo . - Co ecw Or10 olor EE 390 @Deeow tow M58 cred CamScanner li92 4>g.uaallrs E22 eo ole Bs ot Pree esate EDLY le Pri ot wt ® fe= e Parity Flag (PF): PF is set if the result produced by the instruction has even parity-that is, if it contains an even number of bits at the 1 logic level. If parity is ae fen Make DEY er Vi RE we Aer! The Auxiliary carry Flag (AF); AF is set if there is a carry-out from the low nibble into the high nibble or a borrow-in from the high nibble into the low nibble of the lower byte in a 16-bit word. Otherwise, AF is reset. GFeo ahsciye Ae ESR @zZe:! The Zero Flag (ZF) ZF is set if the result produced by an instruction is Otherwise, ZF is reset. Sfro Nidds Shute Wan ECB @sF=! The Sign Flag (SF); The MSB of the result is copied into SF. Thus, SF is set if the result is a negative number or reset if it is positive. ¢ Overflow Flag (OF)3) When OF is set, it indicates that the signed result is out of range. If the result is not out of range, OF remains reset. EF 390 7 CamScanner 2 li92 4>g.uaalleS B_ Grkl Plags The other three implemented flag bits-the direction flag (DF), the interrupt enable flag (IF). and the trap flag (TF) are €ontrol flags. ee ae bed deel TFs! *\IF, Interrupt Enable Flag} This bit is set to enable or cleared to disable the external interrupt requests. For the 8088/8086 to recognize interrupt requests at its interrupt (INT) input, the IF flag must be set. When IF is reset, requests at INT are ignored and the interrupt interface is disabled. ys SP | eum ys pled as ALLoD rbt¢ DFet } * (DF, the Direction Flag: This bit is used to tOhtrol the direction of the string operations. When set, the string instruction automatically decrements the address; therefore, the string data transfers proceed from high address to low address. On the other hand, resetting DF causes data bel gilli transfers proceed from low address to high address. TRI to execute one instruc routine. Used for debu 5 2 = s 8 a € S 6an Be ake SAR Sip — String - A series of data byte or word available in memory at consecutive locations, to be referred as Byte String or jord String. & String of characters may be located in consecutive memory locations, where each character may be reoresented by its ASCII equivelent. ally stored as count in the CX register. The incrementing or decrementing of the pointer, in in the Direction Flag (DF) Status. is a Byte string Operation, the index registers are it is @ word string operation, the index registers are updated ly decremented by one). oS 2 = 8 2 = & SsAssignment#1, 1. Write the functions of ALU, Adder in BIU, and Instruction Queue of the Microprocessor. 2. What is memory segmentation? What are the functions of different segments in memory? If SS= COA , CS = 123416 , DS = 258Cis , ES = 3D951e SP = 20106 , IP = 010016 , S! = 02106 , DI = 031016 , What are the logical and physical addresses of segment bases and current locations in each segment? 3. What is stack? Write the difference between stack and Queue. Write the functions of stack. 4, Fill up the memory locations based on the instructions given below. Initially: $5=F000,$P=0009, Stack: .x=4000, bx=3000, €x=5020, dx=2050 ‘mov ax, 123th id push ax 0007 ‘mov bx, 1010h ro00s |__| add bx, a 0005: push bx 0008 sub ex, 1000h push ox 0003 push dx Fo002 0001 After execution of four POP operations: pop cx pop ax pop bx pop dx What would be contents of four registers AX, BX, CX and DX? CamScanner 3 li92 4>g.uaalla plysleal adress that follows, Assinne all ‘the unknown value for each of the following physical addresses, Assume) TRIADA © 23DA i DABCO egister and the instruction pointer mt values in the code segment FF, What vale mh problem 58, what value mt in memory at ade CamScanner +Ass ignmen tue w tion (i) Write the funclions of ALU » Adder in BIU, and Insteu 2 Queue of Me Microprocessor. Solltinn Arithmetic and Logic Unik (ALU) is digital cirauk used te pecform arithmetic and Logic operations « ey AW represents the Fundamental building Unlock of Central Reecessing Unit (Pu) Adder in BIU used 4 generate tne 20 bik physical address , Gems prysical address is formed by adding 46 bits Base Address te 16 bits offset address BASE ADORESS : oF FSET Lasteuction Queue permits the 2082 IF prefech upté W byfes (Chit Ror the Boas) of instruction code. (23what is he memory segmentation? What are the Functions of different segments in memory ? iF SS= COA. CS 1234), DS=2*SBlig ES= 3095). Sr 201g = TPs oloo,g «= SEF OZIOy, = Dz 03104 Wh. ‘ ‘ a oe The Reateal address and physical address of Bren! bases and current locations ta each segnant ? Sobhition Memory segmantition is the process in which the main memory is Logically divided inte different segmants and each segment as its own base address. There ave all 4 of 7 +B nth sar meatus ab atne 05,655 Code sagmont (CS) + helds the pregram insivuction code . Data sagmunt (DS) holds the data of the program . Extra sound 5) :Pten used Por shared data Stack 34g GSS) + used 16 stere intercupt and subroutine retirn addresses, ACH pelt MS ese ~ CamScanner 4 Lied a>gusall A= Ww Wp i\z sszcom, | cs-usug | vsersee,| esrapane! SPr2OlOe | IP = 01006 | Si-or0% | DI eotlo 515? caizp | ostsr @s;or eit tt sole H [= 258C HrozaH] = F095 HW soto W Logical Address [= const: 20104 i . coAodu iasudu | wsecdy | 2095hq phy sical Abbess 2oOlOye olsons Savers ates ee ctiee Address, CZA10 W 1244o 25Ab0 3a0Cbo " Z * —l___ Es | Copco ani THEO] 240 | 2BCpofihitES|2sacon) | 40954 ; oid= 0100! a Maat oven Cet = oybll c2no¥ = vauo | tespza|25ADOH | gsenfeyie}zoccen (B\what is the stake ? write the difference belween stack and Queue. Write te function of stack. Solum The ckack is asechion of read furite memory (RAM “Ve diference betinan stack and Queve stack isan order List of elements ——~ are made ak the Same end. Keowas (LIFO) Last ain Firsk out viereas quae is exactly the 6 Sppolite of stack which is open al both ine ends meaning one end is used te insert data while he other te remove olata . known as (FIFO) First. in - Last -ouk- Ovawn where all insertion and deletions Finc\ion 4 stock. _ stere information temporarily. Seb ab oe ee — fartic main principal operations Okush stering contents L cpy register in the stack. @POP Loading Contents of the strck inte CPU registers CamScanner 3 li92 4>g.uaall(2). Fil up the memory locations based on the instructions given below Stadt Foeog| Foo #| Feoes Fos FoooH Fooo3 Fece2| Foo! ‘By intially sszFo0o SP = 0009 ax= 4000 5 bx=3000 4 CX= 5030 4 dx=2050 mov aX,IZ31h push ax mov b%s lolgh add by ,ax Push by Sub Cx, locoh Push cK Push dx After execution of four PoP operations pop CX pop aX por »X pop IX — wrak would be Ake cartels cP four registios ANB sal OX? Sittin —> Feveg mev ax,\231h => awzIzah ; reco | hn ears ForoB Fooo row —s] 3 Pusmon me SPE oreF 28th ae La ee] mov bx, 1010 => bx=loloh Foe S[_H1 : Fooou| Ho ald bx, ax =e BH NLS Feel eo aa bea 124th Fooo! |e. Push bX > spscoes gy. ene Fuses Sub cx, mn Wich > ck eae lo 06 - cx= 4030h PU CK > SPz e503 Foo Feet push dx Secs exs Ho Fo bh oti Seco! Feeot Fowl Atter execition PoP instructions X= 2o Fok Pop cx c= 2050h por aX ay = 4030 h por PX bye i24ih por aK dx-<1231W CamScanner 3 li92 4>g.uaallTB] Calculate tHe vobue. of He physical addresses thas Pallows. (| All numbers are Reradecimat mumbers = Physical) address ooo © 123+ @® }000:1234 LI2@34hH «— © olo0: ABCO ol000 AgBc D+ oBBC Dhe— : 2 © A200: 426F Ag Az @ B2co: FAIS?) c2 ooo 2crt+ 20 Fre— B2Coo 12+ 6 1 2he— (56) Find he unknown value fer each f the Flowing physical = adresses. Assume nuntbers bie @ Aooo : 2 =Aol2z3 © 7: MDA= 235DA © D765: 7 = DABCO @® ?:ch2i = 3202) are foradociwell namnbers unknown value A0123 - A0008) Q-= ol23 ee 235DA IY4DA7 a 221007 h wQerow ~ DABC ptE6S5 “GSISh B2deI guaall °o oOBA) UP Current value of the code aepunl ropistir andthe iashuchion potter are o2oo¢ and orc ie vespechivelyy Whab physical address is used sn cthe newt dusbucbon (etch valliles 2s CS= 0200 o tpe el Ac 1K ' ) ( =, Physic al Address = es e200 0 ue oOl1Ac4 oO 2 \A Cy a A “ul sequent i be be located om cubhess Acooo, ts AV FFF 6 + Whak vetlue must be ( sx led m DS? 18 Salli (9) WP the data Sey problem 58. What yahe mut be Leaded! ints DT ikit is Le pont regis ler corifains the viclue found rn te adlestadlion ope rand Atored in me mony a address Aiz3u,6 ? Sollitins £ OSs ACO, y ps: Dre RA physical Address = N234 6 i ° Aooo: “2 = ARSE PNA 1234 > “(ep Aoo 00 ~ 1234 CamScanner 3 li92 é>s.uaall£E390 (Digital Systems Engineering) Quiz #4 Student Name: Student 1D: Write the functions of ALU, Adder in BIU and Instruction Queue f Write the logical and physical addresses of each segment b current locations in the segment, wk if S55 ADEDs.. CS = 2100, OS = 2500;¢, ES = 30005 Sa SP = 2010,,, 1P = 0100y, SI = 0210,,, D1 = 031050, {5 Marks] 2. (i) Fill up the memory locations based on the PUSH instructions given. Jechute below. * : 6 ede Marks} Stack mov a4, 1030h pashan mov bx, 2232 sub bat > aye eeshdn so adder, 1900h qeot push ch pushdy (ii) After execution of four POP operations: ‘popdx pK 29.050 bh 2 POD. sista en eran Oo cae boon 2\bvLh pop ax oy ey = (bon What would be contents of four registers AX, BX, Ch and DX? CamScanner 3 li92 4>g.uaallx xlipiloxx Important Questions Port @) — TS =—_ Owrite the Rnckons of Bus Lnlerface Unit (ZU) and Execution Unit (EU) the microprocessor. How do they work on earalle) er Ryher porformance ? Soluion na ap > Bus litedface Unik (BIU) is Fespoasible Ror performing all otternall lus operations such a5 instrudion Petehing readiay and writing ‘dala operands Br memory. Ik js also performs other hunetons related te inskucton d dats ist such that inskucton queuing and adirest generation, *ftist = Execution Unit (EU) is cesponsible for decoding and execuiling instructions. => Thay work on parallel Rr fagher performance : EV accesses iastrudtions, generates data addeess if necessary 5 passes them ts B1IU and requests it to perform the read or write operation 25 memory or 1/0 2 and pertorms the operation specified by the instruction. tase@ ersied ony i Ate data registers @ Write *he Fanctions of al\ he data regi ee Wete the main usages of the dia registers AX,BX> CX and DX. Sabin @ Aris the Accumulctir register perform some of the operations > such as MUL and DIV - Alt inpuk/oulput operations muck use accumulator register AL or AX Gr dala @BX is he Base register the only general purpose register wich maybe used For indirect addressing « For example Mev [ax], AX sad For indirect adores! tasteuckions ( Loop ,Le0pe xd LeopNe) | OCX isthe Counk register perform <+O le Oshitt and ritste instructions (eer, Rew, ROL ROR, SHH SHR and SAR) Ost tions (6, REPE and REPWE) alluse the Counter register 6 defermine ow many times they will repeal Q@DK_is the Data register used tagether with AX Gr the word size MUL and Dav sverton ~ Ht had the pork nuhber form 0UT iastudions. — available aGalerient place ste dzfy. CamScanner 3 li92 é>s.uaalltrod Owrite ne sex/resot conditions Rr all SEES Piags Sabbihin i ° row) -in ) if there is a carry-ouk or a borre Orherwise, CF is resol 2 Carry Fiag (CF): CF is sex (crs Re MSB during execuilion fan instruction. 2 Paciky Fiag (PF), PF is sek (PF=1) if result produce by jaslzudion has even . parity (even eumber of bils ok fogie 4). IF warily is odd, PF is reset. 3 Auxiliary Flag(AF): AF is sik (AF=) iP there is corcyouk From lower nipale te Tigfer pple or Berrew-in From Ragher ripple 4s Lower nipple, Otherwise, AF is reset. 4 Zero Fag (2F) + Ze isset (2F=0 if the result produced by an instruction iszaro, otherwise, ZF is reset. & Sige Flag GE): M88 of the result is copied inde SF. SSS SF issak Ga) iP the resubk is anegative number, SF is vesek iF the result cs positive. S& OverFlow Flag OF) OF is sek (oF=1) , it sadicates thal he signed reaulk is out oF range. OF is reset if) He result ig net ouk of range. Ze ee FD ADE blagsdt em (3) Whak is memory sogmantation ? Weite the main uses of dif Saeki ‘ 2 ‘a memory 7 . Salut * Assigamodttl cia yasin _ Eve th 8088/2086 has 1Mibyte address space , not all thamesery activate ab one Times A MBykes of memory ane partionedd ints Suk, ’ bute segment — Only Pour of these 64 Kuste symuds are adivate at sty, ime: CS, DS, Es,ss. OGde Segneet C5): holds He program inshudlion code, @ Dla segmort (D5): holds the dati of the Pregran. \@ eda sugar Es): Pin used Rr shared dats. DStack Segal (55): used 43 steve talerrupt and subroutine réheen addresses. CamScanner 2 li92 4>g.uaallGntinue 2 Ankecruct Enable Flag (SE) + “Te recognize isteveupt nequists ab is aaterruph (ar) ine, ZF Play musk be seb. when IE cesat, repeat ot INT are ignored! andl interrupt interbace is clisabledl . inetion = When set, -the string instruction automatically olecrement’s the address. (ame string data transfers proceed Crom tnigh address fs Dow address) — rest DE causes data te transfers proceed Prom Low address fs Pegl address. Jo ) 2 usadte countiol the direction f-the string operilions, 9 Tap Flag (TE) 2 TE Sak allows the prmgram Jo single step (execute one 2 ber AN a) "9 instruction ak atime) » Uses! for debugging purpasas: CamScanner 3 li92 4>g.uaall