8051 Data Transfer Instructions

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Data Transfer Operations

A, Acc: Accumulator
B: B special function register
C: Carry flag in PSW
Rn: Register R7-R0 of the currently selected Register Bank.
dir: 8-bit internal data location’s address. This could be an Internal Data RAM
location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-
255)]. Direct Addressing Mode.
@Ri : 8-bit internal data RAM location (0-255) addressed indirectly through
register R1or R0. Indirect Addressing Mode.
#data: 8-bit constant included in instruction. Immediate Addressing Mode.
#data 16: 16-bit constant included in instruction. Immediate Addressing Mode.
addr 16: 16-bit destination address. Used by LCALL and LJMP. A branch can be
anywhere within the 64K byte Program Memory address space. Long Addressing
Mode.
addr 11: 11-bit destination address. Used by ACALL and AJMP. The branch will be
within the same 2K byte page of program memory as the first byte of the following
instruction. Absolute Addressing Mode.
rel: Signed (two’s complement) 8-bit offset byte. Used by SJMP and all conditional
jumps. Range is -128 to +127 bytes relative to first byte of the following instruction.
Relative Addressing Mode.
bit: Direct Addressed bit in Internal Data RAM or Special Function Register
1B: 1 byte
2B: 2 byte
3B: 3 byte
1C: 1 cycle
2C: 2 cycles
4C: 4 cycles
P: oscillator Period

Mnemonic Description

MOV A,Rn Move register to Accumulator

[1B,1C,12P]

MOV A,direct Move direct byte to Accumulator

[2B,1C,12P]

MOV A,@Ri Move indirect RAM to Accumulator

[1B,1C,12P]

1/4
MOV A,#data Move immediate data to Accumulator
[2B,1C,12P]

MOV Rn,A Move Accumulator to Register

[1B,1C,12P]

MOV Rn,direct Move direct byte to register

[2B,2C,24P]

MOV Rn,#data Move immediate data to Register

[2B,1C,12P]

MOV direct,A Move Accumulator to direct byte

[2B,1C,12P]

MOV direct,Rn Move register to direct Byte

[2B,2C,24P]

MOV direct,direct Move direct byte to direct

[3B,2C,24P]

MOV direct,@Ri Move indirect RAM to direct byte

[2B,2C,24P]

MOV direct,#data Move immediate data to direct byte

[3B,2C,24P]

MOV @Ri,A Move Accumulator to indirect RAM

[1B,1C,12P]

MOV @Ri,direct Move direct byte to indirect RAM

[2B,2C,24P]

MOV @Ri,#data Move immediate data to indirect RAM

[2B,2C,24P]

MOV DPTR,#data16 Load Data Pointer with a 16-bit constant

[3B,2C,24P]

MOVC A,@A+DPTR Move Code byte relative to DPTR to Acc

[1B,2C,24P]

MOVC A,@A+PC Move Code byte relative to PC to Acc

[1B,2C,24P]

MOVX A,@Ri Move External RAM (8-bit addr) to Acc

[1B,2C,24P]

MOVX A,@DPTR Move Exernal RAM (16-bit addr) to Acc

[1B,2C,24P]

MOVX @Ri,A Move Acc to External RAM (8-bit addr)

[1B,2C,24P]

MOVX @DPTR,A Move Acc to External RAM (16-bit addr)

[1B,2C,24P]

2/4
 PUSH direct Push direct byte onto Stack
[2B,2C,24P]

POP direct Pop direct byte from Stack

[2B,2C,24P]

XCH A,Rn Exchange register with Accumulator

[1B,1C,12P]

XCH A,direct Exchange direct byte with Accumulator

[2B,1C,12P]

XCH A,@Ri Exchange indirect RAM with Accumulator

[1B,1C,12P]

XCHD A,@Ri Exchange low-order Digit indirect RAM with Acc

[1B,1C,12P]

Move
MOV instruction is concerned with moving data internally
MOV R2, #80h ; Move immediate data value 80h to register R2
MOV R4, A ; Copy data from accumulator to register R4
MOV DPTR, #0F22Ch ; Move immediate value F22Ch to the DPTR register
MOV R2, 80h ; Copy data from 80h (Port 0 SFR) to R2
MOV 52h, #52h ; Copy immediate data value 52h to RAM location 52h
MOV 52h, 53h ; Copy data from RAM location 53h to RAM 52h
MOV A, @R0 ; Copy contents of location addressed in R0 to A
MOVX instruction is used to access the external memory (X indicates eXternal memory
access). All external moves must work through the A register (accumulator).
MOVX @DPTR, A ; Copy data from A to the address specified in DPTR
MOVX A, @DPTR ; Copy data from address specified in DPTR to A
MOVC instruction is used to read data from the external code memory (ROM).
MOV DPTR, # 2000h ; Copy the data value 2000h to the DPTR register
MOV A, #80h ; Copy the data value 80h to register A
MOVC A, @A+DPTR ; Copy the contents of the address 2080h (2000h + 80h) to register
A

PUSH and POP

PUSH and POP instructions are used with the stack only
PUSH 4Ch ; Contents of RAM location 4Ch is saved to the stack. SP is incremented.
PUSH 00h ; The content of R0 (which is at 00h in RAM) is saved to the stack and SP is
incremented.
POP 80h ; The data from current SP address is copied to 80h and SP is decremented.

Exchange
XCH (eXCHange) instruction is used to swap the data between source and destination,
effectively changing the source data. XCH instructions must use register A. XCHD is a
special case of the exchange instruction where just the lower nibbles are exchanged.

3/4
XCH A, R3 ; Exchange bytes between A and R3
XCH A, @R0 ; Exchange bytes between A and RAM location whose address is in R0
XCH A, A0h ; Exchange bytes between A and RAM location A0h (SFR port 2)

4/4
Arithmetic group in 8051
tutorialspoint.com/arithmetic-group-in-8051

In 8051 Microcontroller there are 24 different instructions under the Arithmetic Group.
In total there are 64 opcodes. The Carry Flag (CY), Auxiliary Carry (AC)and Overflow flag
(OV) are affected based on the result of ADD, ADDC, SUBB etc. instructions. The
multiple and divide instructions clear the Carry flag, and also does not affect the AC flag.
After execution of multiplication, the OV flag will be 1 when the result is greater than
FFH. Otherwise, it is 0. Similarly, after division OV flag is 1 when the content of B is 00H
before division, otherwise it is 0. The DA A (Decimal Adjust Accumulator) affects the
Carry Flag only.

In the following table, we will see the Mnemonics, Lengths, Execution Time in terms of
the machine cycle, Number of Opcodes etc.

Mnemonics Byte Count execution time OpcodeCount

ADD A, Rn 8

ADD A, a8 1

ADD A, @Ri 2

ADD A, #d8 1

ADDC A, Rn 8

ADDC A, a8 1

ADDC A, @Ri 2

ADDC A, #d8 1

SUBB A, Rn 8

SUBB A, a8 1

SUBB A, @Ri 2

SUBB A, #d8 1

INC A 1

INC Rn 8

INC a8 1

INC @Ri 2

DEC A 1

1/3
Mnemonics Byte Count execution time OpcodeCount

DEC Rn 8

DEC a8 1

DEC @Ri 2

INC DPTR 1

MUL AB 1

DIV AB 1

DA A 1

Examples

Sr.No Instruction & Description

1 ADD A, 32H
This is an instruction of type ADD A, #d8. The immediate data 32H is added to
register A. The result is also stored in A.

2 ADDC A, @R1
This is an instruction of type ADDC A, @Ri. It means the content on internal
RAM location which is pointed by register R1 is added to A.

3 SUBB A, R5
This is SUBB A, Rn type instruction. The SUBBstands for Subtract with
borrow. So the content of R5 will be subtracted from A.

4 INC 40H
This is a type of INC a8. Here the content in local RAM whose address is 40H,
it is increased by 1.

5 INC DPTR
It can increase the content of DPTR by 1. This instruction takes two machine
cycle to execute.

6 MUL AB
This instruction is used to multiply the content of register A and B. The 16-bit
address will be stored at B and A registers. The B will hold the MS byte, and A
will hold the LSByte.

7 DIV AB
This instruction is used to divide the content of A register by B register. The 8-
bit quotient is stored into the register A, and the 8-bit remainder is stored into
the register B.

2/3
3/3
8051 Logical Operation Instructions
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Logical Operations

A, Acc: Accumulator
B: B special function register
C: Carry flag in PSW
Rn: Register R7-R0 of the currently selected Register Bank.
dir: 8-bit internal data location’s address. This could be an Internal Data RAM
location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-
255)]. Direct Addressing Mode.
@Ri : 8-bit internal data RAM location (0-255) addressed indirectly through
register R1or R0. Indirect Addressing Mode.
#data: 8-bit constant included in instruction. Immediate Addressing Mode.
#data 16: 16-bit constant included in instruction. Immediate Addressing Mode.
addr 16: 16-bit destination address. Used by LCALL and LJMP. A branch can be
anywhere within the 64K byte Program Memory address space. Long Addressing
Mode.
addr 11: 11-bit destination address. Used by ACALL and AJMP. The branch will be
within the same 2K byte page of program memory as the first byte of the following
instruction. Absolute Addressing Mode.
rel: Signed (two’s complement) 8-bit offset byte. Used by SJMP and all conditional
jumps. Range is -128 to +127 bytes relative to first byte of the following instruction.
Relative Addressing Mode.
bit: Direct Addressed bit in Internal Data RAM or Special Function Register
1B: 1 byte
2B: 2 byte
3B: 3 byte
1C: 1 cycle
2C: 2 cycles
4C: 4 cycles
P: oscillator Period

Mnemonic Description

ANL A,Rn AND Register to Accumulator

[1B,1C,12P]

ANL A,direct AND direct byte to Accumulator

[2B,1C,12P]

ANL A,@Ri AND indirect RAM to Accumulator

[1B,1C,12P]

1/3
ANL A,#data AND immediate data to Accumulator
[2B,1C,12P]

ANL direct,A AND Accumulator to direct byte

[2B,1C,12P]

ANL direct,#data AND immediate data to direct byte

[3B,2C,24P]

ORL A,Rn OR Register to Accumulator

[1B,1C,12P]

ORL A,direct OR direct byte to Accumulator

[2B,1C,12P]

ORL A,@Ri OR indirect RAM to Accumulator

[1B,1C,12P]

ORL A,#data OR immediate data to Accumulator

[2B,1C,12P]

ORL direct,A OR Accumulator to direct byte

[2B,1C,12P]

ORL direct,#data OR immediate data to direct byte

[3B,2C,24P]

XRL A,Rn Exclusive-OR Register to Accumulator

[1B,1C,12P]

XRL A,direct Exclusive-OR direct byte to Accumulator

[2B,1C,12P]

XRL A,@Ri Exclusive-OR indirect RAM to Accumulator

[1B,1C,12P]

XRL A,#data Exclusive-OR immediate data to Accumulator

[2B,1C,12P]

XRL direct,A Exclusive-OR Accumulator to direct byte

[2B,1C,12P]

XRL direct,#data Exclusive-OR immediate data to direct byte

[3B,2C,24P]

CLR A Clear Accumulator

[1B,1C,12P]

CPL A Complement Accumulator

[1B,1C,12P]

RL A Rotate Accumulator Left

[1B,1C,12P]

RLC A Rotate Accumulator Left through the Carry

[1B,1C,12P]

2/3
 RR A Rotate Accumulator Right
[1B,1C,12P]

RRC A Rotate Accumulator Right through the Carry

[1B,1C,12P]

SWAP A Swap nibbles within the Accumulator

[1B,1C,12P]

Boolean operations
ANL Logical AND
ORL Logical OR
CPL Complement (logical NOT)
XRL Logical XOR (exclusive OR)

ANL A, #55h ; AND each bit in A with corresponding bit in number 55h, leaving the result
in A.
ANL 42h, R4 ; AND each bit in RAM location 42h with corresponding bit in R4, leaving
the result in RAM location 42h.
ORL A,@R1 ; OR each bit in A with corresponding bit in the number whose address is
contained in R1 leaving the result in A.
XRL R4, 80h ; XOR each bit in R4 with corresponding bit in RAM location 80h (port 0),
leaving result in A.
CPL R0 ; Complement each bit in R0

Rotate
The ability to rotate the A register (accumulator) data is useful to allow examination of
individual bits. The options for such rotation are as follows:
RL A ; Rotate A one bit to the left. Bit 7 rotates to the bit 0 position
RLC A ; The Carry flag is used as a ninth bit in the rotation loop
RR A ; Rotates A to the right (clockwise)
RRC A ; Rotates to the right and includes the carry bit as the 9th bit.

Swap
The Swap instruction swaps the accumulator’s high order nibble with the low-order
nibble using the instruction.
SWAP A

3/3
8051 Program Branching Instructions
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Program Branching Operations

A, Acc: Accumulator
B: B special function register
C: Carry flag in PSW
Rn: Register R7-R0 of the currently selected Register Bank.
dir: 8-bit internal data location’s address. This could be an Internal Data RAM
location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-
255)]. Direct Addressing Mode.
@Ri : 8-bit internal data RAM location (0-255) addressed indirectly through
register R1or R0. Indirect Addressing Mode.
#data: 8-bit constant included in instruction. Immediate Addressing Mode.
#data 16: 16-bit constant included in instruction. Immediate Addressing Mode.
addr 16: 16-bit destination address. Used by LCALL and LJMP. A branch can be
anywhere within the 64K byte Program Memory address space. Long Addressing
Mode.
addr 11: 11-bit destination address. Used by ACALL and AJMP. The branch will be
within the same 2K byte page of program memory as the first byte of the following
instruction. Absolute Addressing Mode.
rel: Signed (two’s complement) 8-bit offset byte. Used by SJMP and all conditional
jumps. Range is -128 to +127 bytes relative to first byte of the following instruction.
Relative Addressing Mode.
bit: Direct Addressed bit in Internal Data RAM or Special Function Register
1B: 1 byte
2B: 2 byte
3B: 3 byte
1C: 1 cycle
2C: 2 cycles
4C: 4 cycles
P: oscillator Period

Mnemonic Description

ACALL addr11 Absolute Subroutine Call

[2B,2C,24P]

LCALL addr16 Long Subroutine Call

[3B,2C,24P]

RET Return from Subroutine

[1B,2C,24P]

1/3
 RETI Return from interrupt
[1B,2C,24P]

AJMP addr11 Absolute Jump

[2B,2C,24P]

LJMP addr16 Long Jump

[3B,2C,24P]

SJMP rel Short Jump (relative addr)

[2B,2C,24P]

JMP @A+DPTR Jump indirect relative to the DPTR

[1B,2C,24P]

JZ rel Jump if Accumulator is Zero

[2B,2C,24P]

JNZ rel Jump if Accumulator is Not Zero

[2B,2C,24P]

CJNE A,direct,rel Compare direct byte to Acc and Jump if Not Equal
[3B,2C,24P]

CJNE A,#data,rel Compare immediate to Acc and Jump if Not Equal

[3B,2C,24P]

CJNE Rn,#data,rel Compare immediate to register and Jump if Not Equal

[3B,2C,24P]

CJNE @Ri,#data,rel Compare immediate to indirect and Jump if Not Equal

[3B,2C,24P]

DJNZ Rn,rel Decrement register and Jump if Not Zero

[2B,2C,24P]

DJNZ direct,rel Decrement direct byte and Jump if Not Zero

[3B,2C,24P]

NOP No operation
[1B,1C,12P]

Jump
LJMP (long jump) causes the program to branch to a destination address defined by the
16-bit operand in the jump instruction. Because a 16-bit address is used the instruction
can cause a jump to any location within the 64KByte program space (216 = 64K).
LJMP LABEL_X ; Jump to the specified label
LJMP 0F200h ; Jump to address 0F200h
LJMP @A+DPTR ; Jump to address which is the sum of DPTR and Reg. A

2/3
SJMP (short jump) uses a singe byte address. This address is a signed 8-bit number and
allows the program to branch to a distance –128 bytes back from the current PC address
or +127 bytes forward from the current PC address.

AJMP allows a jump with a 2KByte address boundary (a 2K page)

Most 8051 jump instructions use an 8-bit destination address, based on relative
addressing, i.e. addressing within the range –128 to +127 bytes.
JZ LABEL_1 ; Jump to LABEL_1 if accumulator is equal to zero
JNZ LABEL_X ; Jump to LABEL_X if accumulator is not equal to zero
JNC LABEL_Y ; Jump to LABEL_Y if the carry flag is not set
DJNZ R2, LABEL ; Decrement R2 and jump to LABEL if the resulting value of R2 is not
zero.
CJNE R1, #55h , LABEL_2 ; Compare the magnitude of R1 and the number 55h and jump
to LABEL_2 if the magnitudes are not equal.

Call
LCALL instruction is used to call a subroutine at a specified address. The address is 16
bits long so the call can be made to any location within the 64KByte memory space.

ACALL instruction is logically similar to the LCALL but has a limited address range
similar to the AJMP instruction.

Return
The return from subroutine is achieved using the RET instruction.

3/3
8051 IO Port Programming
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In the 8051 there are a total of four ports for I/O operations. A total of 32 pins are set
aside for the four ports PO, P1 P2, and P3, where each port takes 8 pins.

The four ports PO, P1, P2, and P3 each use 8 pins, making them 8-bit ports. All the ports
upon RESET are configured as inputs, ready to be used as input ports. When the first 0 is
written to a port, it becomes an output. To reconfigure it as an input, a 1 must be sent to
the port.

Toggle all the bits:

ORG 0H

MOV P0, #0H ; make P0 an output port

MOV P1, #0H ; make P1 an output port

MOV P2, #0H ; make P2 an output port

MOV P3, #0H ; make P3 an output port

BACK : MOV P0, #55H

MOV P1, #55H

MOV P2, #55H

MOV P3, #55H

ACALL DELAY

MOV P0, #0AAH

MOV P1, #0AAH

MOV P2, #0AAH

MOV P3, #0AAH

ACALL DELAY

SJMP BACK

; Delay Subroutine

ORG 500H ; put time delay subroutine at program memory location

500H

1/5
 DELAY MOV R3, ; initialize the counter
: #0FFH

LOOP : DJNZ R3, ; stay her until r5 = 0

LOOP

RET ; return to caller

END

Get a byte from port 0 and send it to port 1:

ORG 0H

MOV P0, #0FFH ; make P0 an input port

MOV P1, #0H ; make P1 an output port

BACK : MOV A, P0

MOV P1, A

SJMP BACK

END

Bit Addressability:
Sometimes we need to access only 1 or 2 bits of the port instead of the entire 8 bits. When
accessing a port in single-bit manner, we use the syntax “SETB X. Y” where X is the port
number 0, 1,2. or 3, and Y is the desired bit number from 0 to 7.

Toggle P0.1:

ORG 0H

MOV P0, #0H ; make P0 an output port

AGAIN: SETB P0.1

ACALL DELAY

CLR P0.1

ACALL DELAY

SJMP AGAIN

2/5
; Delay Subroutine

ORG 500H ; put time delay subroutine at program memory location

500H

DELAY MOV R3, ; initialize the counter

: #0FFH

LOOP : DJNZ R3, ; stay her until r5 = 0

LOOP

RET ; return to caller

END

Single Bit Instruction:

Instruction Function

SETB bit Set the bit (bit = 1)

CLR bit Clear the bit (bit = 0)

CPL bit Complement the bit (bit = NOT bit)

JB bit, target Jump to target if bit = 1

JNB bit, target Jump to target if bit = 0

JBC bit, target Jump to target if bit = 1, Clear bit

Monitoring an IO pin:

ORG 0H

SETB P0.1 ; make P0.1 an input pin

AGAIN : JNB P0.1, AGAIN

MOV P0, #55H

END

Instruction for Reading an Input Port:

3/5
 Mnemonic Example Description

MOV A, PX MOV A, P0 Bring in to A the data at P0 pins

JNB PX.Y, target JNB P0.1, LABEL Jump if P0.1 = 0

JB PX.Y, target JB P0.1, LABEL Jump if p0.1 = 1

MOV C, PX.Y MOV C, P0.1 Copy the status of P0.1 to Carry flag

Instructions reading a Latch:

In reading a port, some instructions read the status of port pins while others read the
status of an internal port latch.

Mnemonic Example

ANL PX, A ANL P0, A

ORL PX, A ORL P0, A

XRL PX, A XRL P0, A

JBC bit, target JBC P0.1, LABEL

CPL PX.Y CPL P0.1

INC PX INC P0

DEC PX DEC P0

DJNZ PX.Y, target DJNZ P0.1. LABEL

MOV PX.Y, C MOV P0.1, C

SETB PX.Y SETB P0.1

CLR PX.Y CLR P0.1

The instructions that read the port latch normally read a value, perform an operation (and
possibly change it), then rewrite it back to the port latch. This is often called “Read-
Modify-Write”. A single instruction can be used to read the port, modify its value and
write the result back to port.

ORG 0H

MOV P0, #55H

4/5
AGAIN: XRL P0, ; read P0, XOR P0 with FFH and write the result back to
#0FFH P0

ACALL DELAY

SJMP AGAIN

; Delay Subroutine

ORG 500H ; put time delay subroutine at program memory location

500H

DELAY MOV R3, ; initialize the counter

: #0FFH

LOOP : DJNZ R3, ; stay her until r5 = 0

LOOP

RET ; return to caller

END

5/5
8051 Timer Programming
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The 8051 has two timers/counters. They can be used either as timers to generate a time
delay or as counters to count events happening outside the microcontroller.

The two timers, Timer 0 and Timer 1, are 16-bit wide. Both timers 0 and 1 use the same
register, called TMOD, to set the various timer operation modes. There are three modes:
0, 1, 2 and 3. Mode 0 is a 13-bit timer, mode 1 is a 16-bit timer, mode 2 is an 8-bit timer
and mode 3 is split timer mode.

C/T bit in the TMOD register is used to decide whether the timer is used as a delay
generator or an event counter. If C/T = 0, it is used as a timer for time delay generation.
The clock source for the time delay is the crystal frequency of the 8051.

The timers in the 8051 can be controlled by both software and hardware. The start and
stop of the timer are controlled by way of software by the TR (timer start) bits TRO and
TR1. Software instructions start and stop the timers as long as GATE = 0 in the TMOD
register. The hardware way of starting and stopping the timer by an external source is
achieved by making GATE = 1 in the TMOD register.

Mode 1:

It is a 16-bit timer; therefore, it allows values of 0000 to FFFFH to be loaded into

the timer’s registers TL and TH.
After TH and TL are loaded with a 16-bit initial value, the timer must be started.
This is done by “SETB TRO” for Timer 0 and “SETB TR1″for Timer 1.
After the timer is started, it starts to count 1. up. It counts up until it reaches its limit
of FFFFH. When it rolls over from FFFFH to 0000, it sets high a flag bit called TF
(timer flag). This timer flag can be monitored. When this timer flag is raised, one
option would be to stop the timer with the instructions “CLR TRO” or “CLR TR1″,
for Timer 0 and Timer 1, respectively. Again, it must be noted that each timer has its
own timer flag: TFO for Timer 0, and TF1 for Timer 1.
After the timer reaches its limit and rolls over, in order to repeat the process the
registers TH and TL must be reloaded with the original value, and TF must be reset
to 0.

ORG 0H

MAIN : MOV TMOD, #01H ; Timer 0, mode 1

START : MOV TL0, #0F2H ; load F2 in to TL0

MOV TH0, #0FFH ; load FF in to TH0

1/5
 CPL P1.5 ; toggle P1.5

ACALL DELAY

SJMP START

; delay using timer 0

ORG 100H

DELAY: SETB TR0 ; start timer 0

LOOP : JNB TF0, LOOP ; monitor timer flag 0 until it rolls over

CLR TR0 ; stop timer

CLR TF0 ; clear timer 0 flag

RET

END

Delay calculation for XTAL = 11.0592 MHz is Delay = (FFFF – YYXX + 1) * 1.085 µs
where YYXX are TH, TL initial values respectively. Notice that values YYXX are in hex.

Timer delay = (FFFF – FFF2 + 1) * 1.085 µs = 15.19 µs

To get the largest delay we make TL and TH both 0. This will count up from 0000 to
FFFFH and then roll over to zero.
Largest delay = (65536 – 0) * 1.085 µs = 71106.56 µs = 71.1065 ms.

For known delay, to find the values needed for the TH, TL registers,

Divide the desired time delay by 1.085 µs.

Perform 65536 – n, where n is the decimal value we got in Step 1
Convert the result of Step 2 to hex, where yyxx is the initial hex value to be loaded
into the timer’s registers
Set TL = xx and TH = yy.

To get values for 50ms,

50 ms / 1.085 µs = 46082
65536 – 46082 = 19454 = 4BFEH. Therefore, we have TH = 4B and TL = FE

ORG 0H

MAIN : MOV TMOD, #01H ; Timer 0, mode 1

2/5
 START : CPL P1.5 ; toggle P1.5

MOV R2, #20 ; count for multiple delay

LOOP1 : MOV TL0, #4BH ; load 4B in to TL0

MOV TH0, #0FEH ; load FE in to TH0

ACALL DELAY

DJNZ R2, LOOP1

SJMP START

; delay using timer 0

ORG 100H

DELAY : SETB TR0 ; start timer 0

LOOP2 : JNB TF0, LOOP2 ; monitor timer flag 0 until it rolls over

CLR TR0 ; stop timer

CLR TF0 ; clear timer 0 flag

RET

END

Mode 0:
Mode 0 is exactly like mode 1 except that it is a 13-bit timer instead of 16-bit. The 13-bit
counter can hold values between 0000 to 1FFFH in TH – TL. Therefore, when the timer
reaches its maximum of 1FFH, it rolls over to 0000, and TF is raised.

Mode 2:

It is an 8-bit timer; therefore, it allows only values of 00 to FFH to be loaded into

the timer’s register TH.
After TH is loaded with the 8-bit value, the 8051 gives a copy of it to TL. Then the
timer must be started. This is done by the instruction “SETB TR0” for Timer 0 and
“SETB TR1” for Timer 1.
After the timer is started, it starts to count up by incrementing the TL register. It
counts up until it reaches its limit of FFH. When it rolls over from FFH to 00, it sets
high the TF (timer flag). If we are using Timer 0, TFO goes high; if we are using
Timer 1, TF1 is raised.

3/5
 When the TL register rolls from FFH to 0 and TF is set to 1, TL is reloaded
automatically with the original value kept by the TH register. To repeat the process,
we must simply clear TF and let it go without any need by the programmer to reload
the original value. This makes mode 2 an auto-reload, in contrast with mode 1 in
which the programmer has to reload TH and TL.

In auto-reload, TH is loaded with the initial count and a copy of it is given to TL. This
reloading leaves TH unchanged, still holding a copy of the original value.

ORG 0H

MAIN : MOV TMOD, #02H ; Timer 0, mode 2

MOV TH0, #0H ; load 00 in to TH0

START : MOV R2, #250 ; count for multiple delay

LOOP : ACALL DELAY ; call delay subroutine for 250 times

DJNZ R2, LOOP

CPL P1.5 ; toggle P1.5

SJMP START

; delay using timer 0

ORG 100H

DELAY : SETB TR0 ; start timer 0

LOOP1 : JNB TF0, LOOP1 ; monitor timer flag 0 until it rolls over

CLR TR0 ; stop timer

CLR TF0 ; clear timer 0 flag

RET

END

Delay calculation for XTAL = 11.0592 MHz is Delay = (FF – XX) * 1.085 µs where XX is
TH initial value. Notice that value XX is in hex.

Timer delay = (FF – 0) * 1.085 µs = 277.76 µs

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5/5
8051 Counter
refreshnotes.com/2016/03/8051-counter.html

8051 timers can also be used as counters to count the external events. When the
timer/counter is used as a timer, the 8051′s crystal is used as the source of the frequency.
When it is used as a counter, however, it is a pulse outside the 8051 that increments the
TH, TL registers.

The C/T bit in the TMOD register decides the source of the clock for the timer. If C/T = 0,
the timer gets pulses from the crystal. In contrast, when C/T = 1, the timer is used as a
counter and gets its pulses from outside the 8051. Therefore, when C/T = 1, the counter
counts up as pulses are fed from pins 14 (Timer 0 input) and 15 (Timer 1 input). In the
case of Timer 0, when C/T = 1, pin P3.4 provides the clock pulse and the counter counts
up for each clock pulse coming from that pin. Similarly, for Timer 1, when C/T = 1 each
clock pulse coming in from pin P3.5 makes the counter count up.

ORG 0H

MAIN : MOV TMOD, #01100000B ; counter 1, mode 2

MOV TH1, #0 ; clear TH1

SETB P3.5 ; make T1 input

START : SETB TR1 ; start counter

LOOP : MOV A, TL1 ; get copy of count TL1

MOV P2, A ; display it on port 2

JNB TF1, LOOP ; keep doing it if TF = 0

CLR TR1 ; stop the counter

CLR TF1 ; clear TF1

SJMP START

END

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8051 Serial Port
refreshnotes.com/2016/03/8051-serial-port.html

8051 has integrated Universal Asynchronous Receiver Transmitter (UART) or Serial

Port
Serial port mode of operation and baud rate can be configured

Registers:

SCON

Bit Name Function

7 SM0 Serial port mode bit 0 (see below)

6 SM1 Serial port mode bit 1 (see below)

5 SM2 Mutliprocessor Communications Enable. When set the "RI" flag will only
be triggered if the 9th bit received was a "1"

4 REN Receiver Enable. This bit must be set in order to receive characters

3 TB8 Transmit bit 8. The 9th bit to transmit in mode 2 and 3

2 RB8 Receive bit 8. The 9th bit received in mode 2 and 3

1 TI Transmit Flag. Set when a byte has been completely transmitted

0 RI Receive Flag. Set when a byte has been completely received

SM1 SM0 Mode Mode Description Baud Rate

0 0 0 8-bit Shift Register Oscillator / 12

0 1 1 8-bit UART Set by Timer 1 (*)

1 0 2 9-bit UART Oscillator / 64 (*)

1 1 3 9-bit UART Set by Timer 1 (*)

(*) Baud rate is doubled if PCON.7 (SMOD) is set.

Serial Port Initialization:

Set mode in SCON register

Set 9th bit for mode 2 and 3

Set Baud Rate:

1/2
 Mode 0: Oscillator / 12 = 11.059 MHz/12 = 921,583 baud
Mode 2: Oscillator / 64 = 11.059 MHz/64 = 172,797 baud
Mode 1 & 3: Baud rate is determined by how frequently timer 1 overflows. The most
common method is to configure timer 1 in 8-bit auto reload mode and set a reload
value (TH1) that causes Timer 1 to overflow at a frequency appropriate to generate a
baud rate.

The following equation is used to determine the TH1 value.

TH1 = 256 - ((Crystal / 384) / Baud)
If PCON.7 is set then TH1 = 256 - ((Crystal / 192) / Baud)
To achieve 19200,
TH1 = 256 - ((Crystal / 192) / Baud)
TH1 = 256 - ((11059000 / 192) / 19200)
TH1 = 256 - ((57699) / 19200)
TH1 = 256 - 3 = 253

Transmit Data:
To send a byte to the serial port one must simply write the value to the SBUF (99h)
SFR
Wait until TI bit is set

Receive Data:
Wait for the 8051 to set the RI flag
Read the value stored in the SBUF (99h) SFR

8051

2/2
8051 Programming Serial Interrupt
refreshnotes.com/2016/03/8051-programming-serial-interrupt.html

TI (transfer interrupt) is raised when the last bit of the framed data, the stop bit, is
transferred, indicating that the SBUF register is ready to transfer the next byte. RI
(received interrupt), is raised when the entire frame of data, including the stop bit, is
received. In other words, when the SBUF register has a byte, RI is raised to indicate that
the received byte needs to be picked up before it is lost (overrun) by new incoming serial
data. In the 8051 only one interrupt is set aside for serial communication. This interrupt
is used to both send and receive data. If the interrupt bit in the IE register (IE.4) is
enabled, when RI or TI is raised the 8051 gets interrupted and jumps to memory address
location 0023H to execute the ISR. In that ISR we must examine the TI and RI flags to see
which one caused the interrupt and respond accordingly.

; wake up and go to main, avoid using memory space allocated for ISR

ORG 0H

LJMP MAIN ; bypass ISR

; ISR for timer 0

ORG 0023H

LJMP ISR_SERIAL

; the main program for initialization

ORG 30H

MAIN : MOV R1, #30H ; start of serial buffer

MOV R2, #0H ; clear serial byte counter

MOV TMOD, #20H ; timer 1, auto re-load mode

MOV TH1, #-6 ; 4800 baud rate

MOV SCON, #50H ; 8-bit, 1 stop, REN enabled

MOV IE, #10010000B ; enable serial interrupt

SETB TR1 ; start timer 1

HERE : MOV A, R2

JZ HERE

1/2
 DEC R2

DEC R1

MOV SBUF, @R1 ; send the received byte

SJMP HERE ; keep doing it

; Serial port ISR

ORG 100H

ISR_SERIAL : JB TI, TRANSMIT ; jump if TI is high

MOV @R1, SBUF ; otherwise due to receive

; store the received byte in RAM

INC R1 ; point to next location in buffer

INC R2 ; increment byte counter

CLR RI

RETI ; return from interrupt

TRANSMIT : CLR TI

RETI ; return from interrupt

END

2/2
8051 Interrupts
refreshnotes.com/2016/03/8051-interrupts.html

An interrupt is some event which interrupts normal program execution

Interrupts give us a mechanism to "put on hold" the normal program flow, execute a
event specific subroutine, and then resume normal program flow as if we had never
left it.
The subroutine, called an interrupt handler, is only executed when a certain event
(interrupt) occurs.
The event may be one of the timers "overflowing," receiving a character via the serial
port, transmitting a character via the serial port, or one of two "external events".
When any of the above events occur the main program is temporarily suspended
and control is passed to a special section of code (interrupt handler) to execute some
function related to the event that occurred.
Once the execution is complete, control would be returned to the main program

Steps in Executing an Interrupt:

It finishes the instruction it is executing and saves the address of the next
instruction (PC) on the stack.
It also saves the current status of all the interrupts internally (i.e., not on the stack).
It jumps to a fixed location in memory called the interrupt vector table that holds
the address of the interrupt service routine.
The microcontroller gets the address of the ISR from the interrupt vector table and
jumps to it. It starts to execute the interrupt service subroutine until it reaches the
last instruction of the subroutine, which is RETI (return from interrupt).
Upon executing the RETI instruction, the microcontroller returns to the place where
it was interrupted. First, it gets the program counter (PC) address from the stack by
popping the top two bytes of the stack into the PC. Then it starts to execute from
that address.

Interrupt Vector Table:

This defines which section of code should execute when an interrupt occurs. The code
(interrupt handler) location is fixed or predefined. When an interrupt occurs, the main
program will be temporarily suspended and control will jump to the fixed address.

Interrupt Handler Address Flag

Interrupt (ROM Location) Pin Clearing

Reset 0000h 9 Auto

External event 0 0003h P3.2 Auto

(12)

Timer 0 overflow event 000Bh Auto

1/4
 External event 1 0013h P3.3 Auto
(13)

Timer 1 overflow event 001Bh Auto

Serial Port: 0023h Programmer

Reception/Transmission of a Clears it
byte.

A limited number of bytes is set aside for each interrupt. A total of 8 bytes from location
0003 to 000A is set aside for INT0, external hardware interrupt 0. If the service routine
for a given interrupt is short enough to fit in the memory space allocated to it, it is placed
in the vector table; otherwise, an LJMP instruction is placed in the vector table to point to
the address of the ISR. In that case, the rest of the bytes allocated to that interrupt are
unused.

ORG 0H ; wake-up ROM reset location

LJMP MAIN ; bypass interrupt vector table
; ----------wake up the main program
ORG 30H
MAIN:
....
END

Setting Interrupts:
By default at power up, all interrupts are disabled
Program may enable and disable interrupts by modifying the IE SFR (A8h).
EA bit must be set to trigger interrupt(s)

Bit Name Function

7 EA Global Interrupt Enable/Disable bit.

6 -- Undefined

5 -- Undefined

4 ES Enable Serial Interrupt

3 ET1 Enable Timer 1 Interrupt

2 EX1 Enable External 1 Interrupt

1 ET0 Enable Timer 0 Interrupt

0 EX0 Enable External 0 Interrupt

Interrupt Priority:

2/4
By default, 8051 checks interrupt conditions in the following order
External 0 Interrupt
Timer 0 Interrupt
External 1 Interrupt
Timer 1 Interrupt
Serial Interrupt

Program can set priority to interrupt. There are two levels of interrupt priority: high and
low. Interrupt priorities are controlled by IP SFR (B8h).

Bit Name Function

Bit Name Function

7 -- Undefined

6 -- Undefined

5 -- Undefined

4 PS Serial Interrupt Priority

3 PT1 Timer 1 Interrupt Priority

2 PX1 External 1 Interrupt Priority

1 PT0 Timer 0 Interrupt Priority

0 PX0 External 0 Interrupt Priority

When considering interrupt priorities, the following rules apply.

Nothing can interrupt a high-priority interrupt--not even another high priority
interrupt.
A high-priority interrupt may interrupt a low-priority interrupt.
A low-priority interrupt may only occur if no other interrupt is already executing.
If two interrupts occur at the same time, the interrupt with higher priority will
execute first. If both interrupts are of the same priority the interrupt which is
serviced first by polling sequence will be executed first.

Interrupt and Program Flow:

When an interrupt is triggered, the microcontroller does the following automatically:
The current Program Counter (PC) is saved on the stack, low-byte first.
Interrupts of the same and lower priority are blocked.
In the case of Timer and External interrupts, the corresponding interrupt flag is
cleared.
Program execution transfers to the corresponding interrupt handler vector address.
The Interrupt Handler Routine executes.

When an interrupt ends, microcontroller does the following automatically.

3/4
 Two bytes are popped off the stack into the Program Counter to restore normal
program execution.
Interrupt status is restored to its pre-interrupt status.

Important Considerations:
Microcontroller protects Program Counter only. It does not protect other registers like,
PSW
DPTR (DPH/DPL)
SP
ACC
B
Registers R0-R7

In general, interrupt routine must protect the above registers. Interrupt routine must
pushes the register values onto the stack using the PUSH instruction before executing
event handling related code. Once the execution is done, it pops the original values back
into the registers. It is generally a good idea to always protect registers by pushing and
popping it off the stack at the beginning and end of your interrupts.

4/4
8051 Assembly Programming
refreshnotes.com/2016/03/8051-assembly-programming.html

CPU can work only in binary

It is difficult for humans to deal with 0’s and 1’s in order to program the computer
A program that consists of 0s and 1s is called machine language
Assembly languages were developed to provide mnemonics for machine code
instructions.
Comparing to machine language, Programming in assembly language is easier,
faster and less prone to error.
Assembly language is referred to as low-level language because it deals directly with
the internal structure of the CPU and its registers.
Assembly language programs must be translated into machine code by a program
called an assembler.
Assembly language is a series of lines or statements of assembly language
instruction or directives (also called pseudo-instructions).
Instructions tell CPU what to do and directives give directions to the assembler

Structure of 8051 Program:

ORG

Label : mnemonic operands ; comment

END

ORG – Indicates the start of the program. It tells the assembler to place the opcode
at memory location 0
END – Indicates to the assembler the end of program or source code
Label – Allows the program to refer a line of code by name. Any label referring to an
instruction must be followed by a colon symbol (:). It is an optional field. Each label
name must be unique. Label consists of alphabets A to Z or a to z, numbers 0 – 9,
special characters question mark (?), period (.), at (@), underline (_) and dollar ($).
First character of label must be alphabetic. Mnemonics and reserved words must
not be used as label.
Mnemonic is the command to CPU
Operand(s) is the data to command. It is an optional field. Few commands do not
need data.
Comment – Comments may be at the end of a line or on a line by themselves.
Comment must begin with semicolon (;). It is an optional field.

Sample Program:

ORG ; start (origin) at location 0

1/2
START : MOV R1, #23H ; load 23H into R1

MOV R2, #32H ; load 32H in to R2

MOV A, #0 ; load 0 into A

ADD A, R1 ; add contents of R1 to A. A = A+R1. A = 23

ADD A, R2 ; add contents of R2 to A. A = A+R2. A = 55

ADD A, #10H ; add constant 10 to A. A = A+10. A = 65

END ; end of asm source file

2/2
8051 Assembling a Program
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Following are the steps to create an executable assembly program

Editor: It is to create source (myfile.asm) file with extension asm or src. The asm
extension for the source file is used by an assembler.

Assembler: It converts the assembly language instructions into machine code. The
assembler will produce an object file (.obj) and a list file (.lst). List file lists all the
opcodes, addresses and errors, if detected, in program

Linker: It takes one or more object files and produces an absolute object file with the
extension abs

OH: It is an object to hex converter. It creates a file with extension hex that is ready to
burn into ROM

List File:
It lists all the opcodes and addresses as well as
errors that the assembler detected. The
programmer uses the list file to find syntax errors.
It is only after fixing all the errors indicated in the
lst file that the obj file is ready to be input to the
linker program.

Machine Assembly
Address Language Language

0000 ORG 0H

0000 7D13 MOV R5, #13H

0002 7F23 MOV R7, #23H

0004 7400 MOV A, #0

0006 2D ADD A, R5

0007 2F ADD A, R7

0008 2412 ADD A, #12H

000A END

1/2
2/2