Data Flow Modeling of

Combinational Logic

ECE 448 – FPGA and ASIC Design with VHDL 1

Register Transfer Level (RTL) Design Description

Current Topic

Combinational
Logic
Combinational …
Logic

Registers

2
 Data-Flow VHDL

Concurrent Statements
• concurrent signal assignment
()

• conditional concurrent signal assignment

(when-else)

• selected concurrent signal assignment

(with-select-when)

3
Data-flow VHDL: Example

x
y s
cin

cout

4
 Data-flow VHDL: Example (1)

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY fulladd IS
PORT ( x : IN STD_LOGIC ;
y : IN STD_LOGIC ;
cin : IN STD_LOGIC ;
s : OUT STD_LOGIC ;
cout : OUT STD_LOGIC ) ;
END fulladd ;

5
 Data-flow VHDL: Example (2)

ARCHITECTURE dataflow OF fulladd IS

BEGIN
s <= x XOR y XOR cin ;
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;
END dataflow ;
equivalent to

ARCHITECTURE dataflow OF fulladd IS

BEGIN
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;
s <= x XOR y XOR cin ;
END dataflow ;
6
Logic Operators

• Logic operators
and or nand nor xor not xnor

• Logic operators precedence

only in VHDL-93
or later
Highest
not
and or nand nor xor xnor
Lowest

7
No Implied Precedence
Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d

Correct
y <= (a and b) or (c and d) ;

8
Signal assignment statement with a closed
feedback loop

• A signal appears in both sides of a

concurrent assignment statement
• E.g.,
q <= ((not q) and (not en)) or (d and en);
• Syntactically correct
• Form a closed feedback loop
• Should be avoided

9
 Data-Flow VHDL

Concurrent Statements
• concurrent signal assignment
()

• conditional concurrent signal assignment

(when-else)

• selected concurrent signal assignment

(with-select-when)

10
Conditional concurrent signal assignment

When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;

11
Most often implied structure

When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;

0
Value N
.… … 0
1
Value N-1 0
1 Target Signal
1
Value 2
Value 1
Condition N-1

Condition 2
Condition 1

12
Example

13
Example

14
Signed and Unsigned Types

Behave exactly like

STD_LOGIC_VECTOR
plus, they determine whether a given vector
should be treated as a signed or unsigned number.
Require
USE ieee.numeric_std.all;

15
Signed, Unsigned, STD_LOGIC_VECTOR

• Despite their syntax, SIGNED and UNSIGNED data types

are intended mainly for arithmetic operations. On the
other hand, logical operations are not allowed.

16
Operators

• Relational operators
• Can be used with std_logic_vector, signed,
and unsigned
= /= < <= > >=

• Logic and relational operators precedence

Highest not
= /= < <= > >=
Lowest and or nand nor xor xnor

17
Priority of logic and relational operators

compare a = bc
Incorrect
… when a = b and c else …
equivalent to
… when (a = b) and c else …

Correct
… when a = (b and c) else …

18
VHDL operators

19
 Data-Flow VHDL

Concurrent Statements
• concurrent signal assignment
()

• conditional concurrent signal assignment

(when-else)

• selected concurrent signal assignment

(with-select-when)

20
Selected concurrent signal assignment

With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;

21
Most Often Implied Structure
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;

expression1 choices_1
expression2 choices_2
target_signal

expressionN choices_N

choice expression

22
Allowed formats of choices_k

WHEN value

WHEN value_1 | value_2 | .... | value N

WHEN OTHERS

23
Allowed formats of choice_k - example

WITH sel SELECT

y <= a WHEN "000",
c WHEN "001" | "111",
d WHEN OTHERS;

24
Syntax

• select_expression
• Discrete type or 1-D array
• With finite possible values
• choice_i
• A value of the data type
• Choices must be
• mutually exclusive
• all inclusive
• others can be used as last choice_i
25
E.g., 4-to-1 mux

26
entity mux4 is
PORT(
s: IN std_logic_vector (1 downto 0);
a: IN std_logic;
b: IN std_logic;
c: IN std_logic;
d: IN std_logic;
x: OUT std_logic
);
end mux4;

27
Question

• Can “11” be used to replace others?

28
E.g., 2-to-22 binary decoder

29
E.g., 4-to-2 priority encoder

30
Question

• Can we use ‘-’?

31
E.g., simple ALU

32
 Simple ALU VHDL Entity Declaration

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.numeric_std.all;

ENTITY simple_alu IS
PORT ( ctrl : IN STD_LOGIC_VECTOR (2 downto 0) ;
src0 : IN STD_LOGIC_VECTOR (7 downto 0);
src1 : IN STD_LOGIC_VECTOR (7 downto 0);
result: OUT STD_LOGIC_VECTOR (7 downto 0)) ;
END simple_alu ;

33
Comparison

• "when-else" should be used when:

1. there is only one condition (and thus, only
one else), as in the 2-to-1 MUX
2. conditions are independent of each other
(e.g., they test values of different signals)
3. conditions reflect priority (as in priority
encoder); one with the highest priority
need to be tested first.

34
Comparison

• "with-select-when" should be used when

there is:
1. more than one condition
2. conditions are closely related to each
other (e.g., represent different ranges of
values of the same signal)
3. all conditions have the same priority (as in
the 4-to-1 MUX).

35
 Behavioral Modeling of
Sequential-Circuit Building
Blocks

ECE 448 – FPGA and ASIC Design with VHDL 36

VHDL Design Styles
VHDL Design
Styles

dataflow structural behavioral

Concurrent Components and Sequential statements

statements interconnects • Registers
• Shift registers
• Counters
synthesizable • State machines
and more
if you are careful
37
Processes in VHDL
• Processes Describe Sequential Behavior
• Processes in VHDL Are Very Powerful
Statements
• Allow to define an arbitrary behavior that may
be difficult to represent by a real circuit
• Not every process can be synthesized
• Use Processes with Caution in the Code to
Be Synthesized
• Use Processes Freely in Testbenches

38
Anatomy of a Process

OPTIONAL

[label:] PROCESS [(sensitivity list)]

[declaration part]
BEGIN
statement part
END PROCESS [label];

39
PROCESS with a SENSITIVITY LIST

• List of signals to which the

process is sensitive.
• Whenever there is an
event on any of the
signals in the sensitivity label: process (sensitivity list)
list, the process fires. declaration part
• Every time the process begin
fires, it will run in its statement part
entirety. end process;
• WAIT statements are
NOT ALLOWED in a
processes with
SENSITIVITY LIST.

40
Component Equivalent of a Process
clk y
w
priority: PROCESS (clk) a priority
z
BEGIN b
c
IF w(3) = '1' THEN
y <= "11" ; • All signals which appear on the
ELSIF w(2) = '1' THEN left of signal assignment
y <= "10" ; statement (<=) are outputs e.g.
ELSIF w(1) = c THEN y, z
y <= a and b; • All signals which appear on the
ELSE right of signal assignment
z <= "00" ; statement (<=) or in logic
END IF ; expressions are inputs e.g. w, a,
END PROCESS ; b, c
• All signals which appear in the
sensitivity list are inputs e.g. clk
• Note that not all inputs need to
be included in the sensitivity list
41
 Registers

ECE 448 – FPGA and ASIC Design with VHDL 42

D latch
Graphical symbol Truth table

D Q
Clock D Q(t+1)
0 – Q(t)
Clock 1 0 0
1 1 1

Timing diagram
t1 t2 t3 t4

Clock
D
Q
Time

43
D flip-flop
Graphical symbol Truth table
Clk D Q(t+1)
D Q
 0 0
Clock  1 1
0 – Q(t)
1 – Q(t)
Timing diagram
t1 t2 t3 t4

Clock
D
Q
Time

44
D latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
D Q
ENTITY latch IS
PORT ( D, Clock : IN STD_LOGIC ; Clock
Q : OUT STD_LOGIC) ;
END latch ;

ARCHITECTURE behavioral OF latch IS

BEGIN
PROCESS ( D, Clock )
BEGIN
IF Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral;

45
D flip-flop
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
D Q
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Clock
Q : OUT STD_LOGIC) ;
END flipflop ;

ARCHITECTURE behavioral OF flipflop IS

BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral ;

46
D flip-flop
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
D Q
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Clock
Q : OUT STD_LOGIC) ;
END flipflop ;

ARCHITECTURE behavioral2 OF flipflop IS

BEGIN
PROCESS ( Clock )
BEGIN
IF rising_edge(Clock) THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral2;

47
 D flip-flop with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY flipflop_ar IS D Q
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ; Clock
END flipflop_ar ; Resetn

ARCHITECTURE behavioral OF flipflop_ar IS

BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= '0' ;
ELSIF rising_edge(Clock) THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral ;
48
 D flip-flop with synchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop_sr IS
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
D Q
Q : OUT STD_LOGIC) ;
END flipflop_sr ;
Clock
ARCHITECTURE behavioral OF flipflop_sr IS Resetn
BEGIN
PROCESS(Clock)
BEGIN
IF rising_edge(Clock) THEN
IF Resetn = '0' THEN
Q <= '0' ;
ELSE
Q <= D ;
END IF ;
END IF;
END PROCESS ;
END behavioral ;

49
Asychronous vs. Synchronous

• In the IF loop, asynchronous items are

• Before the rising_edge(Clock) statement
• In the IF loop, synchronous items are
• After the rising_edge(Clock) statement

50
8-bit register with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY reg8 IS
PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
END reg8 ;

ARCHITECTURE behavioral OF reg8 IS

BEGIN
PROCESS ( Resetn, Clock ) 8 Resetn 8
BEGIN D Q
IF Resetn = '0' THEN
Q <= "00000000" ;
ELSIF rising_edge(Clock) THEN Clock
Q <= D ;
reg8
END IF ;
END PROCESS ;
END behavioral ;`
51
Use of OTHERS

OTHERS stand for any index value that has

not been previously mentioned.

Q <= “00000001” can be written as Q <= (0 => ‘1’, OTHERS => ‘0’)

Q <= “10000001” can be written as Q <= (7 => ‘1’, 0 => ‘1’, OTHERS => ‘0’)
or Q <= (7 | 0 => ‘1’, OTHERS => ‘0’)

Q <= “00011110” can be written as Q <= (4 downto 1=> ‘1’, OTHERS => ‘0’)

52
 Counters

ECE 448 – FPGA and ASIC Design with VHDL 53

2-bit up-counter with synchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY upcount IS
PORT ( Clear, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;
END upcount ;

ARCHITECTURE behavioral OF upcount IS

SIGNAL Count : std_logic_vector(1 DOWNTO 0);
BEGIN 2
upcount: PROCESS ( Clock ) Clear
Q
BEGIN
IF rising_edge(Clock) THEN
upcount
IF Clear = '1' THEN
Count <= "00" ;
ELSE Clock
Count <= Count + 1 ;
END IF ;
END IF;
END PROCESS;
Q <= Count;
END behavioral;

54
4-bit up-counter with asynchronous reset (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;

ENTITY upcount_ar IS
PORT ( Clock, Resetn, Enable : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
END upcount_ar ;

Enable 4
Q

Clock
upcount
Resetn

55
4-bit up-counter with asynchronous reset (2)
ARCHITECTURE behavioral OF upcount _ar IS
SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = '0' THEN
Count <= "0000" ;
ELSIF rising_edge(Clock) THEN
IF Enable = '1' THEN
Count <= Count + 1 ;
END IF ; Enable 4
END IF ; Q
END PROCESS ;
Q <= Count ; Clock
END behavioral ; upcount
Resetn

56
 Shift Registers

ECE 448 – FPGA and ASIC Design with VHDL 57

Shift register

Q(3) Q(2) Q(1) Q(0)

Sin
D Q D Q D Q D Q

Clock

Enable

58
 Shift Register With Parallel Load
Load

D(3)
D(2) D(1) D(0)
Sin

D Q D Q D Q D Q

Clock

Enable

Q(3) Q(2) Q(1) Q(0)

59
4-bit shift register with parallel load (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY shift4 IS
PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Enable : IN STD_LOGIC ;
Load : IN STD_LOGIC ;
Sin : IN STD_LOGIC ;
Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END shift4 ;

4 Enable 4
D Q
Load
Sin
shift4
Clock

60
4-bit shift register with parallel load (2)
ARCHITECTURE behavioral OF shift4 IS
SIGNAL Qt : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN 4 Enable 4
PROCESS (Clock) D Q
BEGIN Load
IF rising_edge(Clock) THEN
Sin
IF Enable = ‘1’ THEN shift4
IF Load = '1' THEN Clock
Qt <= D ;
ELSE
Qt <= Sin & Qt(3 downto 1);
END IF;
END IF ;
END PROCESS ;
Q <= Qt;
END behavioral ;

61
 Circuit built of medium scale components

s(0)

r(0) 0 p(0) En

r(1) 1
w0 q(1)
w y Enable
p(1) y1 1 3 z(3)
r(2) w1 q(0) t(3)
p(2) y0 w y
r(3) w2 0 2 z(2) t(2)
ena D Q
z y
w3 1 z(1) t(1)
r(4) 0 p(3)
priority
y
En 0 z(0) t(0)
dec2to4 regne
r(5) 1
Clk Clock

s(1)

62
Structural description – example (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY priority_resolver IS
PORT (r : IN STD_LOGIC_VECTOR(5 DOWNTO 0) ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
clk : IN STD_LOGIC;
en : IN STD_LOGIC;
t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END priority_resolver;

ARCHITECTURE structural OF priority_resolver IS

SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ;

SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;
SIGNAL z : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
SIGNAL ena : STD_LOGIC ;

63
 Structural description – example (2)

BEGIN

u1: work.mux2to1(dataflow)
PORT MAP (w0 => r(0) ,
w1 => r(1),
s => s(0),
f => p(0));
p(1) <= r(2);
p(2) <= r(3);

u2: work.mux2to1(dataflow)
PORT MAP (w0 => r(4) ,
w1 => r(5),
s => s(1),
f => p(3));

u3: work.priority(dataflow)
PORT MAP (w => p,
y => q,
z => ena);

64
 Structural description – example (3)

u4: work.dec2to4 (dataflow)

PORT MAP (w => q,
En => ena,
y => z);

u5: work.regne(behavioral)
PORT MAP (D => z ,
Enable => En ,
Clock => Clk,
Q => t );
END structural;

65
FPGA Board
• Inputs: Switches and Push Buttons
• Outputs: SSDs and LEDs

66
Seven Segment Display (SSD)
• Common Anode vs. Common Cathode
• Reduce number of pins
• Common anode is active low

• Digit Mutliplexing:
• Each SSD has separate common anode pin
• Multiple SSDs share the same Cathode pins
• For example, the a cathode of the four SSDs
are connected together to form a single
output called CA (Cathode a)
• 12 pins instead of 36
• Select each SSD sequentially (setting
AN0=0, then AN1=0, and so on)
• Do this “fast enough” to create the illusion
that all SSDs are lit constantly
67
SSD Multiplexing

• We use a 2-bit counter (00, 01, 10, 11) and a 2x4 decoder
to generate the 4 SSD enables (00 => AN0 active, 01 =>
AN1 active, etc.).
• We use the same counter bits as select lines to a 4x1
mux to “steer” the proper Ca-Cg to the enabled SSD.
68
Clock Division (1)
• The counter value should change every 1ms to 16ms (i.e. 60Hz to
1000Hz)
• Clock frequency from board (MCLK) is 100 MHz
• Given the following architecture:
signal DIVCLK : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000";

DIV_PROCESS: PROCESS(MCLK)
BEGIN
IF rising_edge (MCLK) THEN
DIVCLK <= DIVCLK + 1;
END IF;
END PROCESS;

• DIVCLK[0] is 50 MHz, DIVCLK[1] is 25 MHz, and so on

• All outputs have 50% duty cycle
69
 Clock Division: Arbitrary Frequency
• Target Frequency is 100 Hz → Cycle Time = 0.01 second
• Original Frequency is 100 MHz → Cycle Time = 0.01 µsecond
• # of original cycles = 0.01 second / 0.01 µsecond = 1000000 cycles

CLK_PROCESS: PROCESS(MCLK)
BEGIN
IF RISING_EDGE(MCLK) THEN
IF(COUNTER < "11110100001000111111") THEN
COUNTER <= COUNTER + 1;
ELSE
COUNTER <= "00000000000000000000";
END IF;
END IF;
END PROCESS;
HUNDREDHZCLOCK <= '0' WHEN COUNTER < "01111010000100100000" ELSE '1';

70
Detour Sign Example
• Design a system that receives 2-bit input from switches
and displays the following words on the SSDs:
➢ Input = “00” → SSDs <= StOP
➢ Input = “01” → SSDs <= LeFt
➢ Input = “10” → SSDs <= rIte
➢ Input = “11” → Nothing is displayed (SSDs are OFF)

• Multiple SSDs constantly:

• Four characters in each case → 2-bit counter is needed
• Clock divider is needed (100 Hz Frequency)

71
Block Diagram of Detour Sign

72
 Detour Sign Design Components
• One possible implementation:
• Clock divider Entity
• 2-bit Counter Entity
• 4-to-1 MUX Entity
• Choose the 1st character (S, L, r, nothing) according to input switches
• Choose the 2nd character (t, e, I, nothing) according to input switches
• Choose the 3rd character (O, F, t, nothing) according to input switches
• Choose the 4th character (P, t, e, nothing) according to input switches
• SSD Driver to determine which character and enable the
correct SSD

73
74
Clock Divider VHDL Code (1)
entity HUDREDHZ_CLOCK_GENERATOR_NEW is
Port ( MCLK : in STD_LOGIC;
HUNDREDHZCLOCK : out STD_LOGIC);
end HUDREDHZ_CLOCK_GENERATOR_NEW;

architecture Behavioral of HUDREDHZ_CLOCK_GENERATOR_NEW is

SIGNAL COUNTER : STD_LOGIC_VECTOR(19 DOWNTO 0) :=

"00000000000000000000";

begin
CLK_PROCESS: PROCESS(MCLK)

BEGIN
75
Clock Divider VHDL Code (2)
IF(MCLK'EVENT AND MCLK = '1') THEN
IF(COUNTER < "11110100001000111111") THEN

COUNTER <= COUNTER + 1;

ELSE
COUNTER <= "00000000000000000000";
END IF;
END IF;
END PROCESS;

HUNDREDHZCLOCK <= '0' WHEN COUNTER <

"01111010000100100000" ELSE '1';

end Behavioral;
76
Two-bit Counter VHDL Code (1)
ENTITY TWO_BIT_COUNTER IS
PORT ( SW_IN : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
CLK : IN STD_LOGIC;
SW_OUT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0));
END TWO_BIT_COUNTER;

ARCHITECTURE BEHAVIORAL OF TWO_BIT_COUNTER IS

SIGNAL COUNTER : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";

SIGNAL SW_REG : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";

BEGIN

77
Two-bit Counter VHDL Code (2)
PROCESS_COUNT : PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
COUNTER <= COUNTER + 1;
IF COUNTER = "11" THEN
SW_REG <= SW_IN;
END IF;
END IF;
END PROCESS;

SW_OUT <= SW_REG;

Q <= COUNTER;

END BEHAVIORAL;
78
Four-to-One MUX VHDL Code (1)
ENTITY FOUR_TO_ONE_MUX IS
PORT ( I0 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
I1 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
I2 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
I3 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END FOUR_TO_ONE_MUX;

ARCHITECTURE BEHAVIORAL OF FOUR_TO_ONE_MUX IS

BEGIN

79
Four-to-One MUX VHDL Code (2)
WITH SEL SELECT Y <=
I0 WHEN "00",
I1 WHEN "01",
I2 WHEN "10",
I3 WHEN OTHERS;

END BEHAVIORAL;

80
SSD Driver VHDL Code (1)
ENTITY SSD_DRIVER IS
PORT ( A : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
C : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
D : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
COUNTER : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
SSD_DATA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SSD_EN : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END SSD_DRIVER;

ARCHITECTURE BEHAVIORAL OF SSD_DRIVER IS

BEGIN

81
SSD Driver VHDL Code (2)
WITH COUNTER SELECT SSD_DATA <=
D WHEN "00",
C WHEN "01",
B WHEN "10",
A WHEN OTHERS;

WITH COUNTER SELECT SSD_EN <=

"11110111" WHEN "00",
"11111011" WHEN "01",
"11111101" WHEN "10",
"11111110" WHEN "11",
"11111111" WHEN OTHERS;

END BEHAVIORAL;
82
Top Design VHDL Code (1)
ENTITY DETOUR_LAB IS
PORT ( SW_IN : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
MCLK : IN STD_LOGIC;
SSD_DATA : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
SSD_EN : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END DETOUR_LAB;

ARCHITECTURE BEHAVIORAL OF DETOUR_LAB IS

SIGNAL WIRE_HUNDREDHZ_CLOCK : STD_LOGIC;

SIGNAL WIRE_SEVSEG_DATA : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_SW_OUT : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL WIRE_Q : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL WIRE_CHAR_1 : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL WIRE_CHAR_2 : STD_LOGIC_VECTOR(6 DOWNTO 0);
83
Top Design VHDL Code (2)
SIGNAL WIRE_CHAR_3 : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL WIRE_CHAR_4 : STD_LOGIC_VECTOR(6 DOWNTO 0);

BEGIN

CLOCK_GENERATOR : ENTITY
WORK.HUDREDHZ_CLOCK_GENERATOR_NEW PORT MAP(
MCLK => MCLK,
HUNDREDHZCLOCK => WIRE_HUNDREDHZ_CLOCK);

COUNTER_2 : ENTITY WORK.TWO_BIT_COUNTER PORT MAP(

SW_IN => SW_IN,
CLK => WIRE_HUNDREDHZ_CLOCK,
SW_OUT => WIRE_SW_OUT,
Q => WIRE_Q);
84
Top Design VHDL Code (3)
MUX_CHAR_1 : ENTITY WORK.FOUR_TO_ONE_MUX PORT MAP(
I0 => "0010010", I1 => "1000111", I2 => "0101111",
I3 => "1111111", SEL => WIRE_SW_OUT, Y => WIRE_CHAR_1);
MUX_CHAR_2 : ENTITY WORK.FOUR_TO_ONE_MUX PORT MAP(
I0 => "0000111", I1 => "0000100", I2 => "1001111",
I3 => "1111111", SEL => WIRE_SW_OUT, Y => WIRE_CHAR_2);

MUX_CHAR_3 : ENTITY WORK.FOUR_TO_ONE_MUX PORT MAP(

I0 => "1000000", I1 => "0001110", I2 => "0000111",
I3 => "1111111", SEL => WIRE_SW_OUT, Y => WIRE_CHAR_3);

MUX_CHAR_4 : ENTITY WORK.FOUR_TO_ONE_MUX PORT MAP(

I0 => "0001100", I1 => "0000111", I2 => "0000100",
I3 => "1111111", SEL => WIRE_SW_OUT, Y => WIRE_CHAR_4);

85
Top Design VHDL Code (3)
DRIVER : ENTITY WORK.SSD_DRIVER PORT MAP(
A => WIRE_CHAR_4,
B => WIRE_CHAR_3,
C => WIRE_CHAR_2,
D => WIRE_CHAR_1,
COUNTER => WIRE_Q,
SSD_DATA => SSD_DATA,
SSD_EN => SSD_EN);

END BEHAVIORAL;

86
Test Bench VHDL Code (1)
ENTITY DETOUR_LAB_TB IS

END DETOUR_LAB_TB;

ARCHITECTURE BEHAVIORAL OF DETOUR_LAB_TB IS

SIGNAL SW_IN_TB : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";

SIGNAL MCLK_TB : STD_LOGIC := '0';
SIGNAL SSD_DATA_TB : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL SSD_EN_TB : STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

DETOUT_LAB_U1 : ENTITY WORK.DETOUR_LAB(BEHAVIORAL)

PORT MAP( SW_IN => SW_IN_TB, MCLK => MCLK_TB,
SSD_DATA => SSD_DATA_TB, SSD_EN =>
SSD_EN_TB);
87
Test Bench VHDL Code (2)
CLK_PROCESS : PROCESS
BEGIN
WAIT FOR 10ns;
MCLK_TB <= NOT(MCLK_TB);
END PROCESS CLK_PROCESS;

INPUT_PROCESS : PROCESS
BEGIN
WAIT FOR 0.1sec;
SW_IN_TB <= "01";
WAIT FOR 0.1sec;
SW_IN_TB <= "10";
WAIT FOR 0.1sec;
SW_IN_TB <= "11";
WAIT FOR 0.1sec;
SW_IN_TB <= "00";
END PROCESS INPUT_PROCESS;
END BEHAVIORAL; 88
Push Buttons as Inputs

• Debouncer Circuit:

• Counter time ≈ 15 ms

89
?

90