ELEC 204 - Lab - Week - 2 - Fall - 2022 PDF
ELEC 204 - Lab - Week - 2 - Fall - 2022 PDF
Combinational Logic
Current Topic
Combinational
Logic
Combinational …
Logic
Registers
2
Data-Flow VHDL
Concurrent Statements
• concurrent signal assignment
()
3
Data-flow VHDL: Example
x
y s
cin
cout
4
Data-flow VHDL: Example (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
PORT ( x : IN STD_LOGIC ;
y : IN STD_LOGIC ;
cin : IN STD_LOGIC ;
s : OUT STD_LOGIC ;
cout : OUT STD_LOGIC ) ;
END fulladd ;
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Data-flow VHDL: Example (2)
• Logic operators
and or nand nor xor not xnor
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No Implied Precedence
Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d
Correct
y <= (a and b) or (c and d) ;
8
Signal assignment statement with a closed
feedback loop
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Data-Flow VHDL
Concurrent Statements
• concurrent signal assignment
()
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Conditional concurrent signal assignment
When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
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Most often implied structure
When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
0
Value N
.… … 0
1
Value N-1 0
1 Target Signal
1
Value 2
Value 1
Condition N-1
Condition 2
Condition 1
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Example
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Example
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Signed and Unsigned Types
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Signed, Unsigned, STD_LOGIC_VECTOR
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Operators
• Relational operators
• Can be used with std_logic_vector, signed,
and unsigned
= /= < <= > >=
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Priority of logic and relational operators
compare a = bc
Incorrect
… when a = b and c else …
equivalent to
… when (a = b) and c else …
Correct
… when a = (b and c) else …
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VHDL operators
19
Data-Flow VHDL
Concurrent Statements
• concurrent signal assignment
()
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Selected concurrent signal assignment
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;
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Most Often Implied Structure
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;
expression1 choices_1
expression2 choices_2
target_signal
expressionN choices_N
choice expression
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Allowed formats of choices_k
WHEN value
WHEN OTHERS
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Allowed formats of choice_k - example
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Syntax
• select_expression
• Discrete type or 1-D array
• With finite possible values
• choice_i
• A value of the data type
• Choices must be
• mutually exclusive
• all inclusive
• others can be used as last choice_i
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E.g., 4-to-1 mux
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entity mux4 is
PORT(
s: IN std_logic_vector (1 downto 0);
a: IN std_logic;
b: IN std_logic;
c: IN std_logic;
d: IN std_logic;
x: OUT std_logic
);
end mux4;
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Question
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E.g., 2-to-22 binary decoder
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E.g., 4-to-2 priority encoder
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Question
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E.g., simple ALU
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Simple ALU VHDL Entity Declaration
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.numeric_std.all;
ENTITY simple_alu IS
PORT ( ctrl : IN STD_LOGIC_VECTOR (2 downto 0) ;
src0 : IN STD_LOGIC_VECTOR (7 downto 0);
src1 : IN STD_LOGIC_VECTOR (7 downto 0);
result: OUT STD_LOGIC_VECTOR (7 downto 0)) ;
END simple_alu ;
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Comparison
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Comparison
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Behavioral Modeling of
Sequential-Circuit Building
Blocks
38
Anatomy of a Process
OPTIONAL
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PROCESS with a SENSITIVITY LIST
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Component Equivalent of a Process
clk y
w
priority: PROCESS (clk) a priority
z
BEGIN b
c
IF w(3) = '1' THEN
y <= "11" ; • All signals which appear on the
ELSIF w(2) = '1' THEN left of signal assignment
y <= "10" ; statement (<=) are outputs e.g.
ELSIF w(1) = c THEN y, z
y <= a and b; • All signals which appear on the
ELSE right of signal assignment
z <= "00" ; statement (<=) or in logic
END IF ; expressions are inputs e.g. w, a,
END PROCESS ; b, c
• All signals which appear in the
sensitivity list are inputs e.g. clk
• Note that not all inputs need to
be included in the sensitivity list
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Registers
D Q
Clock D Q(t+1)
0 – Q(t)
Clock 1 0 0
1 1 1
Timing diagram
t1 t2 t3 t4
Clock
D
Q
Time
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D flip-flop
Graphical symbol Truth table
Clk D Q(t+1)
D Q
0 0
Clock 1 1
0 – Q(t)
1 – Q(t)
Timing diagram
t1 t2 t3 t4
Clock
D
Q
Time
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D latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
D Q
ENTITY latch IS
PORT ( D, Clock : IN STD_LOGIC ; Clock
Q : OUT STD_LOGIC) ;
END latch ;
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D flip-flop
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
D Q
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Clock
Q : OUT STD_LOGIC) ;
END flipflop ;
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D flip-flop
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
D Q
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Clock
Q : OUT STD_LOGIC) ;
END flipflop ;
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D flip-flop with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop_ar IS D Q
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ; Clock
END flipflop_ar ; Resetn
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Asychronous vs. Synchronous
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8-bit register with asynchronous reset
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY reg8 IS
PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
END reg8 ;
Q <= “00000001” can be written as Q <= (0 => ‘1’, OTHERS => ‘0’)
Q <= “10000001” can be written as Q <= (7 => ‘1’, 0 => ‘1’, OTHERS => ‘0’)
or Q <= (7 | 0 => ‘1’, OTHERS => ‘0’)
Q <= “00011110” can be written as Q <= (4 downto 1=> ‘1’, OTHERS => ‘0’)
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Counters
54
4-bit up-counter with asynchronous reset (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY upcount_ar IS
PORT ( Clock, Resetn, Enable : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
END upcount_ar ;
Enable 4
Q
Clock
upcount
Resetn
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4-bit up-counter with asynchronous reset (2)
ARCHITECTURE behavioral OF upcount _ar IS
SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn = '0' THEN
Count <= "0000" ;
ELSIF rising_edge(Clock) THEN
IF Enable = '1' THEN
Count <= Count + 1 ;
END IF ; Enable 4
END IF ; Q
END PROCESS ;
Q <= Count ; Clock
END behavioral ; upcount
Resetn
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Shift Registers
Sin
D Q D Q D Q D Q
Clock
Enable
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Shift Register With Parallel Load
Load
D(3)
D(2) D(1) D(0)
Sin
D Q D Q D Q D Q
Clock
Enable
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4-bit shift register with parallel load (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shift4 IS
PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Enable : IN STD_LOGIC ;
Load : IN STD_LOGIC ;
Sin : IN STD_LOGIC ;
Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END shift4 ;
4 Enable 4
D Q
Load
Sin
shift4
Clock
60
4-bit shift register with parallel load (2)
ARCHITECTURE behavioral OF shift4 IS
SIGNAL Qt : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN 4 Enable 4
PROCESS (Clock) D Q
BEGIN Load
IF rising_edge(Clock) THEN
Sin
IF Enable = ‘1’ THEN shift4
IF Load = '1' THEN Clock
Qt <= D ;
ELSE
Qt <= Sin & Qt(3 downto 1);
END IF;
END IF ;
END PROCESS ;
Q <= Qt;
END behavioral ;
61
Circuit built of medium scale components
s(0)
r(0) 0 p(0) En
r(1) 1
w0 q(1)
w y Enable
p(1) y1 1 3 z(3)
r(2) w1 q(0) t(3)
p(2) y0 w y
r(3) w2 0 2 z(2) t(2)
ena D Q
z y
w3 1 z(1) t(1)
r(4) 0 p(3)
priority
y
En 0 z(0) t(0)
dec2to4 regne
r(5) 1
Clk Clock
s(1)
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Structural description – example (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority_resolver IS
PORT (r : IN STD_LOGIC_VECTOR(5 DOWNTO 0) ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
clk : IN STD_LOGIC;
en : IN STD_LOGIC;
t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END priority_resolver;
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Structural description – example (2)
BEGIN
u1: work.mux2to1(dataflow)
PORT MAP (w0 => r(0) ,
w1 => r(1),
s => s(0),
f => p(0));
p(1) <= r(2);
p(2) <= r(3);
u2: work.mux2to1(dataflow)
PORT MAP (w0 => r(4) ,
w1 => r(5),
s => s(1),
f => p(3));
u3: work.priority(dataflow)
PORT MAP (w => p,
y => q,
z => ena);
64
Structural description – example (3)
u5: work.regne(behavioral)
PORT MAP (D => z ,
Enable => En ,
Clock => Clk,
Q => t );
END structural;
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FPGA Board
• Inputs: Switches and Push Buttons
• Outputs: SSDs and LEDs
66
Seven Segment Display (SSD)
• Common Anode vs. Common Cathode
• Reduce number of pins
• Common anode is active low
• Digit Mutliplexing:
• Each SSD has separate common anode pin
• Multiple SSDs share the same Cathode pins
• For example, the a cathode of the four SSDs
are connected together to form a single
output called CA (Cathode a)
• 12 pins instead of 36
• Select each SSD sequentially (setting
AN0=0, then AN1=0, and so on)
• Do this “fast enough” to create the illusion
that all SSDs are lit constantly
67
SSD Multiplexing
• We use a 2-bit counter (00, 01, 10, 11) and a 2x4 decoder
to generate the 4 SSD enables (00 => AN0 active, 01 =>
AN1 active, etc.).
• We use the same counter bits as select lines to a 4x1
mux to “steer” the proper Ca-Cg to the enabled SSD.
68
Clock Division (1)
• The counter value should change every 1ms to 16ms (i.e. 60Hz to
1000Hz)
• Clock frequency from board (MCLK) is 100 MHz
• Given the following architecture:
signal DIVCLK : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000";
DIV_PROCESS: PROCESS(MCLK)
BEGIN
IF rising_edge (MCLK) THEN
DIVCLK <= DIVCLK + 1;
END IF;
END PROCESS;
CLK_PROCESS: PROCESS(MCLK)
BEGIN
IF RISING_EDGE(MCLK) THEN
IF(COUNTER < "11110100001000111111") THEN
COUNTER <= COUNTER + 1;
ELSE
COUNTER <= "00000000000000000000";
END IF;
END IF;
END PROCESS;
HUNDREDHZCLOCK <= '0' WHEN COUNTER < "01111010000100100000" ELSE '1';
70
Detour Sign Example
• Design a system that receives 2-bit input from switches
and displays the following words on the SSDs:
➢ Input = “00” → SSDs <= StOP
➢ Input = “01” → SSDs <= LeFt
➢ Input = “10” → SSDs <= rIte
➢ Input = “11” → Nothing is displayed (SSDs are OFF)
71
Block Diagram of Detour Sign
72
Detour Sign Design Components
• One possible implementation:
• Clock divider Entity
• 2-bit Counter Entity
• 4-to-1 MUX Entity
• Choose the 1st character (S, L, r, nothing) according to input switches
• Choose the 2nd character (t, e, I, nothing) according to input switches
• Choose the 3rd character (O, F, t, nothing) according to input switches
• Choose the 4th character (P, t, e, nothing) according to input switches
• SSD Driver to determine which character and enable the
correct SSD
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74
Clock Divider VHDL Code (1)
entity HUDREDHZ_CLOCK_GENERATOR_NEW is
Port ( MCLK : in STD_LOGIC;
HUNDREDHZCLOCK : out STD_LOGIC);
end HUDREDHZ_CLOCK_GENERATOR_NEW;
begin
CLK_PROCESS: PROCESS(MCLK)
BEGIN
75
Clock Divider VHDL Code (2)
IF(MCLK'EVENT AND MCLK = '1') THEN
IF(COUNTER < "11110100001000111111") THEN
end Behavioral;
76
Two-bit Counter VHDL Code (1)
ENTITY TWO_BIT_COUNTER IS
PORT ( SW_IN : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
CLK : IN STD_LOGIC;
SW_OUT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0));
END TWO_BIT_COUNTER;
BEGIN
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Two-bit Counter VHDL Code (2)
PROCESS_COUNT : PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
COUNTER <= COUNTER + 1;
IF COUNTER = "11" THEN
SW_REG <= SW_IN;
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;
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Four-to-One MUX VHDL Code (1)
ENTITY FOUR_TO_ONE_MUX IS
PORT ( I0 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
I1 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
I2 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
I3 : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
END FOUR_TO_ONE_MUX;
BEGIN
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Four-to-One MUX VHDL Code (2)
WITH SEL SELECT Y <=
I0 WHEN "00",
I1 WHEN "01",
I2 WHEN "10",
I3 WHEN OTHERS;
END BEHAVIORAL;
80
SSD Driver VHDL Code (1)
ENTITY SSD_DRIVER IS
PORT ( A : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
C : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
D : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
COUNTER : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
SSD_DATA : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SSD_EN : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END SSD_DRIVER;
BEGIN
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SSD Driver VHDL Code (2)
WITH COUNTER SELECT SSD_DATA <=
D WHEN "00",
C WHEN "01",
B WHEN "10",
A WHEN OTHERS;
END BEHAVIORAL;
82
Top Design VHDL Code (1)
ENTITY DETOUR_LAB IS
PORT ( SW_IN : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
MCLK : IN STD_LOGIC;
SSD_DATA : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
SSD_EN : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END DETOUR_LAB;
BEGIN
CLOCK_GENERATOR : ENTITY
WORK.HUDREDHZ_CLOCK_GENERATOR_NEW PORT MAP(
MCLK => MCLK,
HUNDREDHZCLOCK => WIRE_HUNDREDHZ_CLOCK);
85
Top Design VHDL Code (3)
DRIVER : ENTITY WORK.SSD_DRIVER PORT MAP(
A => WIRE_CHAR_4,
B => WIRE_CHAR_3,
C => WIRE_CHAR_2,
D => WIRE_CHAR_1,
COUNTER => WIRE_Q,
SSD_DATA => SSD_DATA,
SSD_EN => SSD_EN);
END BEHAVIORAL;
86
Test Bench VHDL Code (1)
ENTITY DETOUR_LAB_TB IS
END DETOUR_LAB_TB;
BEGIN
INPUT_PROCESS : PROCESS
BEGIN
WAIT FOR 0.1sec;
SW_IN_TB <= "01";
WAIT FOR 0.1sec;
SW_IN_TB <= "10";
WAIT FOR 0.1sec;
SW_IN_TB <= "11";
WAIT FOR 0.1sec;
SW_IN_TB <= "00";
END PROCESS INPUT_PROCESS;
END BEHAVIORAL; 88
Push Buttons as Inputs
• Debouncer Circuit:
• Counter time ≈ 15 ms
89
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