PLD Architectures and Applications Design Flow. CPLD Architecture, Features, Specifications, Applications. FPGA Architecture, Features, Specifications, optatons, Clock management techniques. The Simulation and Synthesis Tools, FPGA synthesis and implementation pplication Comparison of CPLD & FPGA, Introduction \What is need of PLD? Explain technologies involved in detail . Enist al the types of memory used in PLO’ SUTEIINE pos Logic devices can be classified into two broad categories; fixed and programmable, As the name implies in a fixed logic device the circuit is permanent and performs only the specific functions that is defined during its manufacture. On the other hand, programmable logic devices can be programmed according to users’ requirements. The programmable logic devices that are available in the market nowadays allow it to be reprogrammed several times. Accommodating complex circuits in a very small, area in less time become easier after the invention of integrated circuits. A number of discrete fixed logic ICs. would occupy huge space of the PCBs while designing a system, Instead of utilizing several Ics separately and then interconnecting them, PLDs could provide several functions realized on a single tiny IC discrete PLDs are the ICs that allow a user to program any function on it after it is manufactured so that it behaves d way. There are several programmable manufacturing companies like Altera, Xilinx, Actel, Quick logic ete. 3.1.1 Need of Programmable Logic Devices For fixed logic devices, if the IC after it is manufactured does not work properly or if the requirement changes, the design must be developed again from the scratch, whereas, programmable logic devices (PLDs) make use of software tool that enables quick design and verification. Also, designers can change the design as often as they want until the design meets its required specification. = Itis easy to modify the design whenever required as Unvy are software configured. — There are no Non-Recurring Engineering (NRE) cost involved in developing design using PLD's. = It reduces time to market. It can be designed and verified quickly while the same process requires several weeks with discrete ICs. 3.1.2 PLD Classification APLD is a device that are user programmable. That fs, such ICs are manufactured without any fixed function and they must be programmed while using them in a circuit, PLDs are programmed using specialized software tools. PLDs can be classified into following the groups. — _ SPLD (Simple Programmable Logic Device) = CPLD (Complex Programmable Logic Device) = FPGA (Field Programmable Gate Array) PLD's ‘SPL cPLD FPGA PROM PAL PLA Fig, 3.1.1 : Classification of PLD's‘specications ‘WB Visi Design & Technology (SPPU) FPGA / CPLD Design Flow ‘A typical programmable logic device involves the following design steps (shown in Fig. 3.1.1). First step is to enter the design specification which can be done either using schematic editor or through hardware descriptive language such as VHDL or through finite state machine (FSM). Once the design specification is entered in the PC, it is synthesized there by converting the system description from higher level description to lower level circuit. After synthesis, itis simulated to verify its functionality. Ifthe circuit does not meet the desired specification, changes are made in the program/or circuit (in schematic entry) and are synthesized and verified again. ‘This is repeated until the circuit meets the desired Specification or is functionally correct (with timing specification). Finally the design implementation is done followed by the programming of FPGA/CPLD, Schematic capture [HOLS (UHL or ven FSM 7 tit does not meet the [Functional simulation Device programing] Fig, 3.2.1 Design Flow When a designer is handed over the specifications of a new product, he can start the design using one of L the following approaches 2. Bottom up ] i 3. Mixed ] Fig. 3.2.2 : Design Approach Top down : In this approach, first the top-level betas designed and then it is partitioned into say a. systems and then sub sub-systems til itis eg to simple components. The Behaviour description ofthe circuit is suitable here. Ithas eg observed that this approach Is suitable for lp designs, typically is involving more than 10000 baste gates. Many FPGA based designs follow i approach. Bottom up : Thi the traditional schematic based approach. k 1s used when a library of known low level components are available. You build medium sub- systems from them and then finally interconnect them to realize the overall, suitable for using components, s standard Mixed : Tso ‘0 the top-down approach tse : tas eb start from top tevel, But here you Be TH UP to the component evel. You can ind suitable medium-level ‘te fesien, A library of ottomeye PAE for this ASIC deggePPPOACH. This ig) When vendor Te available jn, Standard cel cel stop when you can fi entities for realizing medium-level_compones Purpose, using the approach is suitable for supplied cell libraries ay libraries,yr ao a Teomoloa x Programmable Logic , and explain the architecture of 0 oot SSE) on i ne detail Architecture of CPLD. raw and a ee Ae reitecture of CPLD in detail. Explain cells. ) rea 0. BT yo blocks. Inter connect resources, eaten oo pint compat of devices. mo i Soe eE mmable logic devices contain Complex prograr : eral PLD blocks also called as macrocells with general purpose interconnect between them. itecture of CPLD. Fig. 33.1 shows the archi ‘A CPLD typically contains from tens to a few hundred macrocells. A group of eight to 16 rmacrocells in typically grouped together forming a larger function block. Ina device containing many function blocks, all of them are interconnected through programmable switch logic. ‘The macrocells within a function block are further usually interconnected. 33.1. CPLD Architecture Ca Q. Drawandexplain CPLD architecture. a eee Complex programmable logic devices contain several PLD blocks also called as macrocells with Sneral purpose interconnect between them. Fig-33.1 shows the architecture of CPLD. Mostly CPLD's differ in architecture in terms of the ‘umber of product terms per macrocells or in the "umber of connections within the switch matrix, PLD Architectures and Applications oooo0oo0ovood oO BH =o a lee on a mat a a tog | © oo [vee sae] a ao ooooooooo Fig. 3.3.1: CPLD Architecture ‘The macrocells consist of the logic array, the product term selection matrix, flip-flop, and 2 multiplexer. The flip-flop is used to store the output value produced by the OR gate. Macrocells are functional blocks that perform combinatorial or sequential logic Generally, CPLDs are based on CMOS technology and use non-volatile memory cells such as EPROM or EEPROM to define the functionality. 3.3.2 CPLD XC9500 Paseo Q. Draw CPLD XC9500 series architecture and explain SEE in deta The Xilinx XC 9500 is a family of Complex Programmable Logic Devices (CPLDs). Itcontains several PLDs. The internal PLDs in Xilinx are called as function blocks (FBs). ‘There are 36 inputs and 18 macrocells and outputs available in each PLD. Hence it is called as a “36V18". ‘The devices in this family are named according to the number of macrocells it contains. The smallest CPLD has 2 FBs and 36 macrocells while the largest contains 16FBs and 288 macrocells. Each XC9500 macrocell is capable to be individually configured for any combinatorial or registered function. PE TeciinowietgeRF Vist Design & Technology (SPUD "a ayeem programming controler vok vorsts E73} Fig. 3.3.2 : Block Diagram of CPLD XC9500 Fig. 3.3.3 : Macrocell of CPLD Xc9500yaa Features 0 jgh-performance , : pin-topin logic delays on all pins ou 6 to 288 macrocells with 800 density range: 3 106,400 usable gates svin-system programmable sndurance of 10,000 program/erase cycles gnnanced pin-locking architecture Flexible 36V18 Function Block .s drive any or all of 18 macrocells 35 a pesign & TechnolOBy (spPu) v 'Q, Give typleal features and specifications of FPGA. ff CPLD XC9500 PLD Architectures and Applications [ed Following are the parameter specification provided in the datasheet of the CPLD. CPLD contain several logic blocks Macrocells each containing several macrocells. ‘The total number of logic gates in System Gates the device. ‘The number of product terms that Product Terms ‘can be managed by a macrocell per Macrocell ‘The total number of shift registers = 90 product term Registers wethin Function Block ie hedevice al oduct term clocks, output enables, set - a pee ee i. Internal Internal frequency is the speed (in and rset signal , : Frequency | Miz) at which the device can z A —Gatnsive IEEE Std 1149.1 boundary-scan (TAG) a ettons 1 6r 3am support transfers internally _tewrate control on individual outputs savorSv1/0 capability User I/Os ‘The total number of user 1/0 ports _* present 34 Complex Programennele Logic Operating The range of ambient operating Devices (CPLD) Features Temperature _ | temperature The number of external clock that [university Question Q. Explain features of CPLD. can be The device 1. Reprogrammable reprogrammed. Performance : High-performance device jon-volatile configurable memory 3, Memory : 4. Built-in Processor : The device has a hardwired, built-in processor for added control. 5. Insystem Programmability : The device can be programmed while connected to the system. It Is not required to disconnect the device for reprogramming Hot Insertion : The CPLD can be inserted or Temoved into a working system. 6 35 Complex Programmable Logic Devices (CPLD) Specifications University Que: ist ypical specitications of CPLD. External Clocks can be connected to the device The total number of pins in the package Pin Count 3.6 _CPLD Programming Technology Programming Technotogies| 7, Floating gate technologies ‘UV EPROM (Ultra voilet EPROM) EEPAO (Electrical erasable EPROM) Flash memory l 2.1m Systom Programmable ('SP) EEPROM and Nash mamory SinsyslomRe-Programmabie | Flash mamory, UTTAR Fig. 3.6.1 : Programming Technologies SE Techno¥ visio, 1,000,000 gates / chip 200 _|2000 |transistors Gordon Moore, then with Fairchild Corporation and ‘eter cofounder of Intel in 1960, predicted that the ‘umber of transistor that can be implemented per RD en every 1% years because of the ing feature size and growing die size. ae is highlighted by the way in which Sngenge tTansistor are integrated in crults on a iphas grown, 4-2 Number of ransstor perch Digital CMOS Circuits Siloon IC Tochnology ey Bipolar Mos NMOS PMOS CMOS Fig. 4.1.1: Silicon IC technology classification (eto rcranca = 18 you) 1 Moropronssot (tla of erensa = 125 yr) om 0% 7 7% 6 9% 9 200 ve Fig. 4.1.2: Level of integration versus time for memory chips and logic chips It can be observed (Fig. 41.2) that in terms of transistor count, logic chips contain significantly fewer transistors in any given year mainly due to large consumption of chip area for complex interconnects. Memory circuits are highly regular, and thus more cells can be integrated with much less area of interconnects. This has also been one of the main reasons why the rate of increase of chip complexity (transistor count per chip) is consistently higher for memory circuits. To continue growth in this field it will be necessary to Improve the technology both in terms of scaling and processing. Although the large majority of the current ICs are implemented in MOS technology, other technologies come into play when very high performance is concerned. As an example of this is BICMOS technology that combines bipolar and MOS devices onthe same die, pe rechnowledge ¥42 4, Basic MOSFET Structure -1 Enhancement Type MOSFET MOSFET is broadly classified into two types namely enhancement type MOSFET and depletion type MOSFET. Iman enhancement type MOSFET channel has to be induced for the device to conduct, which is achieved by increasing Vgs voltage above the threshold voltage, Since increase in Ves voltage enhances the channel, hence its called enhancement type MOSFET, Another type of MOSFET is depletion type MOSFET in which the channel exists even when it is unbiased, Each enhancement and depletion type MOSFETs are further classified either as an n-channel MOSFET (MOS transistor) or a p-channel MOSFET (pMos transistor), The threshold voltage required for channel formation nMOSFET is mathematically expressed as, - 9 2 % Vr = Oms~ Cox” Tox” 2 OF Vrs always positive for ne (4.2.1) channel MOSFET ie for n Stable mask into these areas Thus, source 5 and drain ar another by are Isolated from one Fegions is the channel length L, and the lateral ©xtent ofthe channel is the channel width, D D: lt el: ate Dad el Circuit symbol for n-channel enhancement ‘type MOSFET Fig. 4.2.2 shows the circuit symbols of an nMOS transistor. First symbol isthe four terminal symbol, while the later shows MOSFET symbol with source and gate shorted giving three terminal symbol of ‘MOS transistor. MOSFET has derived its name from its physieal structure, The name however has become general one and is used also for the FETs that do not use metal for gate electrode. In fact metal is mostly sarod ey nwt dope polycrystalline material saline eon a the microscopic level consists of 7 led crystallites. ¥, silicon crystal:yn & Technology (SPPU) ose se erm polycrystalline arises from viewing the vera! as being made up of randomly distributed ralites. It has the same melting temperature as ‘al silicon. This allows the wafer to be subjected the processing steps that require high heat treatments after the gate has been formed making it auch suitable material than metal, sso, poverystalline silicon can be doped to any teva, For example during fon implantation for formation of source and drain regions poly silicon also gets doped. another name for the MOSFET is the insulated gate fer or IGFET; however this label is not used commonly. tis named so, from its structure where the gate electrode is electrically insulated from the device body (by the oxide layer) 42.1(B) pMOS Transistor — The p-channel MOSFET or pMOS uses n-type semiconductor material as a substrate with p* regions for source and drain regions. The source and drain region are heavily doped regions that are formed by diffusing p type impurities through suitable mass in these area. The device operates in the same manner as n-channel device with holes as the charge carriers that is, wherever there was n- ‘ype silicon in nMOS transistor is now p-type silicon in pMOS transistor and similarly wherever there was p-type si is now n-type is in pMOS transistor. ~ Therefore to from an inversion layer beneath the gate, we need to attract holes to the gate electrode, Thus, Ves voltage must be sufficiently negative. Threshold voltage (Vz) is hence a negative value, Also for current to flow through the channel Vps voltage applied must be negative. Therefore Vs, Vos and Vr are negative for pMOS transistor. Also the Current direction is from source to the drain terminal. Fig. 4.2.3 shows the circuit symbol for the “te enhancement type MOSFET. : ao 423: ab symbol for the p-channel enhancement type MOSFET al, Fig, Digital CMOS Circuits 4.24 shows the structure of PMOS transistor, Gate type substrate Fig. 4.2.4(a): p-MOS transistor structure ‘Saturation a | rogion o Triode region Vos Fig. 4.2.4(b) : Ip versus Vps graph Fig. 4.2.4(b) shows Ip versus Vps curve for a pMOS transistor. 4.2.1(C) Advantages of n-channel MOSFET over p-channel MOSFET - Nowa day's n-channel MOSFETs have become much popular and are used extensively for fabricating MOS circuits and systems than p-channel MOSFET. ‘The p-channel MOSFETs find their use only in Complementary Metal Oxide Semiconductor (CMOS) integrated circuits. - The main advantage of n-channel MOSFET over p-channel MOSFET is due to the fact that charge carries in n-channel devices are the electrons, which have a mobility of about 1300 cm2/Vs. On the other hand, the charge carries in p-channel devices are the holes which have a mobility of about 500 cm2/Vs. = Since the current in a semiconductor, is directly proportional to the mobility, therefore the current in a n-channel MOSFET is more than two to three times that of a p-channel MOSFET for the same dimensions. The ON resistance of the n-channel MOSFET is one third of that for p-channel MOSFET.vl u ‘etal cy LSI Design & Technology (SPPU) : = Dj value o! Ge jeve the same val , ; It means that in order to achi he a NOSTE the p- fan equivalent n- its using n- current and ON resistance, i the area o| requires three times ; : anne! MOSFET. Thus Cee see sm el MOSFETs are much n han ‘serpent! MOSFETs. This result is in hig! packing density. 4.2.2. Depletion Type MOSFET ‘There are two types of depletion type MOSFETs : a) n-channel depletion type MOSFET (®) p-channel depletion type MOSFET Although depletion type MOSFET is to some extent similar in construction and in operational modes to that of enhancement type MOSFET but have one important distinction. - The depletion type MOSFET inherently has a channel. Even when gate terminal is not biased, it has an n-type region connecting the n* source and the drain regions (for n-channel depletion type MOSFET) at the Surface of the semiconductor even when gate terminal is not biased, ~ Thus ifa voltage Vps is applied between drain and Source, a current ID flows for Ves = 0. So, unlike enhancement MOSFET, there is no need to induce a channel in depletion type MOSFET. Fi the circuit symbol for the n-channel depletion type 4.2.2(A) n-Channel Depletion Type MOSFET Construction ; Meonsists of a p-type sitio n substral slleonsemleondure te formed from This substrate acts Fig. 4.2.6 : n-channel depletion type Mostey The transistor has-four terminals Tandy drain, source and the body. Three terminals ate sho the Fig. 4.2.6, AS we have seen the gate and the substrate» isolated from each other due to the presence of sli dioxide between them. Silicon dioxide being 2 insulating material provides no electrical connect between the gate terminal and the channel of th MOSFET. This gives rise to a very high input impedan of the device and the gate current is almost zero, 4.2.2(B) p-channel Depletion Type MOSFET ~The construction of a p-channel depletion type MOSFET is similar to that of n-channel MOSFET but with an n-type substrate and p-type of source and drain regions. Hence the voltage polarities and the Current directions for a P-MOSFET are reversed. ~ _ p-channel depletion type MOSFET contain a channel (even when unbiased) consisting of holes. 1 typa siloon substrate Ys |OSFET Fig, 4.2.7 : p-channel depletion type Mimary of drain current cr equation of enhancement type nMos ve aransistor 4 2 5 Ves~ Ven) Vos Vps /2] ? Bal C Peeves Von}? n> Cutoff Ve 1S Me NosVip Cutoff VesSVip :Vps>Vas-Vip Linear on(42.3) Ves Vip; Vos < Vos ~ Vip Saturation 43 Channel Length Modulation Qa * Blain channe! length modulation, REED aE further increase in the V, channel's shay i ening ecbeoah gM ate ~ Specifically, as Vps is increased, Off point is moved sli towards the source ie, Is reduced, No effect on the i the channel pinch ightly away from the drain the effective channel length Fig, 4.3.1 : nMOS biased with Vos > Vos. sat This phenomenon is known as channel length modulation. Since Ip is inversely proportional to the channel length, channel length (Equation (4.32)) (Saturation) modulation tends to increase Ip with Vps (Fig. 4.3.2), The saturated current can be approximated by using the maximum value of the non- saturated current with an effective channel length. A simple expression for saturated current is given by adding a factor (1+ AVps) to the peak current by writing: Ip = Bes Vn Lt +a Vaal (43.1) Where 2 is called channel length modulation parameter. Putting Vps equal to zero, itis seen that current does not falls to zero, To get value of 2,we put ly =0 in the above equation; Ipsat (1 + Vs) 1-AVa) Yoe Fig, 4.3.2: VI characteristics including channel modulation effect Se rechknowtedyé