What is STA ( Static Timing Analysis) ?

Static Timing Analysis is a technique of analysing timing paths in a digital

logic by adding up delays along a timing path (both gate and
interconnect) and comparing it with constraints (clock period) to check
whether the path meets the constraint.

Static timing analysis is a method for determining if a circuit meets

timing constraints without having to simulate. So, it validates the design
for desired frequency of operation, without checking the functionality of
the design.
 : What are all the items that are checked by
static timing analysis ?
A partial list of things it checks is here :
• Setup Timing
• Hold timing
• Removal and Recovery Timing on resets
• Clock gating checks
• Min max transition times
• Min/max fanout
• Max capacitance
• Max/min timing between two points on a segment of timing path.
• Latch Time Borrowing
• Clock pulse width requirements
 What Is Setup Time?
Setup time is the amount of time before the clock edge that the input
signal needs to stable to guarantee it is properly accepted on the clock
edge.
 What Is Hold Time?
Hold time is the amount of time after the clock edge that the
input should be stable to guarantee it is properly accepted on the clock
edge.
Removal and Recovery Timing on resets ?
Recovery Time is the minimum required time to the next active clock
edge the after the reset (or the signal under analysis) is released

Removal Time is the minimum required time after the clock edge after
which reset can be released.
 Clock gating checks
A clock gating check occurs when a gating signal can control the path of
a clock signal at a logic cell. An example is shown in Figure 1. The pin of
logic cell connected to clock is called clock pin and pin where gating
signal is connected to is gating pin. Logic cell where clock gating occurs
is also referred to as gating cell.
 Min max transition times
The transition time is the time needed for a signal to pass from 10% to
90% or from 20% to 80% of its final state.
Min/max fanout
 How can I reduce my FPGA
power consumption?
One of the more powerful techniques is to maximize the use of hard IP
blocks available on chip, because FPGA vendors design the hard IP to
use only the exact resources required to achieve a given protocol or
architecture. Another technique is to simply suspend all or part of the
FPGA when it's not in use.
 Describe a timing path
Timing path is defined as the path between start point and end
point where start point and end point is defined as follows: Start Point:
All input ports or clock pins of a sequential element are considered as
valid start point. End Point: All output port or D pin of sequential
element is considered as End point.
What is timing critical path?
The critical path is defined as the path between an input and an output
with the maximum delay.
http://www.vlsi-expert.com/2011/03/static-timing-analysis-sta-
basic-timing.html
 Latch Time Borrowing
Time Borrowing is permitting the logic to automatically borrow time
from next cycle, thereby reducing the time available for data to arrive
for the following cycle OR permitting the logic to use slack from the
previous cycle, in the current cycle
Clock pulse width requirements
Minimum pulse width checks are done to ensure that width of the
clock signal is wide enough for the cell's internal operations to
complete. i.e. to get a stable output you need to ensure that the clock
signal at the clock pin of the flop is at least of a certain 'minimum' width
What does the setup/Hold time of a flop depend upon ?
Setup/Hold time of a flip-flop depends upon the Input data slope, Clock
slope and Output load.
Explain signal timing propagation from one flip-flop to
another flip-flop through combinational delay.
 Explain setup failure to a flip-flop
if we reduce frequency, our cycle time increases and eventually FF2_in
will be able to make it in time and there will not be a setup failure. Also
notice that a clock skew is observed at the second flop. The clock to
second flop clk2 is not aligned with clk1 anymore and it arrives earlier,
which exacerbates the setup failure.
 What is design sign off?
Sign off typically implies that the design is final and no further
revisions are possible.
 If hold violation exists in design, is it OK to sign off
design? If not, why?
No you can not sign off the design if you have hold violations. Because
hold violations are functional failures. Setup violations are frequency
dependent. You can reduce frequency and prevent setup failures. Hold
violations stemming from the same clock edge race, are frequency
independent and are functional failures because you can end up
capturing unintended data, thus putting your state machine in an
unknown state.
What are setup and hold checks for clock gating and
why are they needed ?
What determines the max frequency a digital design
will work on. Why hold time is not included in the
calculation for the above ?
Worst max margin will decide the max frequency a design will work on.
As setup failure is frequency dependent. Hold failure is not frequency
dependent hence it is not factored into the frequency calculation.
 One chip which came back after being manufactured
fails setup test and another one fails a hold test. Which
one may still be used how and why ?
Setup failure is frequency dependent. If certain path fails setup
requirement, you can reduce frequency and eventually setup will pass.
This is because when you reduce frequency you provide more time for
the flop/latch input data to meet setup. Hence we call setup failure a
frequency dependent failure. While hold failure is not frequency
dependent. Hold failure is functional failure.
: Are clock domain crossing issues detected by STA tool
?
No clock Domain crossing issues are not detected by Static Timing
Analysis tool. As mentioned earlier, tool simply tries to find out the
worst case setup and hold checks between launch and capture edge.
Designer has to design for clock domain crossings.
 What are these lockup latches?
Lockup latch is simply a transparent latch (D Latch). These lockup latches
are used in scan-based designs, i.e., in between to scan flip flops which
have large probability of hold failure. The lockup latches are used to
avoid large clock skew problems.
 Difference between lockup latches and lockup
registers.
Both lockup latch and lockup register do serve the same purpose, but
they do have some differences. Due to which one is preferred among
the other one. Let see who wins the quiz.
Coming to the area perspective a lockup latch is half the size of a lockup
register. So, lockup latch is area efficient compared to the use of lockup
registers. Also, we can say that lockup latches are power efficient by
considering the same point.
 Advantages of inserting lockup latches
First this by inserting lockup latches we can do timing closure for hold
failure during SCAN-SHIFT mode. That is the case when there is a large,
uncommon path between launch and capture flip flops.
This scenario is AREA efficient and POWER efficient when compared to
lockup registers, which will be discussed in the later section.
 Does location of lockup latch matter ?
The location of lockup latch very much matters. When you introduce
lockup latch in between two flops, you are essentially breaking timing
path into two segments. One path from the original launch flop to the
lockup latch and other timing path from the lockup latch to the original
capture flop.
 What are your options to fix a timing path ?
There are several different possibilities for fixing a timing path.
- Obvious logic optimization
- Better placement
- - More pipelining.
- Move logic to previous pipe stage ?
- Replicate drivers
- Parallelism in RTL
- Use of Macro.
- Synthesized if...elseif...elseif series.
- One Hot instead of Binary coded State Registers
- Physical design techniques.
- Power trade off techniques
 What are multi cycle paths ?
Multicycle paths are data paths between two registers that operate at
a sample rate slower than the FPGA clock rate and therefore take
multiple clock cycles to complete their execution.
 What is a false path?
False Paths are those timing arcs in design where changes in source
registers are not expected to get captured by the destination register
within a particular time interval.
 What is signal integrity ?
Signal Integrity is the ability of an electrical signal to carry information
reliably and resist the effects of high-frequency electromagnetic
interference from nearby signals
 What is crosstalk glitch and how do you fix it ?

1. Break the victim net by inserting an buffer in between .

2. Provide sufficient spacing between the victim and aggressor net to
reduce coupling capacitance.
3. Route the victim / aggressor net in a different metal layer to remove
coupling capacitance.
4. Strengthen the signal on the victim net by using a lower VT or higher
drive strength cell .
5. Weaken the strength of the aggressor net cell . ( Least preferred ) .
 : What are the main clock distribution styles used ?
In digital designs there are two main clock distribution styles that are
used.
1) Clock mesh or Clock grid distribution system.
2) 2) CTS(Clock tree synthesis), or Clock tree distribution system
 What is a clock tree synthesis?
Clock Tree Synthesis (CTS) is the technique of balancing the clock delay
to all clock inputs by inserting buffers/inverters along the clock routes
of an ASIC design. As a result, CTS is used to balance the skew and
reduce insertion latency
 Why is clock gating done ?
As you can see in the figure by clock gating we can mask certain clock
pulses, or in other words we can control the clock toggling activity. Clock
is usually a very high fanout signal which is distributed throughout the
chip. Because it usually drives large number of elements and normally
continuously toggles, it account for major portion of dynamic power
dissipation of the chip. Ability to turn off clock toggling when not
needed is the most effective dynamic power saving mechanism. From
timing perspective, one has to ensure that clock gating doesn’t
introduce glitches or changes the shape of the clock pulse. There are
setup and hold checks to ensure this.
What is metastability and what are its effects ?
In metastable states, the circuit may be unable to settle into a stable '0'
or '1' logic level within the time required for proper circuit operation.
As a result, the circuit can act in unpredictable ways, and may lead to a
system failure, sometimes referred to as a "glitch".
: How do you synchronize between 2 clock domains?
Common methods for synchronizing data between clock domains are:

• Using m-FF based synchronizers.

• Using MUX based synchronizers.
• Using Handshake signals.
• Using FIFOs (First In First Out memories).
• Using Toggle synchronizers
• Using Xilinx specific clock domain crossing (CDC) tools
• Using PLL and DLL
 How is FIFO depth/size determined ?
Size of the FIFO depends on both read and write clock domain
frequencies, their respective clock skew and write and read data rates.
Data rate can vary depending on the two clock domain operation and
requirement and frequency. FIFO has to be able to handle the case
when data rate of writing operation is maximum and for read operation
is minimum.
Design a flip flop using a mux.
How will a flip flop respond if the clock and D input of
a D flipflop are shorted and clock connected to this
shorted input?
One can expect this flip flop to be in metastable state most of the time.
Because with clock and data input tied together, every time clock rises
the data will also rise and will definitely violate the setup time and hold
time for that flip flop. With the continuous violation of setup and hold
time we can expect flip flop to be in metastable state for at least very
large amount of time.
: How do you fix timing path from latch to latch ?
Latch to latch setup time violation is fixed just like flop to flop path setup
time violation, where you either speed up the data from latch to latch
by either optimizing logic count, or speeding up the gate delays and/or
speeding up wire delays
What is the difference between a latch and a flip-flop
Latch is level sensitive device, while flip-flop is edge sensitive. Actually a
D flip-flop is made from two back to back latches, in master-slave
configuration
 What happens to delay if you increase load
capacitance?
Usually device slows down if load capacitance is increased. Device delay
depends on three parameters, 1) the strength of device, which usually is
the width of the device 2) input slope or slew rate and 3) output load
capacitance. Increasing strength or the width increases self load as well.
 Handling timing closure
• Placement: You can use pblock constraints to try to guide placement.
This is hit or miss and is beyond the scope of this book.
• Routing: If you have a very high utilization, routing can become
congested. Trying to redesign some paths to ease timing may help.
• Too much logic in a path: This can be resolved by adding pipelining or
breaking up long paths if possible.
• Lack of DSP pipelining: This falls under the previous bullet of too much
logic. If you are trying to do more than the DSP can handle without
using some of the internal resources, you may need to evaluate adding
pipeline stages
 How to pipeline a design
We've seen that too much logic in a path can cause timing closure
problems.
This can be addressed in a few ways:
• Using aggressive optimizations
• Pipelining logic
• Pipelining DSP elements
Performance Metrics for Circuits
What is speed grade and how do you select FPGA as per requirements
Speed Grade is what that determines how max a clock can run in FPGA.
Companies use different values, while -1, -2 indicates the scale. Higher the grade,
higher the cost of FPGA
What is the maximum possible speed achievable for a given device say
Virtex6 device (some speed grade)
The Fmax is determined by Flop-to-Flop timing using shortest route (CLB) with
least clock skew. To put it simple, usually this is calculated based on logic levels
between a source to destination path
How do you code to reduce power in FPGA design
Avoid reset for FPGA
Clock Gate
Use synchronous design
Avoid overconstraining
Reduce Device temperature (cooling solution)
Use clk_en and control enable for all Memory
Use LUT for smaller memory. BRAM takes more power
How do you manage multiple clocks and how do you route them
CDC tools can help this like Spyglass, etc. But asynchronous transfers must be
handles carefully in design and later they can be assigned false path for the tool to
go easy on compilation
How do you control reset logic
For FPGA, global reset is sufficient. Use async reset for internal logic and sync that
reset in main clk (if they are in same clock, else use accordingly)
Always assert the reset asynchronously and de-assert synchronously with clock

Some questions about RTL coding for FPGA primitive components, what
are the primitive components and what have you used.
BUFGMUX, ibuff, obuff, etc
What is the difference between PAL and PLD?
PLD (programmable logis devices) has a programmable OR plane, and
fixed AND plae, PLA (programmable logis arrays) has programmable OR,
and programmable AND palne, PAL (programmable array logic) has fixed
OR, and programmable AND plane.
What do you understand by transport delay and
inertial delay?
Transport delay: Transport delay is a type of delay caused by the wires
that connect to the gates. Due to the wire's resistance and inductance, it
delays the signal.
Inertial delay: The inertial delay is the time it takes for a gate to change
its output.
Why might you choose to use an FPGA in your design?

FPGAs are highly customizable. Some reasons to use an FPGA in your

design might be: many unique peripherals required, lots of input/output
needed, very fast processing speed required, lots of math operations,
high data throughputs, interfaces to high bandwidth external memory,
and reprogrammability are common reasons.
What does a for loop do in synthesizable code?
Does it work the same way as in a software
language like C?
A for loop in VHDL and Verilog is not the same thing as a for loop in
python or C. In synthesizable code, for loops are used to replicate logic.
It saves having to type the same thing over and over again, but it does
not produce a loop in the same way that software programming loops
work. In general, for loops should be avoided in synthesizable code for
beginners unless they clearly understand how they work. Further
Reading:
 What is the purpose of a PLL?

PLL stand for Phase-locked loop and is commonly used inside FPGAs to
generate desired clock frequencies. PLLs are built-in to the FPGA fabric
and are able to take an input clock and derive a unique out-of-phase
clock from that input clock. They are very useful if your design requires
several unique clocks to be running internally.
 Describe the difference between inference and
instantiation
Inference is when you write VHDL or Verilog to “infer” or tell the
synthesis tools to place some type of component down. For example, by
creating a large memory storage register, you might be inferring a Block
RAM. Instantiation is when you directly create the primitive component
for the Block RAM based on the particular vendor’s user guide for how
to instantiate primitive components. Inferrence is more portable across
FPGA technologies. Instantiation might be better if you need to be very
explicit about the primitive that you want to work with, or apply some
unique settings to it.
 What is FIFO?
FIFO stands for First In First Out. It is a commonly used FPGA
component. A FIFO is a storage element, usually made of a Block RAM
for large FIFOs and registers for short FIFOs. They are used to buffer
data, for example when reading and writing to external memory, or for
when crossing clock domains, or for storing pixels coming out of a
camera. Further Reading
 What is a Block RAM?

A Block RAM is a specific part of an FPGA that is usually a 16k or 32k bits
storage element. It can have dynamic width and depth and is useful for
many applications inside of an FPGA. They are used in Dual-port
memories, FIFOs, and LUTs to name a few.
 What is a shift register in an FPGA?

A shift register is a method of moving data from a source to a

destination in some number of clock cycles. It is useful for creating
delays inside of your FPGA, or for converting serial data to parallel data,
or for converting parallel data to serial data.
 What is the purpose of the synthesis tools?

The synthesis tools are provided by the FPGA vendor and are used to
translate your VHDL or Verilog code into logic that the FPGA is built from
(e.g. Flip-Flops, Look-Up Tables, Block RAMs, etc).
 What happens during Place and Route?

The synthesis process is usually followed by place and route, which

takes the primitives and places them inside the FPGA and checks that
the entire design meets your timing constraints. The timing constraints
tell the FPGA the clock rates and the specific I/O to use, and the place
and route process ensures that your design is able to work at those
speeds.
 What is a SERDES transceiver and where are they
used?
SERDES stands for SERializer/DESerializer. These are high-speed
transmitters and receivers that are used to send serial data across a
point to point link. Usually these are used at speeds of > 1 Gbps. Current
FPGA technology can have SERDES transceivers that operate at > 50
Gbps for a single data link. Data integrity at these speeds is very
challenging, so lots of tricks are employed to ensure data is able to pass
successfully. They are used commonly in RF applications, high-speed
video applications, communication interfaces such as PCI Express, SATA,
Gigabit Ethernet, etc.
 Data Required Time

the sum of the delay from a clock source to the clock

pin of the destination register, minus the micro setup
time of the destination register.

Clock latency
The time taken by Clock signal to reach from clock source
to the clock pin of a particular flip flop is called as Clock
latency. Clock skew can also be termed as the difference
between the capture clock latency and the launch clock
latency for a set of flops.
False path and multicycle paths are the timing exceptions
in the design.
False paths:
Paths in the design which doesn't require timing analysis
are called False paths. These paths are timing
exceptions in the design. Which is commonly occured in
the blocks at which more than one clock is involving in the
functionality