536 FET AMPLIFIERS

FIG. 8.68
Analysis of a JFET self-bias network using Multisim.

in Chapter 9 as Fig. 9.70 when we turn our attention to the frequency response of a loaded
JFET amplifier. A detailed analysis is provided in Chapter 9, including determining the dc
levels, the value of gm, and the loaded gain. The drain current of Example 9.12 is 2 mA,
resulting in a drain voltage of 10.6 V and a source voltage of 2 V, which compare very well
with the 10.594 V and 2.0 V respectively, of Fig. 8.68. When a load such as RL is added to
the network, it will appear in parallel with RD of the network, changing the gain equation
to -gmRD 储 RL. For Example 9.12, gm is 2 mS, resulting in a gain Vo > Vi of (2 mS)
(2.2 k 储 4.7 k) = -2.997. The meters of Fig. 8.68 provide the effective values of the
voltages at those points. Since we used a power source, the reading of the meter XMM1 is
very close to that of the applied source. The difference is due solely to the ac drop of volt-
age across Rsig and CG. The magnitude of the ac gain (Vo > Vi) of the configuration is
2.042 mV>0.699 mV  2.921, which is very close to the hand-calculated solution.

PROBLEMS
●
Note: Asterisks indicate more difficult questions.
8.2 FET Small-Signal Model
1. Calculate gm0 for a JFET having device parameters IDSS = 12 mA and VP = - 4 V.
2. Determine the pinch-off voltage of a JFET with gm0 = 10 mS and IDSS = 12 mA.
3. For a JFET having device parameters gm0 = 5 mS and VP = - 4 V, what is the device current
at VGS = 0 V?
4. Calculate the value of gm for a JFET (IDSS = 12 mA, VP = - 3 V) at a bias point of VGS =
- 0.5 V.
5. For a JFET having gm = 6 mS at VGSQ = - 1 V, what is the value of IDSS if VP = - 2.5 V?
6. A JFET (IDSS = 10 mA ,VP = - 5 V) is biased at ID = IDSS >4. What is the value of gm at that
bias point?
7. Determine the value of gm for a JFET (IDSS = 8 mA, VP = - 5 V) when biased at VGSQ = VP >4.
8. A specification sheet provides the following data (at a listed drain-source current):
gfs = 4.5 mS, gos = 25 mS
At the listed drain–source current, determine:
a. gm.
b. rd.
9. For a JFET having specified values of gfs = 4.5 mS and gos = 25 mS, determine the device
output impedance Zo (FET) and device ideal voltage gain Av(FET).
10. If a JFET having a specified value of rd = 100 k has an ideal voltage gain of Av(FET) = - 200,
what is the value of gm?
 ID (mA) PROBLEMS 537

10
9
8
7
6
5
4
3
2
1

−5 −4 −3 −2 −1 0 VGS (V)

FIG. 8.69
JFET transfer characteristic for Problem 11.

11. Using the transfer characteristic of Fig. 8.69:

a. What is the value of gm0?
b. Determine gm at VGS = - 0.5 V graphically.
c. What is the value of gm at VGSQ = - 0.5 V using Eq. (8.6)? Compare with the solution to
part (b).
d. Graphically determine gm at VGS = - 1 V.
e. What is the value of gm at VGSQ = - 1 V using Eq. (8.6)? Compare with the solution to
part (d).
12. Using the drain characteristic of Fig. 8.70:
a. What is the value of rd for VGS = 0 V?
b. What is the value of gm0 at VDS = 10 V?

ID (mA)

10
VGS = 0 V
9

6
−1 V
5

3
−2 V
2

1 −3 V −4 V

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDS (V)

FIG. 8.70
JFET drain characteristic for Problem 12.

13. For a 2N4220 n-channel JFET [gfs(minimum) = 750 mS, gos(maximum) = 10 mS]:
a. What is the value of gm?
b. What is the value of rd?
14. a. Plot gm versus VGS for an n-channel JFET with IDSS = 12 mA and VP = - 6 V.
b. Plot gm versus ID for the same n-channel JFET as part (a).
15. Sketch the ac equivalent model for a JFET if gfs = 5.6 mS and gos = 15 mS.
16. Sketch the ac equivalent model for a JFET if IDSS = 10 mA, VP = - 4 V, VGSQ = - 2 V, and
gos = 25 mS.
538 FET AMPLIFIERS 8.3 Fixed-Bias Configuration
17. Determine Zi, Zo, and Av for the network of Fig. 8.71 if IDSS = 10 mA, VP = - 6 V, and
rd = 40 k.
18. a. Determine Zi, Zo, and Av for the network of Fig. 8.71 if IDSS and VP are one-half the values
of Problems 17. This is IDSS  5 mA and VP  3 V.
b. Compare the solutions to that of Problem 17.
19. a. Determine Zi, Zo, and Av for the network of Fig. 8.72 if IDSS  10 mA, VP  4 V, and
rd  20 k.
b. Repeat part (a) with rd  40 k. What was the impact on the results?

+18 V

RD 1.8 kΩ

Vo
Vo
Zo IDSS = 10 mA
VP = –4 V
Vi 4.7 k
Zo 10 V
1 MΩ RG
Zi – Vi –2.5 V
1.5 V 2 M
+ Zi

FIG. 8.71 FIG. 8.72

Fixed-bias amplifier for Problems 17 and 18. Problem 19.

8.4 Self-Bias Configuration

20. Determine Zi, Zo, and Av for the network of Fig. 8.73 if gfs = 3000 mS and gos = 50 ms.
21. Determine Zi, Zo, and Av for the network of Fig. 8.73 if the 20@mF capacitor is removed and the
parameters of the network are the same as in Problem 20. Compare results with those of
Problem 20.
22. Repeat Problem 20 if gos is 10 mS. Compare the results to those of Problem 20.
23. a. Find the value of RS to obtain a voltage gain of 2 for the network of Fig. 8.74 using rd   .
b. Repeat part (a) with rd  30 k. What was the impact of the change in rd on the gain and
the analysis?

+12 V 16 V

3.3 kΩ RD 2.7 k

Vo Vo
C2
Vi Vi IDSS = 9 mA
Zo VP = –8 V
C1

Zi 10 MΩ 1 M
1.1 kΩ CS 20 μF RS

FIG. 8.73 FIG. 8.74

Problems 20, 21, 22, and 59. Problem 23.

24. Determine Zi, Zo, and Av for the network of Fig. 8.75 if IDSS = 6 mA, VP = - 6 V, and
gos = 40 mS.
 +20 V PROBLEMS 539

20 V
2 kΩ
2 kΩ 82 MΩ
Vo
Vo
C2 IDSS = 12 mA
Vi
VP = − 3 V
Vi Zo rd = 50 kΩ
C1
Zi
Zi 1 MΩ 11 MΩ Zo
RS CS
610 Ω

FIG. 8.75 FIG. 8.76

Self-bias configuration for Problems 24 and 60. Problems 25 to 28 and 61.

8.5 Voltage-Divider Configuration

25. Determine Zi, Zo, and Vo for the network of Fig. 8.76 if Vi = 20 mV.
26. Repeat Problem 25 with the capacitor CS removed and compare results.
27. Repeat Problem 25 if rd = 20 k and compare results.
28. Repeat Problem 26 if rd = 20 k and compare results.
8.6 JFET Common-Gate Configuration
29. Determine Zi, Zo, and Vo for the network of Fig. 8.77 if Vi = 4 mV.
30. Repeat Problem 29 if rd = 20 k and compare results.
31. Determine Zi, Zo, and Av for the network of Fig. 8.78 if rd = 30 k.

+22 V
+15 V

91 MΩ 2.2 kΩ
3.3 kΩ
Vi Vo
Vi Vo Zo
IDSS = 8 mA Zi
Zo 1 kΩ IDSS = 7.5 mA
Zi 1.5 kΩ VP = − 2.8 V VP = −4 V
11 MΩ
rd = 40 kΩ

FIG. 8.77 FIG. 8.78

Problems 29, 30, and 62. Problem 31.

8.7 JFET Source-Follower Configuration

32. Determine Zi, Zo, and Av for the network of Fig. 8.79.
33. Repeat Problem 32 if rd = 20 k and compare results.
34. Determine Zi, Zo, and Av for the network of Fig. 8.80.
20 V

+20 V 3.3 kΩ

IDSS = 9 mA IDSS = 6 mA
VP = −4.5 V VP = −6 V
Vi rd = 40 kΩ Vi rd = 50 kΩ

Zi Vo Vo
10 MΩ Zi 10 MΩ
2.2 kΩ Zo 3.3 kΩ Zo

FIG. 8.79 FIG. 8.80

Problems 32 and 33. Problem 34.
540 FET AMPLIFIERS 8.8 Depletion-Type MOSFETs
35. Determine Vo for the network of Fig. 8.81 if gos = 20 mS.
36. Determine Zi, Zo, and Av for the network of Fig. 8.82 if rd = 60 k.
37. Repeat Problem 36 if rd = 25 k and compare results.
+22 V
+16 V

1.8 kΩ
1.1 kΩ
Vo
Vo
IDSS = 12 mA
IDSS = 8 mA Vi VP = −3.5 V
VP = − 3 V
+ Zi Zo
Vi = 2 mV 10 MΩ 10 MΩ
100 Ω
–

FIG. 8.81 FIG. 8.82

Problem 35. Problems 36, 37, and 63.

38. Determine Vo for the network of Fig. 8.83 if Vi = 1.8 mV.

39. Determine Zi, Zo, and Av for the network of Fig. 8.84.

+18 V

+20 V
6.8 kΩ
91 MΩ Vo
91 MΩ IDSS = 12 mA
gfs = 35 μS VP = −3 V
Vi gos = 6000 μS Vi rd = 45 kΩ
Vo
Zi
15 MΩ 10 MΩ
3.3 kΩ 1.1 kΩ Zo

FIG. 8.83 FIG. 8.84

Problem 38. Problem 39.

8.10 E-MOSFET Drain-Feedback Configuration

40. Determine gm for a MOSFET if VGS(Th) = 3 V and it is biased at VGSQ = 8 V. Assume
k = 0.3 * 10-3.
41. Determine Zi, Zo, and Av for the amplifier of Fig. 8.85 if k = 0.3 * 10-3.
42. Repeat Problem 41 if k drops to 0.2 * 10-3. Compare results.

+16 V

2.2 kΩ
10 MΩ
Vo

Zo
Vi VGS(Th) = 3 V
rd = 100 kΩ
Zi

FIG. 8.85
Problems 41, 42, and 64.
 43. Determine Vo for the network of Fig. 8.86 if Vi = 20 mV. PROBLEMS 541
44. Determine Vo for the network of Fig. 8.86 if Vi = 4 mV, VGS(Th) = 4 V, and ID(on) = 4 mA,
with VGS(on) = 7 V and gos = 20 mS.

+20 V

10 kΩ
22 MΩ
Vo

VGS(Th) = 3.5 V
Vi k = 0.3 × 10−3
gos = 30 μS

FIG. 8.86
Problems 43 and 44.

8.11 E-MOSFET Voltage-Divider Configuration

45. Determine the output voltage for the network of Fig. 8.87 if Vi = 0.8 mV and rd = 40 k.

30V

3.3 kΩ

40 MΩ
+
VGS(Th) = 3 V
k = 0.4 × 10 −3
+ Vo

Vi 10 MΩ
1.2 kΩ
– –

FIG. 8.87
Problem 45.

8.12 Designing FET Amplifier Networks

46. Design the fixed-bias network of Fig. 8.88 to have a gain of 8.
47. Design the self-bias network of Fig. 8.89 to have a gain of 10. The device should be biased at
VGSQ = 13VP.

+VDD (+22 V)

+VDD (+20 V)

RD
RD
Vo Vo
IDSS = 8 mA
Vi Vi IDSS = 12 mA
VP = − 2.5 V VP = − 3 V
yos = 20 μS rd = 40 kΩ
10 MΩ 10 MΩ
RS

FIG. 8.88 FIG. 8.89

Problem 46. Problem 47.
542 FET AMPLIFIERS 8.14 Effect of RL and Rsig
48. For the self-bias JFET network of Fig. 8.90:
a. Determine AvNL, Zi, and Zo.
b. Sketch the two-port model of Fig. 5.75 with the parameters determined in part (a) in place.
c. Determine AvL and Avs.
d. Change Rsig to 10 k and calculate the new levels of AvL and Avs. How is the voltage gain
affected by an increase in Rs?
e. For the change of part (d), determine Zi and Zo. What was the effect on both impedances?

12 V

2.7 kΩ

10 μF
Vo
Rsig Vi
IDSS = 10 mA
0.6 kΩ VP = − 6 V
10 μF
+ Zo RL 4.7 kΩ
Vs Zi 1 MΩ
– 0.51 kΩ 20 μF

FIG. 8.90
Problem 48.

49. For the source-follower network of Fig. 8.91:

a. Determine AvNL, Zi, and Zo.
b. Sketch the two-port model of Fig. 5.75 with the parameters determined in part (a) in place.
c. Determine AvL and Avs.
d. Change RL to 4.7 k and calculate AvL and Avs. What was the effect of increasing levels of
RL on both voltage gains?
e. Change Rsig to 20 k (with RL at 2.2 k) and calculate AvL and Avs. What was the effect of
increasing levels of Rsig on both voltage gains?
f. Change RL to 4.7 k and Rsig to 20 k and calculate Zi and Zo. What was the effect on both
impedance parameters?

12 V

IDSS = 6 mA
Rsig 8.2 μF
Vi VP = − 6 V

0.5 kΩ
Vo
+
Vs 8.2 μF
2 MΩ
3.3 kΩ 2.2 kΩ
– Zi Zo

FIG. 8.91
Problem 49.

50. For the common-gate configuration of Fig. 8.92:

a. Determine AvNL, Zi, and Zo.
b. Sketch the two-port model of Fig. 5.75 with the parameters determined in part (a) in place.
c. Determine AvL and Avs.
d. Change RL to 2.2 k and calculate AvL and Avs. What was the effect of changing RL on the
voltage gains?
 18 V PROBLEMS 543

3.3 kΩ

5.6 μF
Vo

IDSS = 5 mA
VP = − 4 V

Rsig 5.6 μF Vi Zo 4.7 kΩ

+ 0.5 kΩ
Vs 1.2 kΩ
Zi
–

FIG. 8.92
Problem 50.

e. Change Rsig to 0.1 k (with RL at 4.7 k) and calculate AvL and Avs. What was the effect of
changing Rsig on the voltage gains?
f. Change RL to 2.2 k and Rsig to 0.1 k and calculate Zi and Zo. What was the effect on both
parameters?
g. What general conclusions can you draw from the above calculations?

8.15 Cascade Configuration

51. For the JFET cascade amplifier in Fig. 8.93, calculate the dc bias conditions for the two identi-
cal stages, using JFETs with IDSS = 8 mA and VP = - 4.5 V.
52. For the JFET cascade amplifier of Fig. 8.93, using identical JFETs with IDSS = 8 mA and
VP = - 4.5 V, calculate the voltage gain of each stage, the overall gain of the amplifier, and
the output voltage Vo.
53. If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having specifications
IDSS = 12 mA and VP = - 3 V, calculate the resulting dc bias of each stage.
54. If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having the specifica-
tions IDSS = 12 mA, VP = - 3 V, and gos = 25 mS, calculate the resulting voltage gain for
each stage, the overall voltage gain, and the output voltage, Vo.

Vo

Vi
20 mV

FIG. 8.93
Problems 51 to 55, 65, and 66.
544 FET AMPLIFIERS 55. For the cascade amplifier of Fig. 8.93, using JFETs with specifications IDSS = 12 mA,
VP = - 3 V, and gos = 25 mS, calculate the circuit input impedance (Zi) and output imped-
ance (Zo).
56. For the cascade amplifier of Fig. 8.94, calculate the dc bias voltages currents of each stage.
57. For the amplifier circuit of Fig. 8.94, calculate the voltage gain of each stage and the overall
amplifier voltage gain.
58. Calculate the input impedance (Zi) and output impedance (Zo) for the amplifier circuit of
Fig. 8.94.

FIG. 8.94
Problems 56 to 58.

8.19 Computer Analysis

59. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.73.
60. Using Multisim, determine the voltage gain for the network of Fig. 8.75.
61. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.76.
62. Using Multisim, determine the voltage gain for the network of Fig. 8.77.
63. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.82.
64. Using PSpice Windows, determine the voltage gain for the network of Fig. 8.85.
*65. Use the Design Center to draw a schematic circuit of the cascade JFET amplifier as in Fig.
8.93. Set the JFET parameters for IDSS  12 mA and VP = 3 V, and have the analysis deter-
mine the dc bias.
*66. Use the Design Center to draw a schematic circuit for a cascade JFET amplifier as shown
in Fig. 8.93. Set the analysis to calculate the ac output voltage Vo for IDSS  12 mA and
VP  3 V.