Programmable peripheral interface 8255

PPI 8255 is a general purpose programmable VO device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We can
assign different ports as input or output functions.
Block diagram -

+5V GROUP A I/0

POWER
PORT A PA7- PAO
SUPPLIES GND GROUP A
cONTROL
(8)

GROUPA
BI-DIRECTIONAL PORT C
DATA BUS UPPER (4) VPC7- PCA
DATA BUs
D7-DO BUFFER
8-BIT GROUP B
INTERNAL PORT C
DATA BUs LOWER (4

RD
WR READ GROUPE
WRITE CONTROL GROUP B /O
A
CONTROL PORT B PB7- PBO
LOGIC (8)
RESET

It consists of40 pins and operates in +5V regulated power supply. Port C is frther divided into two 4-bit
ports i.e. port C lower and port C upper and port C can work in either BSR (bit set rest) mode or in mode
Oof input-output mode of 8255. Port Bcan work in either mode or in mode l of input-output mode. Port
Acan work either in mode 0, mode 1 or mode 2 of input-output mode.
It has two control groups, control group A and control group B. Control group A consist of port
A and port Cupper. Control group B consists of port Clower and port B.
Depending upon the value if cs, Aland A0 we can select different ports in different modes as
input-output function or BSR. This is done by writing a suitable word in control register (control
word D0-D7).

CS A1 A0 SELECTION ADDRESS

0 0 PORT A 80 H

1 PORT B 81 H

0 1 PORT C 82 H

0 1 Control Register 83 H

X X No Seletion X
Pin diagram -

PA3 4| 40 K PA4
PA24 2 39 k> PAS
PA143 38 k PA6
PAO 4 4 37k PA7
RD' 36 WR'
CS 35 k RESE
GNDH7 34 ’ DO
VSS8 33 k> D1
A1 9 32 k’ D2
A0 4 10 8255 31 ’ D3
PC7 4 11 30 k D4
PC6 12 29 k’ D5
PC5 13 28 k’ D6
PC4 14 27 k’ D7
PCO 4 15 26 k- VCC
PC2 4> 16 25 > PB7
PC3 17 24k PB6
PBO 18 23 k’ PB5
PB1 4 19 22 k PB4
PB2 4 20 21 k’ PB3

PAO PA7- Pins of port A

PB0 - PB7- Pins of port B
PCO - PC7- Pins of port C
DO - D7-Data pins for the transfer of data
RESET- Reset input
RD' - Read input
WR'-Write input
CS'-Chip select
Al and A0 Address pins

Operating modes -

1. Bit set reset (BSR) mode -

If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C bits
are used for set or reset.

CONTROL REGISTER IN BSR MODE

D7 D6 D5 D4 D3 D2 D1 DO

X X X

PORT C BIT NUMBER SET/RESET SPECIFIED BIT

0- RESET
1- SET
2. Input-Output mode -
If MSB of control word (D7) is 1, PPI works in input-output mode. This is further divided
into three modes:

CONTROL REGISTER INPUT-OUTPUT MODE

D7 D6 D5 D4 D3 D2 D1 DO

MODE SELECTION OF PORT A

00- MO
/O FUNCTION OF PORT C
OF PORTB
01 - M1
UPPER I/O FUNCTION
1X- M2 OF PORT A MODE SELECTION
OF PORTB OF PORTC
LOWER
1- INPUT 0 - MO
FOR I/O FUNCTION-
0-OUTPUT 1- M1

Mode 0 In this mode all the three ports (port A, B, C) can work as simple input
function or simple output function. In this mode there is no interrupt handling
capacity.
Mode 1 - Handshake VO mode or strobbed I/O mode. In this mode either port A or
port B can work as simple input port or simple output port, and port C bits are used
for handshake signals before actual data transmission. It has interrupt handling
capacity and input and output are latched.
Example: A CPU wants to transfer data to a printer. In this case since speed of
processor is very fast as compared to relatively slow printer, so before actual data
transfer it will send handshake signals to the printer for synchronization of the speed
of the CPU and the peripherals.

DO-D7
STB'
CPU PRINTER
ACK
BUSY

Mode 2 - Bi-directional data bus mode. In this mode only port A works, and port
Bcan work either in mode 0 or mode l.6 bits port C are used as handshake signals.
It also has interrupt handling capacity.
 Peripheral Devlces and thelr Interfacing 103
&Draw and dlscuss the block dtagram of progranmable
?
Interval
ttmer (8253, What are the basle functlon of data bus buffer
Or
Draw the functional block dlagram of programmable lnterval timer.
(R.GPV., June 2008)
Ans. The block diagram of 8253 is shown in fig 3.16. It includes three
control logic, and a
counters (0,1 and 2), a data bus buffer, Read/Writecounter -Clock( CLK)
controlregister. There are two input signals for each
and GATE-and one output signal -OUT. CLKO
Data
Counter
Bus GATE 0
Buffer OUT 0
RD
CLK 1

WR dRead/
Write
|Counter
=1
GATE I
Ap Logic.
A

CLK2
Control Counter GATE 2
Word =2 OUT 2
Register
Internal Bus
Data Bus (8-bit)
D-Do.
CLK N Counter Clock Inputs
GATEN, Counter Gate Inputs
OUT N Counter Outputs
RD
Read'Counter
WR Write Command or Data
Chip Select
CS Counter Select
Ag-A1 +5 volts
VCC Ground
GND
Fig. 3.16 Block Diagram of 8253
Buffer- This is tri-_tate, 8-bit, bidirectional bffer.
i ( ) Data Bus
the MPU.
This is connected-to the data bus of
Logie - Control, section includes five signals, which
() Control Select) and the address lines A, and
are- RD (Read), WR (Write), CS (ChipRD signals are connected to I0W
and
Aj For peripheral IO mode, WR memory-mapped I/0, these are connected
arnd IOR:respectively. In the case ofMEMR.(Memory Read). Usually, address
to MEMW (Memory Write) andconnected to lines An and A, of the 8254 and.
lines A, and A, of theMPU. are
CS is tied to a decoded address.
 (V-Sem, EC Branch)
104 Microprocessor and Microcontrolers
According to the signals on linesas A,below
and A, control word register?
counters are selected. This is shown
A Selection
0 Counter 0
1 Counter 1
Counter 2
Control Register
() Control Word Register - When lines An and A, are at logie f
this register is accessed. It is used to write a command word that specifies
counter to be used, its mode, either a Write or a Read operation. In fig. 3.s
the control word format is shown.

D7 D6 Dg D4 D; D2 DË Do
sc1 scoRwRwo M2MI MOBCo|
SC- Select Counter: M-MODE:
SC1 SCO M2 MI MO

Select Counter 0 ooo Mode 0

0 1 Select Counter 1 00 1 Mode 1
|1| 0 Select.Counter 2 Mode 2
Read-back Command Mode 3
(See Read Onerations) Mode 4
|10 1 . Mode 5
RW- Read/Write : BCD:
RWI RWO

00 Counter Latch Command (see Read Binary Counter 16-bits

Operations) Binary Coded Decimal
01Read/ Write Least Significant Byte Only. (BCD) Counter (4 Decades)
1 0Read/Write Most Significant Byte
1ReadWrite Least Significant
Byte first, Then Most Significant Byte
Notes- Don't Care Bits (X) Should be 0 to Ensure Compatability with Future Intcl Products.

Fig. 3.17 Control Word Format

Functions of Data Bus Buffer - The 8-bit, bidirectional data buftet
interfaces the internal circuit of 8253 to microprocessor system bus. Data a
transmitted or received by the buffer upon the execution of IN and OU!
instruction. The read/write logic controls the direction of the data butter
depending upon whether it is a read or a write operation, It may be noted tha
IN instruction reads data while OUT instruction writes data to a
peripheral.
l), Wrile short note on 8254 timer. (R.G.PV, Dec. 2003)
Ans. The programmable interval timer/counter (8254) is functionaly
similar to the software designed timers and counters, It
time.delays and can be used for applications:such as a produces accural
real-time clock,
 Perlpheral Devlces and thelr Interfacing 105
Aioital one-shot, an event counter, a complex
square-wave generator. wavefortm gencrator and a
The 8254 consists threc identical 16-bit
counters which can operate
independently in any one of the 6-modes. It is packaged
needs a single +5V power supply. For operating a counter,in a 24-pin DIP and
Joaded in its register and on command, starts to a 16-bit count is
reaches 0. When count decrement the.count until it
ends, it generates a pulse which can be used to interrupt
the MPU. The counter can count either in BCD or binary. In
can be read by MPUwhile the counter is addition, a count
decrementing.
The 8254 is an upgraded version of 8253 and
they-are-pin-compatible.
The following features of 8254 are diferent from 8253
(i) The 8254 contains a status read-back
the count and the.status of the counters.
command which can latch
(ii) The 8254 can operate with higher clock frequency. range (D.C.
to 8 MHz and 10 MHz for 8254-2). On the.other hand, the
8253 can operate
with clock frequency from D.C. to 2 MHZ.
0.20.: Explain various operating modes of 8254 timer.
(R.G.PV, June 2003, 2004(NNJ
Or
Write mod -0', mode 2° and nnode 4' operation of programmable
intervdl timer. (R. G.PV, June 2008)
Ans. There are following six modes of operation in which eàch of the
three counters of 8254 (8253).can be operated
(1) Mode 0 -Interrupt on terminalcount
(ii) Mode 1 - Programmable.one-shÍt
(ii) Mode 2- Rate generator
(iv) Mode 3- Square wave'rate generator
(v) Mode4''Softwate-triggered strobe
(vi) Mode S+Hardware-triggered strobe.