Behavioral Code for 4x1 Multiplexer: Testbench for Behavioral Code:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

entity mux_4_1_behav is entity tb_mux_4_1_behav is

port (a: in std_logic_vector(3 downto 0); end tb_mux_4_1_behav;
s: in std_logic_vector(1 downto 0);
z: out std_logic); architecture testbench of tb_mux_4_1_behav is
end mux_4_1_behav; component mux_4_1_behav is
port (a: in std_logic_vector(3 downto 0);
architecture behavioural of mux_4_1_behav is s: in std_logic_vector(1 downto 0);
begin z: out std_logic);
behave : process(a, s) end component;
begin
if (s<="00") then z<=a(0); signal a: std_logic_vector(3 downto 0);
elsif (s<="01") then z<=a(1); signal s: std_logic_vector(1 downto 0);
elsif (s<="10") then z<=a(2); signal z: std_logic;
else z<=a(3);
end if ; begin
end process; H1: mux_4_1_behav port map(a=>a, s=>s,
end behavioural; z=>z);
process begin
a <= "0110";

s <= "00";
wait for 10 ns;
s <= "01";
wait for 10 ns;
s <= "10";
wait for 10 ns;
s <= "11";
wait for 10 ns;

end process;
end testbench;

Waveform:

Page No.:
Structural Code for 4x1 Multiplexer: Testbench for Structural Code:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

entity mux_4_1_struct is entity tb_mux_4_1_struct is

port (a: in std_logic_vector(3 downto 0); end tb_mux_4_1_struct;
s: in std_logic_vector(1 downto 0);
z: out std_logic); architecture testbench of tb_mux_4_1_struct is
end mux_4_1_struct; component mux_4_1_struct is
port (a: in std_logic_vector(3 downto 0);
architecture structural of mux_4_1_struct is s: in std_logic_vector(1 downto 0);
component not_gate is z: out std_logic);
port(m: in std_logic; o: out std_logic); end component;
end component;
component and_3_gate is signal a: std_logic_vector(3 downto 0);
port (l, m, n: in std_logic; o: out std_logic); signal s: std_logic_vector(1 downto 0);
end component; signal z: std_logic;
component or_4_gate is
port (v, w, x, y: in std_logic; z: out begin
std_logic); H1: mux_4_1_struct port map(a=>a, s=>s, z=>z);
end component; process begin
signal sbar_0, sbar_1: std_logic; a(0) <= '1';
signal temp: std_logic_vector(3 downto 0); a(1) <= '1';
a(2) <= '0';
begin a(3) <= '0';
inv_s0: not_gate port map(s(0), sbar_0); s <= "00";
inv_s1: not_gate port map(s(1), sbar_1); wait for 10 ns;
a_1: and_3_gate port map(a(0), sbar_0, sbar_1, s <= "01";
temp(0)); wait for 10 ns;
a_2: and_3_gate port map(a(1), s(0), sbar_1, s <= "10";
temp(1)); wait for 10 ns;
a_3: and_3_gate port map(a(2), sbar_0, s(1), s <= "11";
temp(2)); wait for 10 ns;
a_4: and_3_gate port map(a(3), s(0), s(1), end process;
temp(3)); end testbench;
or_inst: or_4_gate port map(temp(0), temp(1),
temp(2), temp(3), z);
end structural;

Waveform:

Page No.:
Dataflow Code for 4x1 Multiplexer: Testbench for Dataflow Code:

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;

entity mux_4_1_dataf is entity tb_mux_4_1_dataf is

port (a: in std_logic_vector(3 downto 0); end tb_mux_4_1_dataf;
s: in std_logic_vector(1 downto 0);
z: out std_logic); architecture testbench of tb_mux_4_1_dataf is
end mux_4_1_dataf; component mux_4_1_dataf is
port (a: in std_logic_vector(3 downto 0);
architecture dataflow of mux_4_1_dataf is s: in std_logic_vector(1 downto 0);
begin z: out std_logic);
with s select end component;
z <= a(0) when "00", signal a: std_logic_vector(3 downto 0);
a(1) when "01", signal s: std_logic_vector(1 downto 0);
a(2) when "10", signal z: std_logic;
a(3) when "11",
unaffected when others; begin
H1: entity work.mux_4_1_dataf port map(a=>a,
end dataflow; s=>s, z=>z);
process begin
a(0) <= '1';
a(1) <= '1';
a(2) <= '1';
a(3) <= '0';
s <= "00";
wait for 10 ns;
s <= "01";
wait for 10 ns;
s <= "10";
wait for 10 ns;
s <= "11";
wait for 10 ns;
end process;
end testbench;

Waveform:

Page No.: