ITI1100-1500 Final Examination Page 2 of 5

Student Name (Please print)______________________________________________

Student Number____________________________________ Section:_______

ITI1100-1500-Digital Systems I
Previous Final Examination

Time: 19:00-22:00 (3 hours)

Professor: Ahmed Karmouch,

Instructions:
• Answer ALL questions.
• This is a closed-book examination.
• Use the provided space to answer the following questions. If more space is needed, use the
back of the page.
• Show all your calculations to obtain full marks.
• Calculators are NOT allowed.
• Read all the questions carefully before you start.

(The following space is reserved for professors)

Question Points Percentage

1 20%
2 30%
3 20%
4 20%
5 10%
Total 100%
 ITI1100-1500 Final Examination Page 3 of 5
Question 1 (20 points)
Convert A = (8.25)10 and B = (24.5)10 into binary format employing 7 bits for the integer part and
2 for the fractional part, including the sign bit. Perform the following operations using the 1’s
complement method.

(i) A + B; (ii) A – B.

Explain clearly your solution.

3
A = 8.25 = 0001000.01
3 B = 24.5 = 0011000.10 -B = -24.5 = 1’s complement of B = 1100111.01 4

1 1
4
A+ 0 0 0 1 0 0 0 . 0 1 + 8.2510 + 1
B 0 0 1 1 0 0 0 . 1 0 24.5010
S 0 1 0 0 0 0 0 . 1 1 32.7510 0100000.11 = 25 + 2-1+ 2-2 = 32.75

4 1
A+ 0 0 0 1 0 0 0 . 0 1 + 8.2510 + 1
(-B) 1 1 0 0 1 1 1 . 0 1 -24.5010
D 1 1 0 1 1 1 1 . 1 0 -16.2510 1’s compl. of (1101111.10) = - 0010000.01 =
= - (24 + 2-2) = -16.25

Question 2 (10 + 5 = 15points)

A combinational logic circuit has three inputs (A, B, and C) and an output Y. The output Y = 1
when C = A, or when C = B = 0.

(i) Write the truth table of the function Y

(ii) Find the (not simplified) Boolean expression of Y in sum-of-products (SoP) form
(canonical disjunctive form).

10
A B C F F = A B  C + A B  C + A B  C + A B  C 5
0 0 0 1
0 0 1 0
0 1 0 0 -1 POINT FOR EACH INCORRECT TERM
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
 ITI1100-1500 Final Examination Page 4 of 5
Question 3: (10 points)

A BCD to 7 segment decoder has 4 inputs (A, B, C, D) and 7 outputs (a, b, c, d, e, f, g) that select
the correspondent segments of the LED display represented in the figure (a). The numeric
representation of the decimal figures is given in the figure (b) shown below.
a
f b
g
e c

d
(a) Segment
designation (b) Numeric representation of decimal numbers on the LEDs
display

Given that the decoder’s outputs are considered in “don’t care” states (marked with “X”) for any
of the 6 unused input combinations,
(i) Find the minimized sum-of-products of the output a only;
(ii)
Draw the logic diagram of the two-level NAND circuit that implements the
above expression (a).
(i) 4 for truth table or canonical form SoP of one of alow or ahigh
A B C D alow ahigh ahigh CD 00 01 11 10
0 0 0 0 0 0 1 AB
1 0 0 0 1 1 0 00 1* 0 1 1
2 0 0 1 0 0 1 01 0 1* 1 0
3 0 0 1 1 0 1 11 x x x x
4 0 1 0 0 1 0 10 1 1* x x
5 0 1 0 1 0 1 PI: A, B’D’, BD, B’C, CD
6 0 1 1 0 1 0 EPI: A, B’D’, BD B’C
7 0 1 1 1 0 1 ahigh= A + B’D’ + BD + or
CD
8 1 0 0 0 0 1
9 1 0 0 1 0 1 alow CD 00 01 11 10
10 1 0 1 0 X X AB
11 1 0 1 1 X X 00 0 1 0 0
12 1 1 0 0 X X 01 1 0 0 1
4
13 1 1 0 1 X X 11 x x x x
14 1 1 1 0 X X 10 0 0 x x
15 1 1 1 1 X X PI = EPI: alow = BD’+A’B’C’D

SoP: ahigh = (0,2,3,5,7,8,9) + d (10,11,12,13,14,15) or

a high = A  B  C  D + A  B  C  D + A  B  C  D + A  B  C  D + A  B  C  D + A  B  C  D + A  B  C  D
alow = (1,4,6) + d (10,11,12,13,14,15) or alow = A  B  C  D + A  B  C  D + A  B  C  D
 ITI1100-1500 Final Examination Page 5 of 5
(ii)


( )
a low = B  D + A  B  C  D = B  D   A  B  C  D 

a high = A + B  D + B  D + C  D =

1
U1A ( )( )(
= A  BD  BD  CD )( )
B 2
3
D' U1B
7400N 4
6
A'
in
1 5
A' 2
U2A
1 U3A
B' 4
6 7400N B' 2
3 9 U2B

C' 5 2 D' 10
8
7400N 12
D 7420N
4 U3B 13
B 5
6
7420N
D
7400N
9 U3C
C 10
8
D
7400N

Question 4: (15 points)

Being given the following sequential circuit, answer the questions:

1 T Q2 1 T Q1 1 T Q0
CLK CLK CLK
Q’2 Q’1 Q’0

Clock
(i) Draw the time diagram of the flip-flops outputs through the first 9 clock pulses.

Clock
t

7 Q0 0 1 0 1 0 1 0 1 0 1 0
t
Q’0
t
Q1 0 1 1 0 0 1 1 0 0 1 1
t
Q’1
t
Q2 0 1 1 1 1 0 0 0 0 1
0 7 6 5 4 3 2 1 0 1 2

(ii) Find the state diagram of this circuit. 7 6

0 5
5
3 (iii) What function does it perform?
It’s a count down mod-8 ripple counter 1
Let’s give them 2 points if the idea of “counting down” or 4
“frequency division” is mentioned, and other variations, too. 2 3
 ITI1100-1500 Final Examination Page 6 of 5

Question 5: (20 points)

Design a synchronous counter having the count sequence given by the following table. Use
positive edge-triggered D flip-flops provided with a clock FM.

(i) Do the counter’s state table showing the synchronous inputs of the D flip-flops, as well.
Present State Next State D inputs
Q2 Q1 Q0 D2 D1 D0 Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
6
0 0 0 0 1 0 0 0 0 0 1 0 0 1 0
0 1 0 1 0 1 0 0 1 x x x x x x
1 0 1 1 1 1 0 1 0 1 0 1 1 0 1
1 1 1 1 0 0 0 1 1 0 0 0 0 0 0
1 0 0 0 1 1 1 0 0 0 1 1 0 1 1
0 1 1 0 0 0 1 0 1 1 1 1 1 1 1
1 1 0 x x x x x x
1 1 1 1 0 0 1 0 0

(ii) Using Karnaugh maps, find the minimal sum-of-products form of the equations for the inputs
to the flip-flops; assume the next states of the unused combinations to be “don’t care states”
D2 D1 D0
Q1 Q0 00 01 11 10 Q1 Q 0 00 01 11 10 Q1 Q0 00 01 11 10
Q2 Q2 Q2
0 0 x 0 1 0 1 x 0 0 0 0 x 0 1
1 0 1 1 x 1 1 1 0 x 1 1 1 0 x
2 D2 = Q2  Q0 + Q1  Q 0 1 D1 = Q1 2 D0 = Q2  Q1 + Q1  Q 0

(iii) Draw the logic diagram of the counter 1

U4A U3A 4
U1A
~1PR
Q2 2 3 1
2
3 5
Q0 2 1D 1Q Q2
6 7408N
7432N 3 6
~1Q
1
~1CLR 7474N

10
~2PR U1B
4 U4B
Q1 5 6 12
2D 2Q
9
Q1
Q0
7408N 11 8
~2Q
(iv) Draw the state diagram. 13
~2CLR 7474N

2 5 U3B 4
~1PR U2A
U4D 4
12 6 2 5
0 7 Q213 11 5 1D 1Q Q0
Q1 7432N 3 6
7408N ~1Q
3 4 1
~1CLR
7474N