18CSC205J OPERATING SYSTEMS UNIT 3

UNIT 3

MEMORY MANAGEMENT
PART
AMULTIPLE CHOICE QUESTIONS:
1. The processes on the disk that are waiting to be brought into memory for execution form
the______________ (PgNo: 354) [L1]
a) Input queue
b) Output queue
c) Ready queue
d) Waiting queue
Answer: a
2. If it is not known at compile time that where the process will reside in memory, then the
compiler must generate(PgNo: 355)[L1]
a) Relocatable code
b) Source code
c) Absolute code
d) Error
Answer: a
3. An address generated by the CPU is commonly referred to as (PgNo :355)[L1]
a)Logical address
b) Physical address
c) CPU address
d) Disk address
Answer:a

4. The set of all logical addresses generated by a program is (PgNo: 356)[L1]

a) Logical address space
b) Logical unit
c) Logical address set
d) Logical Space
Answer: a

5. The run-time mapping from virtual to physical addresses is done by a hardware device
called(PgNo :356) [L1]
a) Memory management unit
b) Address space
c) Swap space
d) Compiler

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Answer:a

6. All routines are kept on disk in a relocatable load format. The main program is loaded
into memory and is executed whenever needed. This is called___(PgNo :357)[L1]
a) Dynamic loading
b) Dynamic linking
c) Static loading
d) Static linking Answer:a
7. A process can be taken temporarily out of memory to a backing store and then brought
back into memory for continued execution. The process ic called as___(PgNo :358)[L1]
a) Swapping
b) Loading
c) Linking
d) Backing
Answer:a
8. consists of all processes whose memory images are on the backing store /memory and
are ready to run (Pgno:359)[L1]
a) Ready queue
b) Process queue
c) Wait queue
d) Static queue
Answer:a
9. In allocation, each process is contained in a single section of memory that is continuous
to the section containing the next process. (Pgno:359)[L1]
a) Contiguous memory allocation
b) Dynamic memory allocation
c) Partition
d) Fragmentation
Answer:a

10. When a partition is free, a process is selected from the input queue and is loaded into the
free partition. This is called (Pgno:362)[L1]
a) contiguous memory allocation
b) Dynamic memory allocation
c) Multiple partition method
d) Variable partition method Answer:c

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11. In which partition scheme, the operating system keeps a table indicating which parts of
memory are available and which are occupied. (Pgno:362)[L1]
a) contiguous memory allocation
b) Dynamic memory allocation
c) Multiple partition method
d) Variable partition method Answer:d
12. All memory available for user processes are considered as one large block of available
memory is referred as hole.

13. _________strategy allocates the first hole that is large enough to accommodate the
process (Pgno:363)[L1]
a) First fit
b) Best fit
c) Worst fit
d) Least fit
Answer:a,
14. _______strategy searches the entire ordered list and allocates the smallest hole that is
large enough to accommodate the process (Pgno:363)[L1]
a) First fit
b) Best fit
c) Worst fit
d) Least fit Answer:b
15. _____strategy produces the largest leftover hole, which may be more useful than the
smaller leftover hole (Pgno:363)[L1]
a) First fit
b) Best fit
c) Worst fit
d) Least fit
Answer:c
16. _______is a condition, where when there is enough total memory space to satisfy a
request but the available spaces are not contiguous (Pgno:363)[L1]
a) First fit
b) External fragmentation
c) Internal fragmentation
d) Segmentation
Answer:b

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17. The process where the memory contents are shuffled, so as to place all free memory
together in one large block is called as (Pgno:364)[L1]
a) Compaction
b) External fragmentation
c) Internal fragmentation
d) Segmentation
Answer:a
18. The memory allocated to a process may be slightly larger than the requested memory.
The difference between these two numbers is called (Pgno:363)[L1]
a) Compaction
b) External fragmentation
c) Internal fragmentation
d) Segmentation
Answer:c
19. are the two techniques that permit the logical address space of the processes to be
noncontiguous, thus allowing a process to be allocated with physical memory wherever
such memory is available.(Pgno:364)[L1]
a) Segmentation and Paging
b) Fragmentation and Paging
c) Segmentation and Compaction
d) Paging and Compaction Answer:a
20. Which of the following segments are constructed by a compiler, whenever a program is
compiled (Pgno:365)[L1]
a) Code
b) Global variables
c) Stacks used by each thread
d) Code ,global variables and stack used by each thread. Answer:d
21. In segmentation, each address is specified by ____________(Pgno:364)[L1]
a) Segment number & offset
b) Offset & value
c) Value & segment number
d) Key & value
Answer:a
22. In Paging, physical memory is breaked into fixed-sized blocks called (Pgno:367)[L1]
a)Frames
b) Pages
c) Segments
d) Thread Answer:a

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23. In paging, logical memory is breaked into blocks of the same size called
_____ (Pgno:367)[L1]
a) Frames
b) Pages
c) Segments
d) Thread
Answer:b
24. Every address generated by the CPU is divided into two parts. They are
___________(Pgno:368)[L1]
a) frame bit & page number
b) page number & page offset
c) page offset & frame bit
d) frame offset & page offset
Answer:b
25. The size of a page is typically of size ____________(Pgno:368)[L1]
a) varied
b) power of 2
c) power of 4
d) power of 6
Answer:b
26. Modern computer systems support a large logical address
space of size_________(Pgno:378)[L1]
a) 232 to 264
b) 264 to 2128
c) 216
d) 268 Answer: a

27. Address translation works from the outer page table inward, this scheme is also known
as______(Pgno:379)[L1]
a) Forward Mapped page table
b) Backward Mapped page table
c) Forward and backward page table
d) Page table Answer: a
28. ______Architecture supports a variation of one level paging.(Pgno:379)[L1]
a) ARM
b) VAX
c) Intel 32

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d) SPARC
Answer: b
29. _______ Architecture supports a variation of four level paging. (Pgno:380) [L1]
a) ARM
b) VAX
c) Intel 32
d) ULTRASPARC
Answer: d
30. ________is an approach for handling address space larger than 32 bits.(Pgno:380)[L1]
a)Hashed page table
b) Inverted page table
c) Hierarchical page table
d) Forward mapped page table Answer: a
31. _________being the virtual page number available in hashed page table. (Pgno:380)[L1]
a)Index value
b) Hash Value
c) Location of the page
d) Pointers to the page Answer:b
32. Each entry in the hash table contains a _______of elements that hash to the same
location. (Pgno:380)[L1]
a) Stack
b) Linked List
c) Arrays
d) Queue Answer: b
33. Each entry in the hash table contains a linked list of elements that hash to the same
location to handle ____________.(Pgno:380)[L1]
a) Cohesion
b) Collision
c) Coupling
d) Collaboration Answer: b
34. 64 bit address space uses _____________page table. (Pgno:380)[L1]
a) Hashed
b) Inverted
c) Clustered
d) Hierarchical Answer :c
35. Clustered page table are useful for __________address space. (Pgno:381)[L1] a)Sparse
b) Dense

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c) Large
d) Small Answer :a
36. __________is the solution to keep track of how physical memory are used when
page table consists of millions of entries. (Pgno:381)[L1]
a) Hashed page table
b) Inverted page table
c) Hierarchical page table
d) Forward mapped page table Answer: b
37. _________is the pair of inverted page table entry. (Pgno:382)[L1]
a) < process id, page number>
b) <page number, process id>
c) <process id, offset>
d) <offset, page number> Answer:a
38. Inverted page table is sorted by _______but look ups occur
on
___________.(Pgno:382)[L1]
a) Virtual address , Physical address
b) Physical address, virtual address
c) Virtual address, logical address
d) Physical address, logical address Answer: b
39. ______________is a memory management scheme that supports user view of
memory.(Pgno:364) [L1]
a) Paging
b) Segmentation
c) Page replacement
d) Virtual memory Answer: b
40. The ________register points to the page directory for the
current process.(Pgno:385)[L1]
a) CR3
b) CR4
c) CR
d) Address Answer: a
41. If Page_size flag is set, the page directory points directly to the ______page frame,
bypassing the inner page table. (Pgno: 385)[L1]
a) 4KB
b) 2KB
c) 4MB

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d) 2MB
Answer: c
42. As software developers began to discover the 4-GB memory limitations of 32-bit
architectures, Intel adopted a___________, which allows 32-bit processors to access a
physical address space larger than 4 GB. (Pgno:386)[L1]
a) Hash table
b) page address extension
c) page address
d) page size Answer: b
43. ________paging is used for 4-KB and 16-KB pages. (Pgno:388)[L1]
a) two-level
b) One-Level
c) Three-level
d) Four-level Answer: a
44. A ____________address space is a collection of segments.(Pgno:364)[L1]
a) Physical
b) Logical
c) Virtual
d) Hashed Answer: b
45. Each entry in the segment table has a ________ and a ____________.(Pgno:366)[L1]
a) Segment base, segment Limit
b) Segment id , offset
c) Segment base, offset
d) Offset, segment limit Answer: a
46. The segment base contains the starting ___________where the segment resides in
memory. (Pgno: 366)[L1]
a) Logical address
b) physical address
c) virtual address
d) hash address
Answer: b

PART B4
MARKS:
1.Write short notes on hierarchical page table.(Pgno:378)[L1]

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18CSC205J OPERATING SYSTEMS UNIT 3

• Most modern computer systems support a large logical address space (232 to
264).
• Clearly, we would not want to allocate the page table contiguously in main
memory.
• One simple solution to this problem is to divide the page table into smaller
pieces.
• Hierarchical Paging is a paging scheme which consist of two or more levels of
page tables in a hierarchical manner.
• The entries of the level 1 page table are pointers to a level 2 page table and
entries of the level 2 page tables are pointers to a level 3 page table and so on.
• The entries of the last level page table are stores actual frame information. Level
1 contain single page table and address of that table is stored in PTBR (Page
Table Base Register).

2.Write short notes on inverted page table.(Pgno:381)[L1]

• Inverted Page Table structure consists of one-page table entry for every frame of
the main memory.
• So the number of page table entries in the Inverted Page Table reduces to the
number of frames in physical memory and a single page table is used to represent
the paging information of all the processes.
• Through the inverted page table, the overhead of storing an individual page table
for every process gets eliminated and only a fixed portion of memory is required
to store the paging information of all the processes together.
• This technique is called as inverted paging as the indexing is done with respect to
the frame number instead of the logical page number.

3.Write short notes on hashed page table.(Pgno:380)[L1]

• A common approach for handling address spaces larger than 32 bits is to use a
hashed page table, with the hash value being the virtual page number.
• Each entry in the hash table contains a linked list of elements that hash to the
same location (to handle collisions).
• Each element consists of three fields:
o(1) the virtual page number, o(2)the value of the
mapped page frame, and o(3) a pointer to the next
element in the linked list.
• The algorithm works as follows:
o The virtual page number in the virtual address is hashed into the hash
table.

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o The virtual page number is compared with field 1 in the first element in
the linked list.
o If there is a match, the corresponding page frame(field2)is used to form
the desired physical address.
o If there is no match, subsequent entries in the linked list are searched for
a matching virtual page number.

4. Discuss on X86-64 bit architecture.(Pgno:387)[L3]

• x86-64 is the64-bitversion of thex86instruction set.
• It introduces two new modes of operation, 64-bit mode and compatibility
mode, along with a new 4-levelpagingmode.
• With 64-bit mode and the new paging mode, it supports vastly larger
amounts ofvirtual memoryandphysical memorythan is possible on its
32-bit predecessors, allowing programs to store larger amounts of data in
memory.
• In 64-bit mode, instructions are modified to support 64-bit operands and
64-bit addressing mode.
• As the full x86 16-bit and 32-bit instruction sets remain implemented in
hardware without any intervening emulation, these olderexecutablescan
run with little or no performance penalty, while newer or modified
applications can take advantage of new features of the processor design to
achieve performance improvements.
5. Discuss about variations in intel32-bit and intel 64-bit architecture.(Pgno:383)[L3]
The difference between 32-bit and 64-bit processors are:
Parameter 32-bit processors 64-bit processors
Addressable 64-bit processors have 16 GB
It has 4 GB addressable space
space addressable space
Application 64-bit applications and programs 32-bit applications and
support won't work programs will work
OS SUPPORT Needed 32bit OS It can run on 32 and 64 bit OS
Works best for performing
Support of Not an ideal option for stress
multi-tasking and stress
Multitasking testing and multi-tasking.
testing.
32-bit systems limited to 3.2 GB
of RAM 32 bit Windows. It 64-bit systems will enable you
Memory Limits addresses limitation doesn't allow to store up to 17. Billion GB
you to use full 4GB of Physical of RAM
memory space.

6. Explain briefly on Intel-32 bit Segmentation.(Pgno:384)[L3]

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• The IA-32 architecture allows a segment to be as large as 4 GB, and the

maximum number of segments per process is 16 K.
• The logical address space of a process is divided into two partitions. The
first partition consists of up to 8 K segments that are private to that
process.
• The second partition consists of up to 8 K segments that are shared among
all the processes.
• Information about the first partition is kept in the local descriptor table
(LDT); information about the second partition is kept in the global
descriptor table (GDT).
• Each entry in the LDT and GDT consists of an 8-byte segment descriptor
with detailed information about a particular segment, including the base
location and limit of that segment.
• The logical address is a pair (selector, offset), where the selector is a 16bit
in which s designates the segment number, g indicates whether the
segment is in the GDT or LDT, and p deals with protection.
• The offset is a 32-bit number specifying the location of the byte within the
segment in question.

7. Explain briefly on Intel-32 bit paging.(Pgno:385)[L3]

• The IA-32 architecture allows a page size of either 4 KB or 4 MB. For
4KB pages,IA-32 uses a two-level paging scheme in which the division of
the 32-bit linear address
• The 10 high-order bits reference an entry in the outermost page table,
which IA-32 terms the page directory.
• The page directory entry points to an inner page table that is indexed by
the contents of the innermost 10 bits in the linear address.
• Finally, the low-order bits 0–11 refer to the offset in the 4-KB page
pointed to in the page table.
• One entry in the page directory is the Page Size flag, which if set indicates
that the size of the page frame is 4 MB and not the standard 4 KB.
• If this flag is set, the page directory points directly to the 4-MB page
frame, by passing the inner page table; and the 22 low-order bits in the
linear address refer to the offset in the 4-MB page frame.

8. Brief on the concept of page address extension(PAE).(Pgno:386)[L2]

• Software developers discovered the 4-GB memory limitations of 32-bit

architectures, Intel adopted a page address extension (PAE), which allows
32-bit processors to access a physical address space larger than 4 GB.

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• The fundamental difference introduced by PAE support was that paging

went from a two-level scheme to a three-level scheme, where the top two
bits refer to a page directory pointer table.
• PAE also increased the page-directory and page-table entries from 32 to
64 bits in size, which allowed the base address of page tables and page
frames to extend from 20 to 24 bits.
• Combined with the 12-bit offset, adding PAE support to IA-32 increased
the address space to 36 bits, which supports up to 64 GB of physical
memory.
• It is important to note that operating system support is required to use
PAE.

9. Explain compile time, load time, execution time with respect to address binding
(Pgno:354)[L3]
The binding of instructions and data to memory addresses can be done at any
step along the way:
• Compile time. If you know at compile time where the process will reside in
memory, then absolute code can be generated. For example, if you know that a
user process will reside starting at location R, then the generated compiler code
will start at that location and extend up from there. If, at some later time, the
starting location changes, then it will be necessary to recompile this code. The
MS-DOS .COM-format programs are bound at compile time.
• Load time. If it is not known at compile time where the process will reside in
memory, then the compiler must generate relocatable code. In this case, final
binding is delayed until load time. If the starting address changes, we need only
reload the user code to incorporate this changed value.
• Execution time. If the process can be moved during its execution from one
memory segment to another, then binding must be delayed until run time. Special
hardware must be available for this scheme to work

10. List the differences between logical and physical address (Pgno: 356)[L2]
LOGICAL ADDRESS PHYSICAL ADDRESS
The physical address is a location in a
It is the virtual address generated by CPU
memory unit
et of all logical addresses generated by Set of all physical addresses mapped to
CPU in reference to a program is referred the corresponding logical addresses is
as Logical Address Space. referred as Physical Address.
The user uses the logical address to The user can not directly access physical
access the physical address. address.

11. Discuss the need for relocation register . (Pgno:356)[L3]

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• The run-time mapping from virtual to physical addresses is done by a hardware

device called the memory-management unit (MMU).
• We can choose from many different methods to accomplish such mapping. For
the time being, we illustrate this mapping with a simple MMU scheme that is a
generalization of the base-register scheme.
• The base register is now called a relocation register. The value in the relocation
register is added to every address generated by a user process at the time the
address is sent to memory.
• For example, if the base is at 14000, then an attempt by the user to address
location 0 is dynamically relocated to location 14000; an access to location 346 is
mapped to location 14346.

12. Write the purpose of dynamic loading (Pgno:357)[L1]

• The size of a process has been limited to the size of physical memory. To obtain
better memory-space utilization, we can use dynamic loading. With dynamic
loading, a routine is not loaded until it is called.
• All routines are kept on disk in a relocatable load format. The main program is
loaded into memory and is executed.
• When a routine needs to call another routine, the calling routine first checks to
see whether the other routine has been loaded.
• If it has not, the relocatable linking loader is called to load the desired routine
into memory and to update the program’s address tables to reflect this change.
• Then control is passed to the newly loaded routine. The advantage of dynamic
loading is that a routine is loaded only when it is needed.
• This method is particularly useful when large amounts of code are needed to
handle infrequently occurring cases, such as error routines.

13. How are dynamic linked libraries are used (Pgno:357)[L2]

• Dynamically linked libraries are system libraries that are linked to user programs
when the programs are run.

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• This feature is usually used with system libraries, such as language subroutine
libraries. Without this facility, each program on a system must include a copy of
its language library (or at least the routines referenced by the program) in the
executable image. This requirement wastes both disk space and main memory.
• With dynamic linking, a stubis included in the image for each library routine
reference. The stub is a small piece of code that indicates how to locate the
appropriate memory-resident library routine or how to load the library if the
routine is not already present. When the stub is executed, it checks to see whether
the needed routine is already in memory.
• If it is not, the program loads the routine into memory. Either way, the stub
replaces itself with the address of the routine and executes the routine.

14. What is the use of swapping (Pgno:358)[L2]

• A process must be in memory to be executed. A process, however, can be
swapped temporarily out of memory to a backing store and then brought back
into memory for continued execution.
• Swapping makes it possible for the total physical address space of all processes
to exceed the realphysical memory of the system, thus increasing the degree of
multiprogramming in a system.

15. Differentiate multiple partition method and variable partition method. (Pgno:362)
[L2]
• In this multiple partition method, when a partition is free, a process is selected
from the input queue and is loaded into the free partition.
• When the process terminates, the partition becomes available for another process.
• In the variable-partition scheme, the operating system keeps a table indicating
which parts of memory are available and which are occupied.
• Initially, all memory is available for user processes and is considered one large
block of available memory, a hole.
• As processes enter the system, they are put into an input queue. The operating
system takes into account the memory requirements of each process and the
amount of available memory space in determining which processes are allocated
memory.
• When a process is allocated space, it is loaded into memory, and it can then
compete for CPU time.
• When a process terminates, it releases its memory, which the operating system
may then fill with another process from the input queue.

16. Write notes on internal fragmentation and external fragmentation (Pgno: 363)[L1]
• Internal Fragmentation:

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18CSC205J OPERATING SYSTEMS UNIT 3

Internal fragmentation happens when the memory is split into mounted

sized blocks. Whenever a method request for the memory, the mounted
sized block is allotted to the method. just in case the memory allotted to
the method is somewhat larger than the memory requested, then the
distinction between allotted and requested memory is that the Internal
fragmentation.

• External Fragmentation:

External fragmentation happens when there’s a sufficient quantity of

area within the memory to satisfy the memory request of a method.
however the process’s memory request cannot be fulfilled because the
memory offered is during a non-contiguous manner. Either you apply
first-fit or best-fit memory allocation strategy it’ll cause external
fragmentation.

17. Provide the 3 strategies for dynamic storage allocation problem. (Pgno:362)[L1]
• First fit. Allocate the first hole that is big enough. Searching can start either at
the beginning of the set of holes or at the location where the previous first-fit
search ended. We can stop searching as soon as we find a free hole that is large
enough.
• Best fit. Allocate the smallest hole that is big enough. We must search the entire
list, unless the list is ordered by size. This strategy produces the smallest leftover
hole.
• Worst fit. Allocate the largest hole. Again, we must search the entire list, unless
it is sorted by size. This strategy produces the largest leftover hole, which may be
more useful than the smaller leftover hole from a best-fit approach.

18. Explain the fifty percent rule in fragmentation. (Pgno:363)[L3].

• Depending on the total amount of memory storage and the average process size,
external fragmentation may be a minor or a major problem.
• Statistical analysis of first fit, for instance, reveals that, even with some
optimization, given N allocated blocks, another 0.5 N blocks will be lost to
fragmentation.
• That is, one-third of memory may be unusable! This property is known as the
50percent rule.

19. Suggest the best solution for external fragmentation.(Pgno:364)[L3]

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• External fragmentation exists when there is enough total memory to satisfy a

request (from a process usually), but the total required memory is not available at
a contiguous location i.e, its fragmented.

Solution to external fragmentation :

1) Compaction : shuffling the fragmented memory into one contiguous location.

2) Virtual memory addressing by using paging and segmentation.

20. What is the difference between segmentation and paging.(Pgno:365)[L2]

• The basic difference between paging and segmentation is that a page is always of
fixed block size whereas, a segment is of variable size.
• Paging may lead to internal fragmentation as the page is of fixed block size, but it
may happen that the process does not acquire the entire block size which will
generate the internal fragment in memory.
• The segmentation may lead to external fragmentation as the memory is filled
with the variable sized blocks.
• In paging the user only provides a single integer as the address which is divided
by the hardware into a page number and Offset. On the other hands, in
segmentation the user specifies the address in two quantities i.e. segment number
and offset.
• The size of the page is decided or specified by the hardware. On the other hands,
the size of the segment is specified by the user.
• In paging, the page table maps the logical address to the physical address, and it
contains base address of each page stored in the frames of physical memory
space. However, in segmentation, the segment table maps the logical address to
the physical address, and it contains segment number and offset (segment limit).

21. Explain the structure of page table. (Pgno:368)[L3]

• Every address generated by the CPU is divided into two parts: a page number(p)
and a page offset(d).The page number is used as an index into a page table.
• The page table contains the base address of each page in physical memory. This
base address is combined with the page offset to define the physical memory
address that is sent to the memory unit.

PART
C12 MARKS:
1. Draw the diagram of segmentation memory management scheme and explain its
principle. (Pgno: 364)[L3]
2. Describe in detail about the common techniques for structuring the page table.
(Pgno:378 )[L2]

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3. Elaborate on INTEL 32-bit architecture. (Pgno:383 )[L1]

4. Discuss about ARM architecture. (Pgno:388 )[L3]
5. Describe in detail on Inverted page table with neat diagram. (Pgno:381) [L3]
6. Explain segmentation in detail. (Pgno:364 )[L3]
7. Explain paging in detail. (Pgno:366 )[L3]
8. Elucidate fragmentation and propose the solutions to avoid fragmentation.
(PgNo:363) [L3]
9. Illustrate memory allocation schemes in detail. (Pgno: 362)[L3]

****************

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