Preface

The content of this book was developed in order to attend the needs
of a Text Book for the course of “Theory of Digital Electronics”.
This course belongs to curriculum of Electrical, Electronics,
Telecommunication Engineering and Computer Science Bachelor Degrees.
Also it belongs to curriculum of Electrical, Electronics and Computer
Sciences Technological Degrees
The contents of the chapter’s doesn´t need any previous knowledge
except mathematical and basic electricity of high school degree.
Because of the great amount of contents, the book is divided in two
parts, Combinational Circuits (Vol. 1) and Sequential Circuits (Vol.2).
It is recommended 4 hours of theoretical classes per week for a
semester of 17 week, divided in two groups of two hours each, or 2 hours
per week for a year of 34 weeks.
This course doesn’t require laboratory classes.
In general this course is given in the same semester of “Digital
Electronic Circuits”, that needs laboratory classes, and that needs
knowledge of “Electronics Introduction” course.
The first chapter of Vol.1 presents definitions and basic mathematical
structures. The following chapters (Vol.1) present the methods and
algorithms of Combinational Digital Circuits, beginning with analysis and
proceeding with synthesis. Some additional chapters complete the contents
with Combinational Circuits Hazards and Iterative Networks.
In the second part (Vol.2) the book presents the knowledge of
analysis and synthesis of Sequential Digital Electronics Circuits including
Asynchronous and Synchronous machines.
Additional chapters complete the contents with types of commands
and flip flops and various structures that are used in electronic digital
projects.
The contents of this book are enough for the next course of
“Microprocessors”.
A special attention is need to sections of solved and proposed
problems in each chapter.
It’s recommended three intermediate tests and the final exam for a
one semester course and four intermediate tests and the final exam for a one
year course.

Prof. Eng. Marcos Olandoski - M.Sc

[email protected]
Copyright 2015
 Contents

Chapter 1
Definitions
Counting Systems – Number Bases
Numeric bases - Definition and Conversion to Base 10
Integer Part
Fractional Part
Numeric Bases – Conversion from base 10 to any Base
Integer Part
Fractional Part
Bases Equivalence between Binary, Octal and Hexadecimal
Numeric Coding Systems
BCD Code – Binary Coded Decimal
Excess 3 Code
Gray Code – Cyclic Code
Converting a Decimal Number to Gray Code
Gray Code to Decimal Conversion
Bit, Byte, Word
ASCII Table
Digital Logic
Operations using Binary Numbers.
Sum Operation
Subtraction Operation
Binary Positive to Binary Negative Operation
Operation with Negative Numbers
Solved Problems
Problems to be solved
Chapter 2
Boolean algebra – Definitions and Theorems
Basic Definitions
Mapping and Function
Algebraic Operations
Boolean algebra Operations
Boolean algebra definitions
Switching Boolean algebra
 Boolean Formulas
Equivalence of Boolean Forms
Boolean algebra Theorems
De Morgan Theorem
De Morgan Theorem Extension
Algebraic operation - Exclusive OR (XOR)
Solved Problems
Problems to be solved
Chapter 3
Functions, Mappings, Standards Forms
Boolean Function
Functions Completely and Not Completely Specified
Completely Specified Function
Not Completely Specified Function
Solved Problems
Problems to be solved
Chapter 4
Logical Circuits using Relays
General
Conventional Relay
Bistable Relay – Magnetic Latching – Relay with Memory
Basic Definitions for Relay Circuits
Logic Circuits using Relays
Circuit with Intermediate Branch
Circuit to Power on and off Equipment
Auxiliary Relay Circuit
Solved Problems
Problems to be solved
Chapter 5
Karnaugh Maps
Maps Construction
Filling the cell values
Definitions and Cells Properties of the Karnaugh map
Visual Processing of Karnaugh Maps
Solved Problems
Problems to be solved
Chapter 6
Quine McCluskey Algorithm
Example – Algorithm for Sum of Products
Example – Algorithm for Product of Sums
Solved Problems
Solution type sum of products
Solution type product of sums
Problems to be solved
Chapter 7
Quine McCluskey Algorithm for Multiple Simultaneous Outputs
Functions
Example using Quine McCluskey Algorithm
Solution for Sum of Products
Solution for Product of Sums
Solved Problems
Problem 1: Solution Type Sum of Products:
Problem 1: Solution Type Product of Sums:
Problem 2: Solution Type Sum of Products:
Problem 2: Solution Type Product of Sums:
Problems to be solved
Chapter 8
NAND and NOR Circuits
Logic Gates
Sheffer Boolean Algebra
Definition: Sheffer Boolean Algebra
Postulate 1:
Postulate 2
Postulate 3
Postulate 4
Postulate 5
Verification of Postulates for NAND and NOR Operations
Postulate 1
Postulate 2
Postulate 3
Postulate 4
Postulate 5
Proof of not associativity of Operations │ e ↓
Analyzing Circuits with the Operations “Stroke” and “Dagger”
 Synthesis of Circuits using Operations “Stroke” and “Dagger”
Solved Problems
Problems to be solved
Chapter 9
Function Decomposition
Simple Disjunctive Decomposition
Propositions
Shannon expansion theorem
Application of Propositions in Sequence
Partition Tables
Final Considerations
Solved Problems
Problems to be solved
Chapter 10
Iterative Network
Iterative Network - 1 Dimension
Iterative Network – 2 dimensions
Typical use of Iterative Networks
Cells Generation Process
Example 1: Adder and Subtractor
Example 2: Gray Code to Binary Number Converter using Logic
Gates
Example 3: Parity Generation or Parity Verification using Logic
Gates
Example 4: Verification Number of Bits with Value 1 equal 3
Example 5: Verification of a bit value 1 after a minimum of 8 bits
value 0
Example 6: Gray Code to Binary Number using Relay Circuit
Example 7: Adder using Relay Circuit
Problems to be solved
Chapter 11
Transients and Hazards in Switching Circuits
Types of Hazards
Static Hazards
Dynamic Hazards
Circuits that present Static Hazards
Static 0 Hazard in logic gates circuit
 Static 1 Hazard in logic gates circuit
Static 0 Hazard in Relay Circuits
Static 1 Hazard in Relay Circuits
Dynamic Error Rising Edge – Logic Gates
Dynamic Error Falling Edge – Logic Gates
Dynamic Error Falling Edge – Relay Circuit
Dynamic Error Rising Edge – Relay Circuit
Detecting Static Hazards
Preventing Static Hazards using Karnaugh Maps
Preventing Static Hazards using Quine McCluskey Algorithm
Disjunctive Forms Theorem
Conjunctive Forms Theorem
Problems to be solved
Chapter 12
Threshold Gates
Ferrite Rings
Magnetic Core Memory – Ferrite Ring Memory
Two Levels Comparator – Schmitt Trigger
One Level Comparator
OR Operation
AND Operation
Inverter Operation
Comparator using Weighting Factors
Problems to be solved
 Chapter 1
Definitions
In this chapter it will be presented the initial definitions that enables
the development and use of mathematical methods and algorithms to
generate electronic and electro mechanics circuits in the digital electronics
area.

Counting Systems – Number Bases

Below is displayed a table with the count in Decimal, Binary, Octal
and Hexadecimal bases

Numeric bases - Definition and Conversion to Base 10

Setting the numerical basis on which is represented a number is
normally presented through an index at the end of the number (K). In the
case of base 10 because this is commonly used, it is not used in the index.
The example presents a number N of 4 digits with values A, B, C and
D using a numerical base K.
Integer Part
The example also shows the number converted to a value in base 10
using the definition of numerical base for Octal base (8).
Fractional Part
The next example shows a fractional number F represented by four
digits E, F, G and H using a numerical base K.
Also the number used in example is converted to a base 10 number
using the numerical base definition for fractional numbers, in this case
using the octal (8) number base.

In normal cases of numbers with integer and fractional parts simply

apply the definitions to the two parties in a single operation.

Numeric Bases – Conversion from base 10 to any Base

Integer Part
1) Binary Base
To convert a number presented in base 10 for binary base, the number
is divided successively by the number-value of the base, in the case number
2.
The remains of each division will form the new number at base 2.
These remains are read from right to left, starting with the rest of the last
division that results in a value 0.

So we have the number 237 in base 10 is equivalent to the number

11101101 in base 2.
2) Octal Base
To convert a number in base 10 for octal base, the number is divided
successively by the number-based value 8. The remains of each division
will compose the number in the base 8.
These remains are read from right to left, starting with the rest of the
last division that results in a value of 0.

So we have the number 237 in base 10 is equivalent to the number

11101101 in base 2.
3) Hexadecimal Base
To convert a number in base 10 to Hex base, base 16, the number is
divided successively by the value of the base 16.
The remains of each division will compose the number in base 16.
These remains are read from right to left, starting with the last remainder of
division that results in a value of 0 for the division.
The remains are represented in base 10. So you need to convert the
remains to the hexadecimal base according to the table at the beginning of
this chapter (Fig.1.1).

Fractional Part
1) Binary Base
To convert the fractional portion of a number in base 10 for binary
base, the fractional part is multiplied by the value of base 2.
When the value resulting number is greater than 1, the value 1
appears on the left side of the line separating the integer part of the
fractional part.
When the resulting number is less than 1, the value 0 appear on the
left side of the line.
The digits that are shown on the left side read from top to bottom will
make the fractional binary number.

So the fractional number 0.42578125 base 10 is equivalent to

0.01101101 fractional number in binary base, base 2.

2) Octal Base
To convert the fractional part of a number in base 10 to the octal base,
base 8, multiply successively the fractional part by the base value 8.
When the resulting number is greater than 1, a value appears
on the left side of the line that separates the integer part of the
fractional part.
When the resulting number is less than 1, the value 0 appear on the
left side of the line.
The numbers that are shown on the left side read from top to bottom
will make the fractional octal number.
 So the fractional number 0.42578125 base 10 is equivalent to the
fractional number 0.332 in octal base, base 8.

3) Hexadecimal Base
To convert the fractional part of a number in base 10 for hexadecimal
base (16), multiply successively the fractional part of the number by the
base value 16.
When the resulting number is greater than 1, a value appears on the
left side of the line that separates the integer part of the fractional part.
When the resulting number is less than 1, the value 0 appear on the
left side of the line.
The numbers that are shown on the left, read from top to bottom will
make the fractional hexadecimal number.
These figures are represented in base 10 and must be converted to
hexadecimal base using the table presented at the beginning of this chapter
(Fig.1.1).

So the fractional number 0.42578125 base 10 is equivalent to the

fractional number 0,6D in hexadecimal base, base 16.

Bases Equivalence between Binary, Octal and Hexadecimal

The calculations presented in the previous two sections resulted in the
following results for the integer and fractional parts for the 237.42578125
number in base 10.
 If the number in binary base, base 2 is separated every four digits and
each group of four digits is converted according to the table presented at the
beginning of this chapter (Fig.1.1) we will have the number in binary base
converted to hexadecimal base, base 16 directly.

If the number in binary base(2), is separated every three digits and

each group of three digits is converted according to the table presented at
the beginning of this chapter (Fig.1.1) we will have the number in binary
base converted to the octal base, base 8 directly.

If the number in octal base (8), has each of its digits replaced by three
binary digits according to the table presented at the beginning of this
chapter (Fig.1.1), we will have the number in octal base directly converted
to binary base (2).

If the number in hexadecimal base (16) has each of its digits replaced
by four binary digits according to the table presented at the beginning of
this chapter (Fig.1.1), we will have number in hexadecimal base directly
converted to binary base (2).

So, it was demonstrated that there is a direct equivalence between the

bases octal and hexadecimal and binary base.
Most of the representations of binary numbers in displays, screens
and printers use the hexadecimal or octal format.
People who work with computer or digital electronics have the
conversion table 0-15 memorized.
Numeric Coding Systems
BCD Code – Binary Coded Decimal
The BCD code uses a binary number with four binary digits to encode
the numbers 0-9 represented in decimal base.
When the BCD code is used to represent the decimal digits the binary
numbers from 10 to 15 is discarded. The efficiency of the binary coded
decimal number is less than the efficiency from direct binary encoding,
since the numbers above 9 are not used.

Example of BCD encoding:

The 9537 number in base 10 is represented by four binary numbers with 4
binary homes each.

Excess 3 Code
While the BCD code uses binary numbers from 0 to 9 to encode 10
decimal digits, the 3 Excess Code begins to encode the digit 0 from the
number 3. That is the equivalent value of the binary number with the value
3 subtracted.
This code has two important features. The first is that all decimal
numbers encoded in 3 Excess Code always has one digit with value 1 in the
coding. Second a transmission using numbers decimal encoded using
Excess 3 code, balance the number of 0s and 1s in the sequence of
transmission, since the balance the numbers decimal encoded are also
balanced.
This can be observed by the existing symmetry between binary
numbers in the table presented.
Gray Code – Cyclic Code
The Gray code is the best known of cyclic codes. The cyclic codes
have the property that only a binary digit changes between two lines of the
table. Also in cycle codes the first line is adjacent to the last row of the table
The following is a table of the Gray code using 4 binary digits.

The cyclic codes were developed to be used in position encoders. For

example, in a rotary position encoder, a disc with several circles containing
translucent or opaque bars, encode binary numbers, where each concentric
circle, represents a bit of binary number. When the shaft undergoes rotation
reading 0 or 1 of each concentric circle composes the numerical absolute
position of shaft rotation.
Using the Gray code, there will never be a position where an
uncertainty occurs, i.e. where you can not accurately determine the correct
absolute number. The maximum that will occur will be the indeterminacy
between two adjacent numbers.

Converting a Decimal Number to Gray Code

In order to realize the conversion of a decimal number to Gray code,
first it is necessary to convert the number to binary code.
Example: Convert the number 47 represented in decimal base to a number
represented in Gray code. First the number is converted to binary
base.

Next is used the table below to perform an operation called Exclusive

OR.

Initially it adds to the left side an extra digit to the binary number
with 0. Then it is applied the operation called Exclusive OR presented in the
above table, starting from the left and moving right. The + symbol with an
external circle is the Exclusive OR operation.

So the number 47 in base 10 is represented by the number 111000 on

Gray encoding.
Gray Code to Decimal Conversion
The conversion of the numbers represented in Gray code to numbers
in decimal base begins with the number in Gray code to binary.
The operation is performed from left to right.
The process starts with a binary 0.
When the digit in the Gray number displays the value 1 the value in
relation to the digit already calculated is reversed. So if we have a value of
1 for the first digit represented in the Gray code, the new binary digit will
be 1. So the next house number in binary is 1. As in the case the next house
in Gray is also one the next house will be a binary 0. Continuing to the next
house in Gray is also one so the next binary digit is 1. Like the other Gray
digits are 0 the value 1 remains the same until the end of the process.
To finish the process, the number in binary is converted to base 10
according to the calculations presented earlier this chapter.

Bit, Byte, Word

A number that consists of 8 binary digits is called Byte.
This number may represent equivalent numbers in decimal base from
0 to 255. Or if you want to work with positive and negative numbers it will
display numbers 0-127 positive and negative -1 to -128.

Each one of the binary digits that makes up a byte is called Bit. The
lower digit, i.e. the binary digit at the right place is called the Least
Significant Bit (LSB - Less Significant Bit) and the digit at the left place is
called the Most Significant Bit (MSB - Most Significant Bit).

If we divide the byte into two parts with 4 binary digits each part,
each part with of 4 binary digits is called Nibble.
The two Nibbles are called most significant and least significant
nibble.

Structures composed of more than one byte, are called Word. The
term Word is generic, does not automatically specifying the number of
bytes that comprise it.
Then it must be specified. For example: 16-bit word or two bytes, 32-
bits word, 64-bits word. Usually the Word term is specified in number of
bits.
 The concept of Word is more associated with physical structures like
number of wires connecting a processing unit to its memory, or the number
of bits that an instruction of a computer uses.

ASCII Table
The ASCII (American Standard Code for Information Interchange)
called American Standard Code for Information Interchange is a standard
for encoding letters, numbers and special symbols in a byte.
This table originally standardized to use in teletype, also has a section
of typical command and control characters for such equipment.
When the advent of computers, this table continued to be used.

Following this table presented showing the values of the bytes in

decimal, hexadecimal, and binary.
Digital Logic
Digital circuits use binary logic as the basis of its operation. This
binary number is associated with a physical logic level as 0 Volts or +Vcc.
Most digital logic circuit operates on the basis of DC voltage levels.
That is, assuming the circuit fed with a specific DC voltage, say +5 Volts
DC, the 0 logic level is associated with the value of continuous 0 Volt and
the logic 1 is associated with the value of +5 Volts DC.
As the level 0 is associated with the lower value of the supply
voltage and the level 1 is associated with the higher value of the supply
voltage, we affirm that we are using positive logic.
There are also circuits in which the logical 0 and 1 levels are
associated with the flow direction of a direct current. In this case you must
set the current flow direction with respective to the input or output of an
electrical circuit.

Operations using Binary Numbers.

Sum Operation
The operation sum of two decimal numbers is performed according
to, as shown below:

The numbers A and B are added a numerical step at a time, starting

with the most right digit and progressing to the most left digit.
When we add 8 + 3 we have the result 11, i.e. the lowest significance
digit has the value 1, but the result was 11 then the second digit having a
value of 10 has to be added with a value of 1 to the next digit at left.
This value is indicated by the value 1 at the line Carry n, which
means that the value 1 must be added to the digit with more significant
value.
This value is transferred to the Carry line (n-1) which is positioned in
the next column over the left. In the next column operation we have to add
the three values 1+4+9 that will have the result 14 or again, the sum is 4 and
the line n Carry must register the 1 value to be added in the next column
over the left.
This value 1 is transferred to carry line (n-1). Operating the leftmost
column we will have the sum of 1 + 3 + 4 which will have the result 8 and
the value 1is registered in line Carry n equal to 0.

To perform the binary sum, the same method is used. The operation
begins with the rightmost digit and progresses to the digits over the left.
The first rightmost column performs the operation 1 + 1 = 10, i.e. the
line sum of the column is assigned the value 0 and n Carry line receives the
most significant value of 1.
This value of n Carry line is moved to the leftmost column in the line
Carry (n-1). The sum of the following next left column performs the
following operation 1 + 1 + 1 = 11, i.e. the sum of the column line is
assigned the value 1 and the line n Carry receives the most significant value
of this sum.
This value of n Carry line is moved to the leftmost column in the row
Carry (n-1). The sequence is repeated until the last digit from the left is only
the value 1 on the line Carry (n-1) resulting in a value 1 for sum line and the
value 0 to line n Carry.

Subtraction Operation
The operation subtraction of two decimal numbers is performed
according to shown below:
 The numbers A and B are subtracted one digit at a time, starting from
the most right digit and progressing to the most left one. When we subtract
8 -9 we have a negative result, then to avoid this problem we add 10 to the
number A resulting 18 to the digit rightmost number A, so the result is 18-9
= 9. But we have to indicate that it was borrowed(borrow) one value over
the left digit i.e. the equivalent of 10 because the next digit is the tens. This
value is indicated at the Borrow line n, which means it was recorded that
the value 1 will be considered when the operation takes place in the more
significant digit. This value is transferred to Borrow line (n-1) which is
positioned next leftmost column.
In operation following the leftmost column we must add the value 1
presented at Borrow(n-1) line to the value of Number B line in the case of
value 7 that will be considered as 7 + 1 = 8.
So the operation to be performed will be 4-8 that will result in a
negative number. Again we turn to the previous procedure, borrowing the
value 1 from the following leftmost column representing value 100. Then
the result of the operation will be 14 - (7 + 1) = 14-8 = 6.
As again it was borrowed one of the hundreds column, we recorded
this amount in Borrow line. This value is transferred to the next column
Borrow (n-1).
Then the last leftmost column is operated. We add the value 1 present
at Borrow line (n-1) to B number column digit that will have the value (3 +
1) = 4.
Then the operation will be performed as 5- (3 + 1) = 1, which is
registered in the Difference line. In this case there was no need to borrow 1
from the leftmost column and the operation is finished.
 To perform subtraction using binary numbers the same method is
used. The operation begins with the most right digit and progresses to the
over the left one. The operation is performed at first right-most column,
which results in a negative number. So we borrow 10 (2 in decimal) from
the left column. Then we perform the subtraction 10-1 = 1 resulting in a
value 1 in binary. A 10 value was borrowed from the next leftmost column.
The resulting value 1 is recorded in the Difference line. The amount
borrowed is recorded in Borrow n line and transferred to the next column
on the left Borrow line (n-1).
The next column difference performs the operation 1 - (1 + 1) because
the number of Borrow line (n-1) is added to the digit of number B. This
number will result in a negative number. So we repeat the previous method
borrowing one of the leftmost column.
Then the operation to be performed is:
11- (1 + 1) = 11-10 = 1. This value 1 is recorded in the Difference line and
the value 1 borrowed from the leftmost column is recorded in Borrow line
n.
This value of n Borrow line is moved to the leftmost column in
Borrow line (n-1). In this third column the number 1at line Borrow (n-1) is
added to digit of number B which will result in (1 + 1) = 10.
This number should be subtracted from the value 0 that is the digit of
number A in this column.
As the result will be negative a value 1 is borrowed from the next
column to the left. So we will have the operation 10-10 = 0 which is
registered in line difference in this third column and record the borrowed
value in line Borrow n.
The value of Borrow line n is transferred to Borrow line (n-1) that
belongs to the next column to the left. In this last column the digit of
number B has value 0 and the borrow value is added resulting in (0 + 1) =
1.
 Then the operation will be 1-1 = 0 which is registered in the column
Difference line. As in the operation of this column nothing was borrowed,
the operation ends.
The operation subtracted the decimal value 7 from the decimal value
10, resulting in the equivalent decimal difference 3.

Binary Positive to Binary Negative Operation

To convert a positive number to a negative number with the same
value the following operation is performed:
a) Invert the value of each binary digit.
b) Sum the value 1 to the number generated by the inversion of the value of
all digits.
This new number will have at the leftmost digit the value 1, indicating that
it is a negative number.

To check whether the number generated by the previous operation is

actually the same number with a minus sign, we conducted an operation
that add the original positive to the negative number generated.
We find that the result is the number 0.

To convert a negative number to a positive number with the same

value the following operation is performed:
a) Invert the value of each binary digit.
b) Sum the value 1 to the number generated by the inversion of the value of
all digits.
This new number will have at the leftmost digit the value 0, indicating that
it is a positive number.
 So we can present a table with the positive and negative binary
numbers with four binary places:

Operation with Negative Numbers

To accomplish the sum of a positive number to a negative number, or
perform a subtraction of two binary numbers, simply convert the number to
be subtracted to a negative number and perform the operation amount
normally.
To add two negative numbers, just convert both numbers to negative
and make the operation sum normally.

Solved Problems
1) Convert the number183 base 10 to Gray encoding.
Solution:
Initially the number 183 in base 10 is converted to binary base,
resulting in the number 10 110 111 in base 2.
 Next is applied the Exclusive OR operation between the binary digits.
At the beginning of the operation a digit with value 0 is added at the left
side of the binary number.

So the end result is 11101100 Gray encoding.

2) Convert the number 110 011 101 Gray coding for the equivalent number
in base 10.
Solution:

The process starts with a binary 0. When the digit number in Gray
displays the value 1 the value calculated in relation to the previous bit is
reversed. So if we have a value of 1 for the first bit of the number
represented in the Gray code the next digit in binary will be 1. If the next
digit in Gray has value 1 the next digit will be inverted in binary value with
respect to the previous digit, and will present the value 0.
The next bit in Gray has value 0 so the next binary number will stay
with the previous value 0. Continuing the next digit in Gray is also 0 so the
next binary house will continue with value 0. As the following three digits
in Gray have value 1 binary we will have the values 1, 0 and 1. The digit in
Gray has value 0 then the binary digit will maintain the value 1.
The last bit in Gray has value 1 the binary number will be 0.
So the binary number will be set to 0100010110
 Converting the binary number for the base 10 by applying the values
of each binary to all binary digits that have value 1 the result will be 278
base 10.

3) Convert 37.40625 in decimal base to binary and octal bases.

Solution:
First convert the integer part:

Then convert the fractional part:

Finally we gather the integer part with the fractional part:

4) Convert the numbers given to the base 10:

1011.1011 Base 2 - Binary
75.34 Base 8 – Octal
AC.7D Base 16 - Hexadecimal
 Solution:

5) Convert directly from octal base to hexadecimal base

Solution:

6) Convert the numbers of operations below from base 10 to binary base 2.

Perform the requested operations on the base 2. Then the result is converted
to base 10.
X=25+39
Y=35-23
Solutions:
First it´s necessary to convert the numbers to base 2.
Then operations are performed in the base 2

The number 23 in binary base is converted to negative.

The sum is performed on the base 2

The result is converted to base 10.

Problems to be solved
1) Convert numbers represented in the data base 10 to base 2 (binary), 8
(octal) and 16 (hexadecimal)
233
-17
-173
83.34
27.17
57.22
107.25

2) Convert the numbers given on various bases to base 10

3) Assuming a system that uses 16-bit word. BCD is the notation for
representing the decimal numbers. Present the data, using 2 bytes for the
following decimal numbers:

1376
9276
3410
8578

4) For the following operations presented in decimal notation, convert the

numbers to binary notation, perform operations using binary base and
finally convert the results to base 10.

12+ 47
57+137
125+342
25.23 + 37.45
32.987 + 134.87
174 - 87
237 -123
47.34 – 23.17

5) Perform the operation 2110 - 2710 using binary.

a) Performing normal subtraction operation using the base 10.
b) Converting the number 27 in binary to a negative number and performing
a binary sum.
For both a) and b) convert the final results in binary to base 10 and compare
the results.

6) Convert the numbers presented in the base 10 to Gray code

73
125
237
1398
3734

7) Convert the numbers presented in Gray notation to base 10

representation.
10011101011
11100001
11010111
11011101110
 Chapter 2
Boolean algebra – Definitions and Theorems

Considering the definition given of positive logic in the previous

section, that is the assertion that the positive voltage level corresponds to
the binary number 1 and the voltage level 0 corresponds to the binary
number 0, it is introduced the concept of a switching combinational circuit
as a logic circuit receiving a set of entries a, b, c, etc.., and present at its
outputs x, y, z, etc.., binary results 0 or 1, that depends only on the amount
invested in its entries at this point.
I.e. a switching combinational Boolean circuit doesn’t have a
memory that can interfere in the result, presented by its output at this time,
Also the sequence of values presented in its inputs will not influence the
future results shown in its outputs.

Basic Definitions

Definition: A set C is a collection of objects.

For example assuming a, b, c k… are objects, the set C containing
these object can be expressed by:
C={a, b, c,.....k}
The values that can take these elements are contained in the set:
B={0,1}
Definition: Each object of a set C is an element.
The number of elements of a set can be finite or infinite.
For example the number of elements that compose the set C= {a, b, c,
d, e, f, g, h, i, j, k} is finite.
The set of integer numbers is composed of infinite elements.

Definition: A set M= {a, c, f} is a subset of the set C= {a, b, c, d, e, f, g, h,

i, j, k,} if and only if all elements of M is also an element of set C.
This definition can be expressed by the mathematical expression:
 Using the presented definitions it is possible to analyze the example
of sum operation already presented in the previous chapter.
In this operation a and b are the entries that represent a column of the
numbers A and B.
The variable c is an entry that represents the “carry (n-1)” for the same
column of the numbers A and B.
s is the output which is the result "sum" of the operation for the
column being calculated and c n is the "Carry n 'resulting for the column
being calculated.

So the inputs are represented by:

E=(a, b, c (n-1))
And the outputs are represented by
S=(s, cn)
So we can say that the entrance set E to the adder is composed of an
ordered pairs s on the set B= {0, 1}.
E=(a, b, c(n-1))
The term "ordered pairs " indicates that there is an order in the presentation
of the values for the entries
So when it is said that it will be applied in the entry the element
{e6=1, 1, 0}, it is assumed that a will receive the value 1, b will receive the
value 1 and “c (n-1)” will receive the value 0.
The same applies to set S. When it is said that result of the circuit will
be the element {s1=0, 1} it is assumed that s will present a 0 value and c n
will present a 1 value.
Using the definitions presented it is possible to look at the example of
the subtraction operation already presented in the previous chapter.
In this operation a and b are the entries that represent the columns of
numbers A and B.
 Borrow (n-1) is the entry that represents “Borrow (n-1)” for the same
column.
The variable d is the output that represents the result of “difference”
and borrows n represents “Borrow n” that results for the column that is
being calculated.

So the inputs are represented by:

E= (a, b, borrow (n-1))
And the outputs are represented by:
S= (d, borrow n)
So it can be said that the entrance for the subtraction operation is
composed by an ordered pairs on the set B= {0, 1}.
E= (a, b, borrow (n-1))
The term "ordered pairs " indicates that there is an order in the
presentation of the values for the entries.
So when it is said that it will be applied in the entry the element
{e1=0,0,1}, it is assumed that a will receive the value 0, b will receive the
value 0 and borrow (n-1) will receive the value 1.
The same applies to the set S. When it is said that result of the circuit
will be the element {s3=1, 1} it is assumed that d will present a 1 value and
borrow n will present a 1 value.
Based on the definitions and explanations above it is possible to
define "input symbol" and "output symbol."

Definition: In a switching Boolean algebra for a combinational circuit the

“input symbol” is an ordered pairs over the set B{0,1} that is applied to the
entries of the circuit. The set of all inputs symbols are called input alphabet.
So for the case of adder the output alphabet is composed by the ordered
output symbols on the set B {0,1}:
Definition: In a switching Boolean algebra for a combinational circuit the
“output symbol” is an ordered pairs over the set B {0, 1} that results in the
outputs of the circuit when an input symbol is applied to its entries. The set
of all output symbols are called output alphabet.
So for the case of adder the output alphabet is composed by the
ordered output symbols on the set B {0,1}:

Definition: A digital circuit is said to be combinational if its output symbol

presented in its outputs at a given time is determined solely by the input
symbol applied to its entries at this moment.
This concept has already been presented at the beginning of this
chapter, but is again presented using the concepts of symbols already
defined.

Mapping and Function

The concept of digital combinational circuit requires a direct

relationship exists between the application of an input symbol in the circuit
and the output symbol that result in its outputs.
So we can present the following definition:

Definition: Are two set S1 and S2. The association for every element of S1
to one and only one element of S2 is a mapping from S1 to S2 also called
“True Table”. The mapping is also called “Function”.
The mappings for sum and subtraction functions are shown below:
Another way of presenting a function:
Assuming a set C1 composed of the elements (0,0), (0,1), (1,0) and (1,1)
and a set composed by elements C2 (0) and (1)

Algebraic Operations

Let’s analyze the combinational circuit below. It contains entries b

and c and an output s. The input symbols are characterized by (b, c) and the
output symbols by (s).
The input and output symbols are defined over the set B= {0, 1}.

The input alphabet is given by:

E={e0=(0,0), e1=(0,1), e2=(1,0), e3=(1,1)}
The output alphabet is given by
S={s0=(0), s1=(1)}
Assuming the map below, for the operation it will be called duo.
 The mapping specifies an association between the input symbols, as
ordered pairs with 2 entries defined over the set B={0. 1} to a set of output
symbols, as ordered pairs of a single output also specified over the set B=
{0, 1}. This function is called algebraic operation.
As can be seen, the algebraic operation can be presented in the form
of mapping or as a table with an entry in the horizontal line and another
input on the vertical line.

Definition: Let D be any set. An algebraic operation on D is a D x D

mapping to D.
Let us assume that D = set {- 1, 0, 1}
The mapping specified below over
D = {- 1, 0, 1} that will be called Tri operation is an algebraic operation.

In the following definitions a generic algebraic operation will be

called #.

Definition: The algebraic operation # over a set D is commutative if and

only if:
If the verification of commutation is performed for a mapping is
necessary to conduct a comprehensive operation for all mapping lines.
 If the operation is represented by a table, simply check that the
operation is symmetrical relative to the main diagonal of the table.
It can be observed that the Duo operation is symmetric relative to the
main diagonal.
However the Tri operation has no symmetry relative to the main
diagonal, as shown below:
1 Tri 0 ≠ 0 Tri 1

Definition: An algebraic operation over a set D is associative if and only

if:
The parentheses indicate the order of execution:

In the case of Duo operation it is demonstrated the associative to the

operation:

(0 duo 0) duo 0 = 0 duo (0 duo 0) = 0

(0 duo 0) duo 1 = 0 duo (0 duo 1) = 1
(0 duo 1) duo 0 = 0 duo (1 duo 0) = 1
(0 duo 1) duo 1 = 0 duo (1 duo 1) = 0
(1 duo 0) duo 0 = 1 duo (0 duo 0) = 1
(1 duo 0) duo 1 = 1 duo (0 duo 1) = 0
(1 duo 1) duo 0 = 1 duo (1 duo 0) = 0
(1 duo 1) duo 1 = 1 duo (1 duo 1) = 1

For tri operation we can observe that:

(1 tri 0) tri 1 = 0 tri 1 = -1

1 tri (0 tri 1) = 1 tri -1 = 0
Then the Tri operation is not associative.

Boolean algebra Operations

Analyzing a table that represents a combinational circuit with only

one entry and one output, called Unary operation, it can be observed that for
this situation only four possibilities exist.
Two are known as constant as the result in the output independent of
the input value.
One is known as identity because the output presents Always the
same value that is presented at the input.
The last one is called an inverter, since the output always presents a
value opposite of the value that is presented at the input.
Below are presented the tables for the four Unary operations. Also for
the Unary operations type identity and inverter the logical symbols are
shown.

Identity Unary Operation Symbols

Inverter Unary Operation Symbols

 Now it will be presented all algebraic operations composed of two
inputs (a, b) and one output (s).
The operations that present a result that has symmetry relative to the
main diagonal are commercially manufactured.
Operations that the output results are not symmetrical relative to the
main diagonal are considered non-standard.
Operations that result in value 0 or 1 for all input possibilities are
called constant.

So the commonly used operations are OR, NOR, Not, AND, NAND,
XOR, XNOR, which are symmetric relative to the main diagonal and are
commutative.
Below are presented the symbols for all the standard operations with 2
inputs.
Boolean algebra definitions

The Boolean algebra is a mathematical system, whose name pays

tribute to George Boole, and is defined as followed:

Definition: A set B= {0, 1} along with two algebraic operation + (OR) and
. (AND), plus the operation “Unary inverter”, is a Boolean algebra, if and
only if the following postulates are true:

Postulate 1: The operations “+” and “.” are commutative and associative.

Postulate 2: There are different elements represented by symbols 0 and 1

respectively, such that:
 The symbol 0 is called the identity element for the operation “+” and
the symbol 1 is called the identity element for the operation “.”.

Postulate 3: Each one of both operation “+” and “.” are distributive over
one another and vice versa:

Postulate 4: For every element “a” in B exists an

Switching Boolean algebra

It was already established that the logical level 1 corresponds to the

value of power supply voltage, that is positive, and that the logic level 0
corresponds to the voltage value 0.
So the B= {0, 1} set is associated with these two physical conditions.

Theorem: The set B= {0, 1} together the two operations “+” and “.” as
defined below, plus the operation “Unary inverter”, are a switching Boolean
algebra.
.
 Both operations are commutative and associative.
The following statements are valid for both operations.

The identity element for the operation “+” is 0 and the identity
element for the operation “.” is 1.
The operations “+” and “.” are distributive over one another and vice
versa, i.e. satisfy the following statements:

called complement element of a.

Then analyzing the operations “+”, and “.” It is possible to verify that the

following is true:
Switching Boolean algebra is essential in the design and optimization
of switching circuit studies.

Boolean Formulas

While the mapping or the truth table is a true and complete

representation of the function, this type of representation is not an algebraic
manner of representation.
Boolean forms are a means of representing algebraically switching
Boolean functions.
 There are numerous ways of Boolean forms representing the same
Boolean function displayed on a map.
So we can say that the digital Boolean form is not the function but
one of many ways of representing the function.
I.e. the Boolean form results in a mapping that represents the
function.
Following is presented some definition for the correct generation of
switching Boolean forms.

Definition:
A symbol x is a variable if it can represent any of the values of
switching Boolean algebra B= {0, 1}.
The variable value is the element of B= {0, 1} that the variable is
representing.
So the variable x can take the value 0 or the value 1.

We can express this definition through a table:

To be able to develop Boolean expressions that represent the function,

the following rules must be followed:

Definition: An algebraic expression is a Boolean expression if and only if it

is obtained according to the following rules:
a) A variable xi, I =1, 2, 3,..., k is a Boolean form.
b) The elements 0 and 1 of set B= {0,1} are Boolean forms.
c) If F1 e F2 are Boolean forms then:
are Boolean forms.

Definition: The complement of a Boolean

that always has the complement value of F for any value that the variables
that composes it take and vice versa.

Definition: The value of a Boolean form is the element of the set B = {0, 1}
it is when the values of the variables that compose it are known.
An example is shown by the following table for F and its complement
function.

Then using the mapping for the functions AND the intermediate
values are calculated.

Finally the mapping for the function OR is applied and the values of F
are calculated.

At least using the Unary operation inverter the values for the

complement of F are calculated.

Equivalence of Boolean Forms

Having two different Boolean forms representing the same function F

it is possible, using the principles of the switching Boolean algebra and
further the properties of the functions AND and OR algebraically verify that
both forms represent the same function and mapping.

Definition: Two switching Boolean forms are equivalent if they describe

the same digital function.
Using the mapping for the function F presented in the previous
definition it’s possible to extract from the mapping two different Boolean
forms F1 and F2.

Developing the Boolean form F2 using the distributive property of

Boolean algebraic operations OR and AND, and P4 postulate which states
that:
And P2 postulate which states that:
a + 0= a and a . 1 = a
it is obtained:

Finally using a not yet proven theorem which states that:

It is obtained:

i.e. the two Boolean forms F1 and F2 are equivalent.

Boolean algebra Theorems

Theorem 1
For any element of a Boolean Algebra B the following is true:

Proof:
Starting with the first Boolean expression (1):

Now proving the second Boolean expression (2):

Theorem 2: For any element of a Boolean Algebra B the following is true:

Proof:
Starting with the first Boolean expression (1):

Now proving the second Boolean expression (2):

Theorem 3: For any element of a Boolean algebra B the complement of the

element a

Proof:
Let’s assume the opposite, i.e. let’s assume that

Satisfy the Postulate P4. So:

Using the Postulates and the hypothesis from (1) to (4):

Theorem 4: In a switching Boolean algebra each of the identity elements 0
and 1 are unique.
Proof: First let’s assume that there are two elements 0 written 01 and 02
For any elements a and b the following is true:
a+01=a and b+02=b
Assuming a=02 and b=01 and using Postulate P1 results:
02 + 01 = 02 and 01 + 02 = 01
01 + 02 = 02 and 01 + 02 = 01

Then: 01=02
Following, let’s assume that there are two elements 1 written 11 and 12
For any elements a and b the following is true:
a.11=a and b.12=b
Assuming a=12 and b=11 and using Postulate P1.
12 . 11 = 12 and 11 . 12 = 11
11 . 12 = 12 and 11 . 12 = 11
Then:
11 = 12

Theorem 5: In a switching Boolean algebra each of the identity elements 0

and 1 are complements of each other and vice versa.
Proof: By the previous theorem for the element complement 0.

Using Postulate P2

Now let’s assume that a=0. Then:

Using Postulate P4

Continuing, let’s assume

By Postulate P2:

Now let’s assume that a=1

Theorem 6: For every element a in a switching Boolean algebra there is an

element complement
Then:

Theorem 7: For any elements a and b of a switching Boolean algebra, the

following is true:

Proof: Initially for part (1):

Following part (2):

Theorem 8: For any elements a and b of a switching Boolean algebra the

following is true:
Proof: First part (1):

Following part (2):

Theorem 9: For any elements a and b of a switching Boolean algebra the

following is true:
Proof: First part (1)

Following part (2):

Theorem 10 -
De Morgan Theorem (Augustus De Morgan)
For any elements a and b of a switching Boolean algebra the following is
true:

Proof: For any theorem it is necessary to prove that x=y it is used theorem
3 that proves the complement of an element is unique and Postulate P4
which states that:

Then if it is proved:

Then: x=y.

So for Morgan’s theorem simply prove that:

First part (1):

And

Following part (2):

And
Theorem 11 –
De Morgan Theorem Extension:

First part (3):

It can be observed that each term has a pair type:

This will result in a value of 0 in accordance with postulate P4. As the

result will be a sum of 0s the final value for this part is 0.
Then further to part (3):

It can be observed that each term has a pair type:

This will result in a value 1 according to the P4 Postulate P4. As the

end result will be a product of terms with value 1, the final expression will
have the value 1.

Initially for the part (4):

It can be observed that each term has a pair type:

This will result in value 0 according to the Postulate P4. Then the
result will be an expression type sum of terms with value 0. The sum of
terms with value 0 results in an outcome with value 0
Next for the part (4):
It can be observed that each term has a pair type:

This will result in value 1 according to the Postulate P4. As the end
result will be a product of terms with value1, the end result for expression
will be the value 1.
So it is proved that the Morgan's theorem is also valid for extended
expressions.

Theorem 12: In any switching Boolean algebra, each of the + and .

algebraic operations are associative. So for all elements a,b and c the
following is true:
a+(b+c)=(a+b)+c (1)
a.(b.c)=(a.b).c (2)
Proof: Initially for part (1):

Replacing:

Replacing w and v

Then further for part (1):

Replacing w and v:
Replacing w and v:

Initially for part (2):

Replacing w and v:

Then further for part (2):

Replacing w and v:
Replacing w and v

Thus it was proved that the operations + and . are associative and that the
Boolean expressions can be written without the use of parentheses.
a+b+c=a+b+c
a.b.c=a.b.c

The fact of the OR and AND operations are associative allows the
expansion of OR gates and E multiple entries numbering more than 2.
Usually integrated circuits are manufactured with 2,3 or 4 entries for these
Boolean algebraic operations.

With respect to algebraic operations NAND and NOR, the expansion

of OR and E gates multiple entries allows the addition of an inverter on the
gate output as a single circuit resulting in integrated circuits with 2, 3 and 4
inputs for operations NANE and NOR.
 The mappings for algebraic operations AND, NAND, OR and NOR
for the extended functions are presented below:

Algebraic operation - Exclusive OR (XOR)

It will be analyzed the operation Exclusive OR (XOR) and the

operation Exclusive NOR (XNOR)
 Algebraic switching Boolean algebra XOR and XNOR operations are
not included in the postulates and theorems.
So we will have to analyze its operation in more detail.
Initially we can observe that when shown in table form in vertical and
horizontal lines, the values in the s output are symmetrical with respect to
the main diagonal.
This fact assures us that these two operations are commutative.
The symbol representing the operation Exclusive OR is
Now it will be demonstrated the associativity property for exhaustion.
First for the XOR operation:

Operation XNOR does not have its own symbol being represented by
the XOR operation with the reverse signal on its top.
 Following it will be demonstrated the associativity property for
exhaustion:

The circuits below demonstrates the associative property according to

the demonstrated.

From the operation represented by mapping it can be expressed the

form of representation of the operation using functions AND, OR and
inverters.

That is, when a=1 and b=0 there is 1. Also when a=0 and b=1 the
result is 1.
For XNOR operation the form is:.

That is, when a=0 and b=0 there is 1. Also when a=1 and b=1 the
result is1.
The XNOR operation has the values at the output s opposites to the
values of XOR operation.
Other possibility of representing the operations XOR and XNOR are
as:
Solved Problems

1) Show that the NAND operation meets all the requirements of digital
Boolean algebra.

Solution:
To demonstrate that an operation meets all requirements of a
switching Boolean algebra it is necessary to show that this operation is
capable of performing the operations Inverter, AND and OR.

If it is established that b=a, the result is:

Applying Theorem 1 result:

Thus joining the two inputs of NAND operation, the circuit will
execute the inverter operation.

b) If it is applied an inverter to the output of NAND operation, the circuit

will execute the AND operation.

Applying theorem 6 results:

So:

So adding an inverter to the output of NAND operation, two inverters

exist, then the NAND operation is converted in an AND operation

c) If it is applied the De Morgan Theorem to an OR operation it will result:

So it was demonstrated that using only the operation NAND it is

possible to perform the operations Inverter, AND and OR.

2) Show that the NOR operation meets all the requirements of digital
Boolean algebra.

Solution:
To demonstrate that an operation meets all requirements of a
switching Boolean algebra it is necessary to show that this operation is
capable of performing the operations Inverter, AND and OR.

a) If it is established that b=a the result is:

Applying Theorem 1 result:

Thus joining the two inputs of NOR operation, the circuit will execute
the inverter operation.

b) If it is applied an inverter to the output of NOR operation the circuit

will execute the OR operation.

Applying theorem 6 results:

Thus:

So adding an inverter to the output of NOR operation, two inverters

exist, then the NOR operation is converted in an OR operation

c) If its applied the De Morgan Theorem to an AND operation it will result:

Thus it was demonstrated that using only the operation NOR it is

possible to perform the operations Inverter, AND and OR.

Problems to be solved
1) For the presented circuit provide the performed Boolean formula and
show the mapping for s.
Is the mapping for s extension of any algebraic operation for 2 inputs?

2) For the presented circuit provide the performed Boolean formula and
show the mapping for s.
Is the mapping for s extension of any algebraic operation for 2 inputs?

3) For the two presented circuits provide the performed Boolean formulas
and shows the mappings for s1 and s2
Are s1 and/or s2 extension of any algebraic operation for 2 inputs?

4) For the two presented circuits provide the performed Boolean formulas
and shows the mappings for s1 and s2
Are s1 and/or s2 extension of any algebraic operation for 2 inputs?

5) For the three presented circuits provide the performed Boolean formulas
and shows the mappings for s1, s2 and s3
Are s1, s2 and/or s3 extension of any algebraic operation for 2 inputs?
6) For the three presented circuits provide the performed Boolean formulas
and shows the mappings for s1, s2 and s3
Are s1, s2 and/or s3 extension of any algebraic operation for 2 inputs?

7) For the three presented circuits provide the performed Boolean formulas
and shows the mappings for s1, s2 and s3
Are s1, s2 and/or s3 extension of any algebraic operation for 2 inputs?

8) For the three presented circuits provide the performed Boolean formulas
and shows the mappings for s1, s2 and s3
Are s1, s2 and/or s3 extension of any algebraic operation for 2 inputs?

9) For the two presented circuits provide the performed Boolean formulas
and shows the mappings for s1 and s2
Are s1 and/or s2 extension of any algebraic operation for 2 inputs?
10) For the two presented circuits provide the performed Boolean formulas
and shows the mappings for s1 and s2
Are s1 and/or s2 extension of any algebraic operation for 2 inputs?

11) For the presented circuits provide the performed Boolean formulas and
shows the mappings for s
Is s extension of any algebraic operation for 2 inputs?

12) Prove that a circuit that performs the given Boolean function is a
universal circuit i.e. it is possible to perform any Boolean operation using

one or more of the given circuit.

13) For the presented circuits provide the performed Boolean formulas and
shows the mappings for s
Is s extension of any algebraic operation for 2 inputs?
14) Let T= {a, b, c} is a set of three elements.
How many commutative and associative algebraic operations can be
defined on T?

15) Using the postulates and theorems of switching Boolean algebra try to
find more simplified Boolean formulas for the presented equations.

16) Using the postulates and theorems of switching Boolean algebra prove
the following equalities. Next to each step cite the postulate or theorem
used.

.
 Chapter 3
Functions, Mappings, Standards Forms

Boolean Function
A Mapping also called truth table represents a Boolean Function.

There are numerous ways to represent Boolean Algebraic Forms that

represents the same Function or Mapping.
For example the Boolean form

It is a representation of Function presented by the Mapping

There are two Canonical Boolean Forms that always represent the
function in the same way.
They are called Boolean Canonical Forms.
The first standard Boolean Canonical Form is the Form called sum of
standard product.
The second Boolean Canonical Form is the Disjunctive Canonical
Form that is a Sum of Standard Products.
Below is presented a table where all the standard products and
standards sums are shown.
 The standard products terms are called Minterm (m) and the standard
sums are called Maxterm.
A term type product of variables when the variables that are true (not
inverted) have the value one and the variables that are not true (inverted –
has a bar over the variable) have a value zero, takes the value 1.
A term type sum of variables when the variables that are true (not
inverted) have the value zero and the variables that are not true (inverted –
has a bar over the variable) have a value one, takes the value 0.
Then a Boolean form type sum of standard products presents all the
products that result in value 1 for the Function. This covers all the lines of
the mapping that result in a value 1 for the function. If one of the standard
product terms has a value 1 the function will have a 1 value.
A Boolean form type product of standard sums presents all the sums
that result in value 0 for the Function. This covers all the lines of the
mapping that result in a value 0 for the function.
If one of the standard sum terms has a value 0 the function will have a 0
value.
Proposition: A function F(a, b, ... k) can be represented by a Boolean
expression as the sum of all such products patterns which correspond to
input symbols that result in one value for the function.
Considering the standard products associated with the values of input
variables that result in value 1 for the function we will have the Boolean
form type sum of standard products. This form is called canonical
disjunctive form, or standard sum.

Proposition: A function F(a, b, ... k) can be represented by a Boolean

expression as the products of all such sums patterns which correspond to
input symbols that results in zero value for the function.
Considering the standard sums associated with the values of input
variables that result in value 0 for the function we will have the Boolean
form type product of standard sums. This form is called canonical
conjunctive form or standard product.

These two forms are equivalent to Boolean algebra, that is, starting
from one of the Boolean form and operating using postulates and theorems
of Boolean algebra it is possible to obtain the second Boolean form.

Functions Completely and Not Completely Specified

Next are presented two mappings. In the first one we have a
completely specified function, or for each of all lines defined by the input
variables of the function the value is defined as Boolean value 0 or 1.l
In the second mapping, for some lines defined by the input variables
of the functions the value is not defined. In terms of specification for the
design the result for these lines of the function is not used, the result may be
0 or 1 Boolean.
Completely Specified Function
For the function completely specified we have the following Boolean
form type Sum of Standard Products.

For the same function completely specified we have the following

Boolean form type Product of Standard Sums.

Operating algebraically using the postulates and theorems of Boolean

algebra we can prove that both Boolean forms are algebraically equivalent.

Not Completely Specified Function

For the function not completely specified we have a Boolean form
composed of sum of standard products, using only the standard products
that match the lines that results in value 1 for the function.
For the function not completely specified we have a Boolean form
composed of sum of standard products, using only the standard products
that match the lines that results in value 1 for the function.

For the same function not completely specified we have a Boolean

form composed of product of standard sums, using only the standard sums
that match the lines that results in value 0 for the function.

These two forms for the function not completely specified have a
minimum cost and match the values specified for the values 0 and 1 of the
mapping according to the values of the input variables.
 But operating algebraically using the postulates and theorems of
Boolean algebra it turns out that the aforementioned Boolean forms are not
algebraically equivalents.

This happens because the mapping lines for which the function value
is not defined have different values for each of the Boolean forms
presented.
For the sum of standard products the lines for which the values are not
defined will result in value 0 for the function. For the product of standard
sums the lines for which the values are not defined will result in value 1 for
the function.

Solved Problems
1) For the following mapping of a completely specified function provide the
standard forms type sum of products and product of sums.
Show algebraically that both standard forms are equivalent.

Solution:
-Product of standard sums

-Sum of standard products

First we develop and prove that F1 is equivalent to F2

Then we develop F2 and prove that it is equal to F1.

Although we have developed F1 and F2 to prove the equivalence of

Boolean forms actually just one of the ways is enough to develop and prove
their equivalence with the other standard form.
2) The mapping of a completely specified function is presented. Provide the Boolean standard forms
type sum of products and product of sums.

Show algebraically that both standard forms are equivalent.

Solution:
-Sum of Standard Products

-Product of Standard Sums

 If F1 and F2 are algebraically equivalent then it is just necessary to prove
that:

First it is proved that:

Proof:

Then it is proved that

Proof:

It was proved that F1 and F2 are equivalent forms.

3) A function not completely specified it is presented using reduced presentation for functions.
Provide the mapping, and the Boolean forms type product of standard sums and type sum of standard
products.

Solution:
First the mapping is constructed and their lines are filled with the values of
the reduced form specification for the function.
The maximum value in the reduced form specification is 7 then the function
will have three input variables. The mapping will have 8 lines.

The standard Boolean forms are:

-Sum of Standard Products

-Product of standard sums

Problems to be solved
1) Given the function completely specified F, presented in the reduced
notation provide the mapping and the standard forms type sum of products
and product of sums.
Show algebraically that both standard forms are equivalent.

2) Given the function F presented in the reduced notation provide the

mapping and the standard forms type sum of products and product of sums.
Show algebraically that both standard forms are equivalent.

3) Given the mapping of a Function not completely specified, provide a Boolean form type sum of
standard products and another Boolean form type product of standard sums.
4) Given the function F presented in the reduced notation provide the
mapping and the standard forms type sum of products and product of

sums.
5) Given the following six Boolean Forms provide disjunctive canonical
Boolean Forms type sum of products.

6) Given the following five Boolean Forms provide conjunctive canonical

Boolean Forms type product of sums for each one of the given forms.
 Chapter 4
Logical Circuits using Relays

General

The first relay appeared in the mid-nineteenth century, initially being

used in telegraphs and telephony equipment.
Currently the relays continue to be used in all applications where it is
necessary to turn on or off an electrical circuit requiring isolation between
the control circuit and power control circuit.
The relays are electro mechanical devices. They are manufactured to
control small currents of 100mA in micro relays, currents of 1A to 2A in
mini relays, and currents of 10A to 20A in power relays to control motors
and medium power equipment such as power relays.
In general, the insulation meets 127VAC or 240VAC for micro and
mini relays. Relays with capacity for currents of 10A to 20A have more
insulation.
To control devices with greater capacity of current and/or voltage the
relays are called contactors.
The micro and mini relays are manufactured to be used in printed
circuits boards. Relays of higher capacity and contactors are manufactures
to be installed in strips and panels, having sockets to be plugged or
terminals for normal wires of various diameters.
The operating principle of all types of relays is similar. It is used an
electro magnet that once energized attracts a piece built with magnetic
metal (iron) that when moved to a new position changes the position of
metal blades where are installed the electrical contacts called plates.
In terms of logic circuits, all computing machines and telephonic
connection centers used relays in their logic circuits until the 1960s.
Currently relays and contactors are used in electrical engineering of
low and high power, in control cabinets and electronic modules where a
better isolation between the electronic circuit and the power control part is
required.

Conventional Relay
Figure 4.1 presents a detailed drawing of the construction of a
conventional relay.
 In a reel constructed of insulating material is wrapped a coil using
copper.
The number of turns and the thickness of the copper wire depending
on type of AC or DC voltage and the voltage value needed to command the
relay or contactor.
For relay and contactor that operate with AC voltage the number of
turns is small so limiting the driver currents is due to coil inductance along
with its metallic core and magnetic circuit composed of the housing and
core.
To relays and contactors which are operated with DC voltage the
number of turns is much greater and the wire diameter is small as the value
of the current that circulates in the coil depends only on the total resistance
of the coil.

On the inside there is a cylindrical reel core constructed of magnetic

material (iron) that together with a structure built with metallic profiles in
the shape of L, called frame, composes the magnetic circuit.
This circuit is open at one end, where it is installed a part constructed
with magnetic material which is fixed on a pivot that allows it to move.
This part name Armor and Anchors complete the magnetic circuit. The
armor has a spring not shown in the drawing which tends to keep the armor
always moved away from the top of the reel core.
 When the coil is energized the concentrated magnetic flux in the
space between the armor and the top of the spool attract the armor that has
L format which moves through an isolated material the electrical contacts.
Between the top of the spool core and the armor there is a spacer
constructed of not magnetic material, normally copper or brass, establishing
a minimum distance between the magnetic core and the armor.
This is necessary so that when the coil is de energized, the residual
flux inherent in magnetic metals not retain the armor against the core of the
reel.
The electrical contacts are mounted into a composite structure of
insulating support materials. There are the upper and the lower fixed
contacts and central movable contacts which are operated by stacking the
control pin.
So when the coil is de-energized the lower fixed contacts are
connected to the central contacts so we call this lower contact as contact
Normally Closed (NC).
When the coil is energized the upper fixed contacts are connected to
the central contacts. So we call this upper contact as contact Normally Open
(NO).
In the schematic the coil is represented by the symbol of an inductor
and receives designation as the relay name in capital letters, for example,
RLA.
The contacts are represented with symbol keys open or closed and
receive the designation of which coil command them using lowercase
letters.
The normally-closed contact is represented through an alphabetical
lowercase letter followed by a forward slash. The normally open-contacts
don´t use the backslash.
As example a1, a1\, b1, b1\, c1, c1\, c2, c2\ are contacts of relays
RLA, RLB and RLC. The RLC has two contacts.
Usually in the schematic, control coils are presented in a part of the
circuit reserved for the command section, while contacts are shown in
power control part.
Operating times and release time for micro and mini relays are among
1mseg and 2 msec. For the relays 10A and 20A those times are around
5mseg order. Contactors times have greater values.
Bistable Relay – Magnetic Latching – Relay with Memory
 This type of relay is built in micro and mini format and has a different
philosophy of operation when compared with conventional relays and
contactors.
The construction consists of armor in the form of a seesaw and two coils
with their respective structures. Moreover, the assembly has two permanent
magnets.
When one of the coils is actuated during a time 3 times the
necessary specified time to attract the armor to the top of the coil, the armor
moves to the side of the energized coil.
When the coil is de-energized a permanent magnet installed side of
the coil retains the armor in this position. That is, the contacts remain in
position even the electrical command has no power. So we called the coils
with the names of Set and Reset coils. The Set coil when commanded closes
the NO contacts, and opens the NC contacts. The Reset coils open the NO
contacts and close the NC contacts.

This type of relay has the property of not consuming energy at the
command when not occurring state change. This property is important in
battery operated circuit where the power consumption is important.
The relay type depicted in Figure 4.2 has two fully independent coils
controlled by independent control circuits. It needs to be careful so that the
two coils are not activated simultaneously.
In the circuit presented below in figure 4.3 diodes are installed along
the coils so that only two command pins are sufficient to control the two
coils.
 So in the relay showed putting up positive potential in the control
terminal A and negative at control terminal B the Reset coil is triggered.
Reversing the polarity Set coil is triggered. Although the number of pins is
only two, the control circuit is more complex.
In this case there is no possibility of both coils are activated
simultaneously.

The relay coils are controlled by electronic circuits or panel push

buttons.
In the case of push buttons there are models with only one NO contact
or two contacts one NA and another NC. When the button is pressed, the
NO contact closes and NC opens, returning to rest states as soon as the
button is no longer pressed by opening the contact NO and again closing the
NC contact.
Also there are push buttons which have retention by mechanical
devices. That is, when the button is pressed the first time it is held tight. So
the NO contact is closed and NC contact open. When pressed a second time
the button returns to its home position by opening the NO contacts and
closing the NC type contacts.
The symbol of push buttons with only one NO contact is shown in
Figure 4.4, and the symbol of the push buttons with one NO and one NC
contact is shown in Figure 4.5.
 In terms of visual appearance on the panel a view of a push button is
shown in Figure 4.6.

Basic Definitions for Relay Circuits

In the presentation of the schematic of a circuit using relays all
electrical contacts NO or NC is always displayed in the state where they are
when all the coils are not energized.
Coils always have one side directly connected to the positive potential
in the case of circuits using DC power supplies and in the case of using AC
circuits in one phase of the AC power.
The other side of the coils is connected to command circuit that could
be an electronic circuit or a contact of another relay.
The contacts of the relays are always connected to the ground in
circuits that are powered by DC voltage. In circuits that use AC power the
contacts are connected to the neutral.
The relay contacts are considered to be in logical state 1 when the
ground or neutral is presented on the other side of the contact. When the
result shown in the output is an open circuit, i.e., the point is not connected
to any potential then the logic binary result is 0.
Considering the above definitions, when a coil of a relay is connected
to a contact or to a group of contacts of relays the result is binary 1, the coil
will be energized and their contacts are triggered, which indicates that the
settings are consistent.

Logic Circuits using Relays

The logical basic functions that allow the execution of any Boolean
form are AND plus OR functions. The inversion function is inherent to
relay contacts, because the relay has output contacts types NO and NC, and
the NC contact executes by itself the inversion function.

So in Figure 4.7 we have circuits corresponding Boolean functions

F1, F2, F3 and F4

Circuit with Intermediate Branch

For the circuit of figure 4.8 the form Boolean F5 is presented.
 This Boolean form can be optimized using Karnaugh maps or Quine
McCluskey algorithm.

Circuit to Power on and off Equipment

Figure 4.9 shows a circuit that is used to power on and off the
equipment.
The circuit uses two panel push buttons, one green color (On) and
other red color (Off).
These pushbuttons don’t keep the contacts actuated when are not
pressed.

Auxiliary Relay Circuit

Figure 4.10 presents a circuit that uses an auxiliary relay, RLC.
 Using algebraic operations a Boolean form capable of generating the
mapping (truth table) for this circuit is obtained.

Solved Problems
1) Given the Boolean form below that performs the function F

Present the truth table for the function F.

Also provide a circuit using only relays that executes the given Boolean
form.

Solution:
First the Boolean form is operated until a standard form is obtained.

From standard Boolean form it can be filled the truth table or mapping.

Operating algebraically a simplified form is obtained

Obtained the simplified form a circuit using only relays

Is presented
2) Analyze the given circuit providing the algebraic equation F and the truth
table.

Solution:
First the Boolean form is obtained from the circuit.

Operating algebraically a simplified Boolean form is obtained. The

obtained form is a simple product, so the truth table can be
filled.
 3) Given the following circuit, provide the Boolean form that executes the
function F, the truth table and a circuit using only relays.

Solution:
First the Boolean form is obtained from the circuit.

Operating algebraically a simplified standard Boolean form is

obtained.

Using the sum of

standard products form the truth table is filled.
 From the truth table a Boolean form using an auxiliary relay is
obtained.
Obviously a Boolean form without the auxiliary relay can be used. A
form without as auxiliary relay is less expensive.

4) Check algebraically if the F1 and F2 functions performed by the circuits

presented below are equivalents.
Solution:
First from the relay circuit that uses an auxiliary relay a Boolean form is
obtained.

Operating algebraically a simplified standard Boolean form type sum

of standard products is obtained.

Using the circuit that uses logic gates another Boolean form is

obtained.

Operating algebraically again a simplified standard Boolean form type sum

of standard products is obtained.
Comparing the two forms type sum of standard products for F1 and F2 it is
verified that both perform the same function.

Problems to be solved
1) Given the Boolean Form

Present the truth table for the Boolean form.

Provide a circuit using only relays that perform the function represented by
the given Boolean form.

2) Given the Boolean Form

Present the truth table for the given Boolean form.

Provide a circuit using only relays that perform the function represented by
the given Boolean form

3) Analyze the given circuit providing the Boolean Form F and the truth
table.

4) Analyze the circuit providing the Boolean form which executes the
function and show the truth table.
5) Review the circuit providing the Boolean form which executes the
function. Also show the truth table.

6) Analyze the circuit providing the Boolean form which executes the
function. Also show the truth table.

7) Review the circuit providing the Boolean form which executes the
function. Also show the truth table.
8) Given the circuit provide the algebraic equation that performs the
function F and present the truth table.

9) Given the circuit using logic gates, provide the Boolean form which
executes the function. Also show the truth table and a circuit using relays
that performs the function.

10) Given the circuit using logic gates, provide the Boolean form which
executes the function. Also show the truth table and a circuit using relays
that performs the function.
 11) Given the circuit using logic gates, provide the Boolean form which
executes the function. Also show the truth table and a circuit using relays
that performs the function.

12) Given the circuit using logic gates, provide the Boolean form which
executes the function. Also show the truth table and a circuit using relays
that performs the function.

13) Given the circuit using logic gates, provide the Boolean form which
executes the function. Also show the truth table and a circuit using relays
that performs the function.

14) Check algebraically if the Boolean forms F1 and F2 performed by

circuits below presented are equivalent.
15) Check algebraically if the Boolean forms F1 and F2 performed by
circuits below presented are equivalent.

16) Check algebraically if the Boolean forms F1 and F2 performed by

circuits below presented are equivalent.
17) Check algebraically if the Boolean forms F1 and F2 performed by
circuits below presented are equivalent.
18) Check algebraically if the Boolean forms F1 and F2 performed by
circuits below presented are equivalent.

19) Check algebraically if the Boolean forms F1 and F2 performed by

circuits below presented are equivalent.

20) Check algebraically if the Boolean forms F1 and F2 performed by

circuits below presented are equivalent.
21) Check algebraically if the Boolean forms F1 and F2 performed by
circuits below presented are equivalent.

22) Check algebraically if the Boolean forms F1 and F2 performed by

circuits below presented are equivalent.
 Chapter 5
Karnaugh Maps
The method of Karnaugh maps aims to generate combinational
circuits with the lowest possible cost from mapping of functions completely
or not completely defined.
The method works visually, i.e. it is not a typical mathematical
algorithm.
The method was developed in 1952 by Edward Veitch and improved
by Maurice Karnaugh engineer.
The visual operation of the maps allows obtaining minimum cost
formulas both as minimum sum of products or minimum amount of
product.
Because it is a visual method the maximum number of variables that
can be analyzed is 6 variables. In addition to this number of variables you
must use the computational algorithm of Quine - McCluskey.

Maps Construction

The construction of Karnaugh maps reproduces the mapping. Each

cell of the map represents and corresponds to a mapping line.
The cells of the maps are structured such that each cell is different
compared to any of its adjacent cells in one coordinate that corresponds to
the binary value of the input variables.
In Figures 9.1 to 9.5 are presented maps to 2, 3, 4, 5, and 6 input
variables.
Observe that inside each cell it is shown the decimal value which
identifies the line of the mapping. That value corresponds to the decimal
equivalent to the binary values of the various input variables.
In terms of operational maps the 2, 3 and 4 variables have the
property of joining the extreme columns so that the first column from left is
adjacent to the last column on the right. Likewise the top line joins the last
bottom line.
So, the reasoning is the formation of a cylinder in the vertical or
horizontal direction, but not simultaneously.
For maps of 5 and 6 variables, besides the union of the first and last
column and first and last line of each of the pieces of 4x4 cells that make up
the maps, these two models of maps have vertical and horizontal axes that
allow these maps be folded using these axes, making regions of 4x4 cells
adjacent to the cell of another 4x4 region over which the respective cell
regions overlap.
The horizontal and vertical axes are designed to be used one at a time.
They cannot be used simultaneously.
Filling the cell values

As explained, each cell represents a line mapping. The

correspondence between the mapping and the respective cell is based on the
cell number that is recorded in its upper corner. The cell number is the
decimal number equivalent to the composition of horizontal and vertical
binary number that specifies the cell position in the map.
So having the mapping with the function values, the value of each
line of the mapping is copied to the map correspondent cell.

For functions not completely specified a few lines of mapping

function don’t have a defined value. These lines are given the value X or D
(don’t care).

When the function is presented as an algebraic formula, this formula

must be converted to a formula type standard or not, sum of products or
product of sums.
Examples:

The F1 formula is a sum of products type.

In these cases it is only necessary that one of the products terms have
a value 1 and the function will have a 1 value.
So each one of the products are analyzed and checked for which
variables values it will present a 1 value.

a = 0, b =1 and c = 0

b = 1 and a = 1

b = 1 and d = 0
The remaining cells have binary value 0.
The F2 formula is a product of sums type.
In these cases it is only necessary that one of the sums terms have a
value 0 and the function will have a 0 value.
So each one of the sums are analyzed and checked for which variables
values it will present a 0 value.

a = 1, c = 1 e d = 0

b=0ea=0

b=0ed=1
The remaining cells are binary value 1.
Definitions and Cells Properties of the Karnaugh map

1) For a Karnaugh map of n variables, a cell defined by n input variables, is called cell order 0. This
cell may assume the value 0, 1 or X (or D).

2) Two cell order 0 defined by the n input variables are adjacent when the values of their input
variables differ in only one value.

Example: for a map of five variables the cells defined by the values 01101
and 01100 differ in only one variable. If these two cell level 0 has value 1
associated for each one, then these two cells of the order 0 cap be grouped
in a cell of order 1 which is defined by (n-1) coordinated with the value 1
assigned to it. This cell of order 1 is defined by (n-1) coordinated and an
empty coordinate that is represented by a -. That is, the cell of order 1 of
this example will be defined by 0110-.
The same applies if one of the original cells would have a value 1 and
the other the value X.
If the two original cells had both the value 0 assigned thereto the cell
resulting order 1 would have the value 0 assigned to it. The same if one of
the original cells had a value 0 and the other the value X.
If the two original cells had both the X value attributed to them the cell
resulting order 1 would have the value X assigned to it.
So we can present in a table the values attributed to the new cell, where
the original cell values that gave rise to the new cell and the value assumed
by the resulting cell are presented.

3) Two cell order (k-1) defined by the values of (k-1) input variables are
adjacent when the values of their input variables that define differ in only
one value and the empty variables represented by the symbol (- ) are located
in (s) same (s) position (s).
 For example in a map of five variables the cells defined by the values 0-
11- and 0-10- differ in only one variable and have the empty variables in the
same positions.
These two adjacent cells can be grouped in a cell of order k will be
defined by (n-k) variables and k empty variables.
The values assigned to the new order k cell will be set according to the
following table.

4) The process continues until the point where it is no longer possible to

group cells. This is usually due to incompatibility of values assigned to new
cells.
For example, there may be two adjacent cells but one has a value of 0
assigned to it and the other has the value 1, which makes them incompatible
in terms of assembly.
5) A minimum cost function is obtained by selecting a set of minimum number of highest possible
order of cells containing all cells with value 1 (not necessarily X). Each of the cells that compose this
set is represented by a product. The sum of these products composes a function the minimum sum of
products type.

6) A minimum cost function is obtained by selecting a set of minimum number of highest possible
order of cells containing all cells with value 0 (not necessarily X). Each of the cells that compose this
set is represented by a sum. The product of these sums composes a function the minimum product of
sums type.

Visual Processing of Karnaugh Maps

The definitions and properties presented in the previous section serves to set
the operating mode to obtain minimum cost function in product of sums
form or in the form of sums of products.
For incompletely specified functions, or for those where the mapping
function value for one or more cells is not set (X or D), the minimum
algebraic forms obtained by the Karnaugh Map method are not necessarily
algebraically equivalent.
But result in the correct values in order to produce the values specified for
the function lines where the function value is set.
Thus a few lines for which the function value is not set assume a value of 1
for the solution that has a form type product of sums.
In the case of function type sum of products a few lines for which the
function value is not set assume a value 0
Then eventually a cell for which the function value is not defined can take
the value 0 in solution type sum of products and take the value 1 in the
solution type product of sums.

Solved Problems

1) Given the function F in summary form and by mapping, build a

Karnaugh map for this function, fill it out and visually provide a minimum
function in the form of sum of products and a second one in the form of
product of sums
Also provide the two circuits using logic gates.
Summary form:

Mapping:

Solution:
 Initially, a Karnaugh map is built and is filled using the results given
by the mapping function.

To obtain an algebraic form type sum of products mark higher order

cells which present value 1 for function. The use or not the cells with X
value is optional.

So the minimum algebraic function in the form of sum of products is:

The circuit composed of OR of ANDs gate is presented below. This

circuit executes an algebraic formula type sum of products.

To obtain an algebraic form type product of sums mark higher order

cells which present value 0 for function. The use or not the cells with X
value is optional.
 So the minimum algebraic function type product of sums is:

The circuit composed of AND of ORs is given below. This circuit

executes an algebraic formula type product of sums.

2) Given the function Z in summary form and by mapping, build a

Karnaugh map for this function, fill it out and visually provide a minimum
function in the form of sum of products and a second one in the form of
product of sums
Also provide the two circuits using logic gates.
Summary form:

Mapping
Solution:
Initially build up the Karnaugh map and fill it in using the results of
the function given by mapping.

I
To obtain an algebraic form type sum of products mark higher order
cells which present value 1 for function. The use or not the cells with X
value is optional.
 So the minimum algebraic function type sum of products is:

The circuit that realizes the algebraic function composed of ANDs,

ORs and Inverters gate is presented below.

To obtain an algebraic form type product of sums mark higher order

cells which present value 0 for function. The use or not the cells with X
value is optional
So the minimum algebraic form type product of sums is:

The circuit constructed using ANDs, ORs and inverters gate that
executes the form type product of sums is shown below.

Problems to be solved

1) Given the algebraic function below using Karnaugh maps method for
minimization of combinational circuits, provide a minimum circuit using
logic gates ANDs, ORs and inverter in the form of sum of products.
Also provide a minimum circuit using the form of product of sums.
2) Given the algebraic function below using Karnaugh maps method for
minimization of combinational circuits, provide a minimum circuit using
logic gates ANDs, ORs and inverters in the form of sum of products.
Also provide a minimum circuit using the form of product of sums.

3) For the given circuit provide the mapping data and using the Karnaugh
Map method minimize the circuit and present a minimal one in the form of
algebraic sum of products and a second minimal one in the form of
algebraic product of sums.
For each of the minimum algebraic forms present the corresponding circuit
using logic gates of ANDs, ORs and inverters.

4) For the given circuit provide the mapping data and using the Karnaugh
Map method minimize the circuit and present a minimal one in the form of
algebraic sum of products and a second minimal one in the form of
algebraic product of sums.
For each of the minimum algebraic forms present the corresponding circuit
using logic gates of ANDs, ORs and inverters.
5) For the given circuit provide the mapping data and using the Karnaugh
Map method minimize the circuit and present a minimal one in the form of
algebraic sum of products and a second minimal one in the form of
algebraic product of sums.
For each of the minimum algebraic forms present the corresponding circuit
using logic gates of ANDs, ORs and inverters.

6) For the given circuit provide the mapping data and using the Karnaugh
Map method minimize the circuit and present a minimal one in the form of
algebraic sum of products and a second minimal one in the form of
algebraic product of sums.
For each of the minimum algebraic forms present the corresponding circuit
using logic gates of ANDs, ORs and inverters.
7) For the given circuit provide the mapping data and using the Karnaugh
Map method minimize the circuit and present a minimal one in the form of
algebraic sum of products and a second minimal one in the form of
algebraic product of sums.
For each of the minimum algebraic forms present the corresponding circuit
using logic gates of ANDs, ORs and inverters.

8) For the given circuit provide the mapping data and using the Karnaugh
Map method minimize the circuit and present a minimal one in the form of
algebraic sum of products and a second minimal one in the form of
algebraic product of sums.
For each of the minimum algebraic forms present the corresponding circuit
using logic gates of ANDs, ORs and inverters.
9) For the given circuit provide the mapping data and using the Karnaugh
Map method minimize the circuit and present a minimal one in the form of
algebraic sum of products and a second minimal one in the form of
algebraic product of sums.
For each of the minimum algebraic forms present the corresponding circuit
using logic gates of ANDs, ORs and inverters.

10) Given the function below presented in summary form, provide a

mapping and Karnaugh map.
Using the method of Karnaugh maps to obtain lower cost circuits
presents a minimum cost algebraic form as the product of sums and another
minimum algebraic form type sum of products. Provide the circuits for both
algebraic forms using ANDs, ORs and inverters.

11) Given the mapping below using the method of Karnaugh Maps provide
a minimum cost algebraic form as the product of sums and another
minimum algebraic form type sum of products.
Provide the circuits for both algebraic forms using ANDs, ORs and
inverters.
 12) Given the mapping below using the method of Karnaugh Maps provide
a minimum cost algebraic form as the product of sums and another
minimum algebraic form type sum of products.
Provide the circuits for both algebraic forms using ANDs, ORs and
inverters.

13) Given the mapping below using the method of Karnaugh Maps provide
a minimum cost algebraic form as the product of sums and another
minimum algebraic form type sum of products.
Provide the circuits for both algebraic forms using ANDs, ORs and
inverters.
14) Given the mapping below using the method of Karnaugh Maps provide
a minimum cost algebraic form as the product of sums and another
minimum algebraic form type sum of products.
Provide the circuits for both algebraic forms using ANDs, ORs and
inverters.

15) Given the mapping below using the method of Karnaugh Maps provide
a minimum cost algebraic form as the product of sums and another
minimum algebraic form type sum of products.
Provide the circuits for both algebraic forms using ANDs, ORs and
inverters.
 16) Given the mapping below using the method of Karnaugh Maps provide
a minimum cost algebraic form as the product of sums and another
minimum algebraic form type sum of products.
Provide the circuits for both algebraic forms using ANDs, ORs and
inverters.
 Chapter 6
Quine McCluskey Algorithm

The method of Karnaugh maps although easy to perform is only able

to minimize the cost of circuits with up to 6 inputs i.e. 6 variables.
For more complex circuits were developed computational algorithm
Quine McCluskey.
The algorithm was initially developed by Edward Joseph McCluskey
in 1952 and improved and expanded by Van Orman Quine Willard in 1956.
There are many programs developed in various programming
languages running Quine-McCluskey algorithm.
Quine McCluskey algorithm runs independently to obtain minimum
cost forms of the type sum of products or product of sums type.
The operating principle in the algorithm is the idea of grouping
adjacent cells as in the Karnaugh map that result in the same value for the
function (1 and X) or (0 to X), trying to get cells of the highest possible
order.
The algorithm during its execution always presents along with the
term that represents the cell of higher order, the terms of zero order being
covered by this higher order term.

The algorithm is presented by executing an example that uses an

incompletely specified function that has 5 variables.

Example – Algorithm for Sum of Products

The function is shown below.
 Initially it is necessary to define what type of Boolean form will be
generated, sum of products or product of sums.
In the case of sum of product the terms that are listed are whose
which input variables result in the value 1 and X to the function.

In the case of sum of product the terms that are listed are whose
which input variables results in a value of 0, and X for the function.
First is presented an example for obtaining a Boolean form type sum
of products.

1) Initially is built a list of the terms of entry, order 0, that result in value 1
and X for the function

2) The list is rearranged in ascending or descending order by groups according to the number of
input variables that have value 1 (or 0) that make up the input set of order 0 terms.
3) A list sorted by groups is processed. Each and all of the terms of a group are compared to one and
all the terms of the group adjacent to verify if each pair has terms that differ (are different) in only
one variable in the same position.

If this is true a new term is generated in a new list indicating the terms
of order 0 that originated and - (dash) in the single variable position that
was different.
Each of the two terms that participated in generating the new term in
the new list receives a mark indicating that this term was used, so indicating
that this term was covered by the new term of higher order added in the new
list.
The new terms are of order 1, and are defined by n-1 variables and
have an empty variable in the position where the original generators terms
differed.
Compared with the method of Karnaugh maps the list of elements of
order 1 has the elements that are representative of all cells of order 1 (2
order 0 cells) able to be formed with the cells order 0 which has a value 1 or
X.
4) The resulting list of the previous step where the terms of order 1 were
generated with an empty variable, separated by groups according to the
number of variables with a value of 1, is now processed.
Each and all of the terms of a group are compared to one and all the
terms of the group adjacent to verify that each pair has terms that have an
empty variable in the same position and differ in only one variable in
another same position.
If this is true a new term is generated in a new list indicating the terms
of order 1 that contributed to the generation of the new term of order 2. The
new term has the position of the variable in which the original terms of
order 1 differed filled by a – (dash)
 Each of the two terms of order 1 that originated the term of order 2 in
the new list receives a mark indicating that these terms were used, so
generating an indication that these terms were covered by the new term of
order 2 that appears in the new list.
The new terms are of order 2 and are defined by n 2 variables and
have two empty variables, at the position in which the two original terms of
order 1 already had an empty variable and another at the position where the
only variable of the original terms differed.
Compared with the method of Karnaugh maps the list of terms of
order 2 presents the terms that are representatives of all cells of order 2 (4
cell class 0) able to be formed with the cells of order 0 that has value 1 or
X.
To end this part of the procedure is necessary to remove from the new
table the duplicate terms.
5) The resulting list from the previous step that generated the terms of order 2 with two empty
variables, separated by groups of terms that have the same number of variables with value equal to 1
is now processed.
6) The procedure should continue to the extent that it is no longer possible to generate higher
order terms.

This actually happens or why the last step of the procedure generated a
list with only one set of terms that have variables with same number of
values 1, or why although there are more than one group, the terms of these
groups are not possible to be grouped, that is, there aren’t terms that have
empty variables in the same positions and only differ in the value of a same
variable in the same position.

7) In this example, the procedure turned out because the process generated
only one group.
At this point the process should generate a list of all terms in all
process steps that have not received a tag, i.e. that were not covered by the
new higher-order terms.
These terms are named Prime implicant terms as they involve the
generation of the Boolean form representing the function. If we make a sum
of products of all prime implicant terms it will generate a form that
represents the Boolean function
8) To be able to abandon redundant terms and get a Boolean form of lower
cost is built a covering table.
For the construction of this table on the rows are presented the prime
implicants terms and at the columns the 0 order input symbols that result in
value 1 for the function.
The input symbols that result in value X should not appear in the table
because the cover of these terms is optional.
So we present the covering table according to the list of prime
implicants terms

The table receives a mark indication X marking the terms of order 0

contained in columns that are covered by the prime implicants terms
presented at the rows.

9) Columns that have the terms of order 0 that result in value 1 to the
function and which are covered by just that prime implicant term makes this
an essential term. So this term is called term prime implicant essential.
For the example the term --- 0-11- and 00 are terms prime implicants
essential.
The mark X corresponding to that term in the columns that have
become these terms essential receives a symbol of a square.
 X marks corresponding to these essential terms at other columns
receive a symbol of a circle.

These terms prime implicant essentials are stored in a list of terms

that will necessarily compose Boolean form.

10) Having defined the terms prime implicant essential one new reduced
covering table is built. At the rows are presented the terms that are not
prime implicant essential. At the columns those input symbols that were not
covered by the terms prime implicant essential

In this new table is included a new column that presents the cost of
construction of the term.
The cost is calculated according to the number of variables that
compose the terms plus one that represent the cost of the output.
That is, the cost considers the number of pins that are used in the
integrated circuits that will compose the circuit.
To obtain the lowest cost form of Boolean sum of products type it is
necessary to select a set of prime implicants terms of lower cost that cover
all columns contained in the table. This set of the terms more the essential
prime implicants terms already stored in the list of prime implicant essential
terms will compose the final Boolean form.
The set of terms that meets these requirements are composed of the
terms: 0 - - - 0, - 1011 and 1001 - . Plus the terms prime implicant
essential 0 - 11- and - - - 00 the lower cost Boolean form is constructed.

11)As a result of Boolean form of lower cost, type sum of products we have the circuit made up of
logic gates:

12) As a result of Boolean form of lower cost, type sum of products we

have the circuit built using relays:

Example – Algorithm for Product of Sums

 In the case of sums of product are listed the terms whose input variables
results in a value 0, and X for the function.
1) Built a list of the input symbols that result in 0 and X values to the function.

2) The list is rearranged in ascending or descending order by groups according to the number of
input variables that have value 1 (or 0) which compose the input terms of order 0
3) A list sorted by groups is processed. Each and all of the terms of a group are compared to one and
all the terms of the group adjacent to verify if each pair has terms that differ (are different) in only
one variable in the same position.

If this is true a new term is generated in a new list indicating the terms of
order 0 that originated and a - (dash) in single variable position that was
different.
Each of the two terms that participated in generating the new term in
the new list receives a mark indicating that this term was used, so indicating
that this term was covered by the new term of higher order added in the new
list.
The new terms are of order 1 and are defined by n-1 variables and
have an empty variable in the position where the original generators terms
differed.
Compared with the method of Karnaugh maps the list of elements of
order 1 has the elements that are representative of all cells of order 1 (2 cell
class 0) able to be formed with order cells 0 which has value 0 or X.
4) The resulting list of the previous step where the terms of order 1 were
generated with an empty variable, separated by groups according to the
number of variables with a value of 1, is now processed.
Each and all of the terms of a group are compared to one and all the
terms of the group adjacent to verify that each pair has terms that have an
empty variable in the same position and differ in only one variable in
another same position.
If this is true a new term is generated in a new list indicating the terms
of order 1 that contributed to the generation of the new term of order 2. The
new term has the position of the variable in which the original terms of
order 1 differed filled by a – (dash)
 Each of the two terms of order 1 that originated the term of order 2 in
the new list receives a mark indicating that this term was used, and
therefore generating an indication that this term was covered by the new
term of order 2 listed in the new list.
The new terms are of order 2 and are defined by n-2 variables and
have two empty variables at the positions were the two original terms of
order 1 already had an empty variable, and another at the position where the
only variable of the original terms differed
Compared with the method of Karnaugh maps the list of terms of
order 2 presents the terms that are representatives of all order cell 2 (4 cell
class 0) able to be formed with the cells of order 0 that has value 0 or X.
To end this part of the procedure is necessary to remove from the new
table the duplicate terms.

5) The resulting list from the previous step that generated the terms of
order 2 with two empty variables, separated by groups of terms that have
the same number of variables with value equal to 1 is now processed.
6) The procedure should continue to the extent that it is no longer possible to generate higher order
terms.

This actually happens or why the last step of the procedure generated a
list with only one set of terms that have variables with same number of
values 1, or why although there are more than one group, the terms of these
groups are not possible to be grouped, that is, there aren’t terms that have
empty variables in the same positions and only differ in the value of a same
variable in the same position.

7) In this example, the procedure turned out because the process generated
only one group.
At this point the process should generate a list of all terms in all
process steps that have not received a tag, i.e. that were not covered by the
new higher-order terms.
These terms are named Prime implicant terms as they involve the
generation of the Boolean form representing the function. If we make a
product of sums of all prime implicant terms it will generate a form that
represents the Boolean function
8) To be able to abandon redundant terms and get a Boolean form of lower
cost it is built a covering table.
For the construction of this table at the rows are presented the prime
implicants terms and at the columns the 0 order input symbols that result in
value 0 for the function.
The input symbols that result in value X should not appear in the table
because the cover of these terms is optional.
So we present the covering table according to the list of prime
implicants terms, and the input symbols that result in value 0 to the
function.

The table receives a mark indication X marking the terms of order 0

contained in columns that are covered by the prime implicants terms
presented at the rows.

9) Columns that have the terms of order 0 that result in value 0 to the
function and which are covered by just that prime implicant term makes this
an essential term. So this term is called term prime implicant essential.
For the example the term 000 - 1, - - -01, 11-10, are terms prime
implicant essential.
The mark X corresponding to that term in the columns that have
become these terms essential receives a symbol of a square.
X marks corresponding to these essential terms at other columns
receive a symbol of a circle.
 These terms prime implicant essentials are stored in a list of terms
that will necessarily compose Boolean form.

10) Having defined the terms prime implicant essential one new reduced
covering table is built. At the rows are presented the terms that are not
prime implicant essential. At the columns those input symbols that were not
covered by the terms prime implicant essential

In this new table is included a new column that presents the cost of
construction of the term.
The cost is calculated according to the number of variables that
compose the terms plus one that represent the cost of the output.
That is, the cost considers the number of pins that are used in the
integrated circuits that will compose the circuit.
To obtain the lowest cost form of Boolean product of sums type it is
necessary to select a set of prime implicants terms of lower cost that cover
all columns contained in the table. This set of the terms more the essential
prime implicants terms already stored in the list of prime implicant essential
terms will compose the final Boolean form.
 The set of terms that meets these requirements is composed by term:
1-11-. Plus the terms prime implicant essential 000 -1, 11 -10, - - - 01 the
lower cost Boolean form is constructed.

11) As a result of Boolean form of lower cost, type product of sums it is

presented the circuit made up of logic gates:

12) As a result of Boolean form of lower cost, type product of sums it is

presented the circuit built using relays:

Solved Problems

1) Given a circuit that was built using logic gates provide a mapping for
this circuit.
From the mapping using the Quine McCluskey algorithm provides a
minimum cost Boolean forms type sum of products and product of sums.
 Show the minimum cost circuits using logic gates and relays for both
minimum cost forms.

From the circuit is obtained the Boolean form that it executes.

Using the postulates and theorems the Boolean for is modified in
order to obtain a sum of products standard form.

Using the terms type standard products the mapping is filled in.

Solution type sum of products

 First it is built a list of the input symbols that result in value 1 to the
function.
The list is rearranged in ascending or descending order by groups
according to the number of input variables that have value 1 which compose
the input terms of order 0
The list sorted by groups is processed. Each and all of the terms of a
group are compared to one and all the terms of the group adjacent to verify
if each pair has terms that differ (are different) in only one variable in the
same position.
If this is true a new term is generated in a new list indicating the terms of
order 0 that originated and a - (dash) in single variable position that was
different.
Each of the two terms that participated in generating the new term in
the new list receives a mark indicating that this term was used, thus
indicating that this term was covered by the new term of higher order added
in the new list.
The new terms are of order 1 and are defined by n-1 variables and
have an empty variable in the position where the original generators terms
differed.
The same procedure is realized to generate a new table with terms
order 2 defined by (n-2) variables and having 2 empty variables.

In this example, the procedure turned out because the process generated
only one group.
At this point the process should generate a list of all terms in all
process steps that have not received a tag, i.e. that were not covered by the
new higher-order terms.
Using the list a covering table is constructed.
The rows present the prime implicants terms and at the columns the 0
order input symbols that result in value 1 for the function.
 So we present the covering table according to the list of prime
implicants terms, and the input symbols that result in value 1 to the
function.

Columns that have the terms of order 0 that result in value 1 to the
function and which are covered by just that prime implicant term makes this
an essential term. So this term is called term prime implicant essential.
For the example the term -111 and 1-0- are terms prime implicant
essential.
The mark X corresponding to that term in the columns that have
become these terms essential receives a symbol of a square.
X marks corresponding to these essential terms at other columns
receive a symbol of a circle.
For this problem the two prime implicant terms essential cover all the
columns, i.e. all the input symbols that result in value 1 to the function.
Thus the Boolean for is composed only by the two terms:
-111 and 1-0-
The Boolean form of lower cost is as follows:

The circuit using logic gates is shown below:

The circuit using relays is as follows:

Solution type product of sums

First it is built a list of the input symbols that result in value 0 to the
function.
The list is rearranged in ascending or descending order by groups
according to the number of input variables that have value 1 which compose
the input terms of order 0
The list sorted by groups is processed. Each and all of the terms of a
group are compared to one and all the terms of the group adjacent to verify
if each pair has terms that differ (are different) in only one variable in the
same position.
If this is true a new term is generated in a new list indicating the terms of
order 0 that originated and a - (dash) in single variable position that was
different.
Each of the two terms that participated in generating the new term in
the new list receives a mark indicating that this term was used, so indicating
that this term was covered by the new term of higher order added in the new
list.
The new terms are of order 1 and are defined by n-1 variables and
have an empty variable in the position where the original generators terms
differed.
The same procedure is realized to generate a new table with terms
order 2 defined by (n-2) variables and having 2 empty variables.
 In this example, the procedure turned out because the process generated
two groups with terms that are not possible to be grouped because the
empty variables are not in the same position.
At this point the process should generate a list of all terms in all
process steps that have not received a tag, i.e. that were not covered by the
new higher-order terms.
Using the list a covering table is constructed.
The rows present the prime implicants terms and at the columns the 0
order input symbols that result in value 0 for the function.
So we present the covering table according to the list of prime
implicants terms, and the input symbols that result in value 0 to the
function.

Columns that have the terms of order 0 that result in value 0 to the
function and which are covered by just that prime implicant term makes this
an essential term. So this term is called term prime implicant essential.
For the example the term 0-0-, -01-and --10 are terms prime implicant
essential.
The mark X corresponding to that term in the columns that have
become these terms essential receives a symbol of a square.
 X marks corresponding to these essential terms at other columns
receive a symbol of a circle.
For this problem the three prime implicant terms essential cover all
the columns, i.e. all the input symbols that result in value 0 to the function.
So the Boolean form is composed only by the three terms
The Boolean form of lower cost is as follows:

The circuit using logic gates is shown below:

The total cost of the circuit shown is given by:

Cost = 2 + 3 + 3 + 3 + 4 = 15

The circuit using relays is as follows:

Problems to be solved

1) Given the circuit that uses logic gates provide a mapping for this circuit.

From the mapping using Quine McCluskey algorithm present the

minimum cost Boolean forms type sum of products and product of sums.
 Present the minimum cost circuits using logic gates and relays for
both Boolean forms.
Calculate the total cost of the two circuits built with logic gates.

2) Given the circuit that uses logic gates provide a mapping for this circuit.

From the mapping using Quine McCluskey algorithm present the

minimum cost Boolean forms type sum of products and product of sums.
Present the minimum cost circuits using logic gates and relays for
both Boolean forms.
Calculate the total cost of the two circuits built with logic gates.

3) Given the circuit that uses logic gates provide a mapping for this circuit.

From the mapping using Quine McCluskey algorithm present the

minimum cost Boolean forms type sum of products and product of sums.
 Present the minimum cost circuits using logic gates and relays for
both Boolean forms.
Calculate the total cost of the two circuits built with logic gates.

4) Given the circuit that uses relays provide a mapping for this circuit.

From the mapping using Quine McCluskey algorithm present the

minimum cost Boolean forms type sum of products and product of sums.
Present the minimum cost circuits using logic gates and relays for
both Boolean forms.
Calculate the total cost of the two circuits built with logic gates.
 Chapter 7
Quine McCluskey Algorithm for Multiple Simultaneous
Outputs Functions

The Quine McCluskey also operates to minimize a group of circuits

for performing multiple simultaneous functions that use the same set of
variables at their inputs.
Multiple simultaneous functions designated more than a function
executed at the same time using the same set of variables at their inputs.
A typical example is a decoder that has 4 inputs, where are presented
decimal numbers represented in BCD notation, and have 7 outputs. Each
one of the 7 outputs commands a segment of a seven segments led display.
As the inputs are the same, circuit parts can be used for more than one
function, minimizing the cost of circuit implementation.
The algorithm will be presented using an example of minimization for
three simultaneous functions, initially generating Boolean forms type sum
of products and then generating Boolean forms type product of sums.

Example using Quine McCluskey Algorithm

For F1, F2 and F3 functions that are part of the same circuit provides
the mappings and apply Quine McCluskey algorithm for simultaneous
multiple functions, generating a minimum circuit for all the three functions
type sum of products and another circuit type product of sums.
Provide the circuits using logic gates

Solution for Sum of Products

1) Initially filled the mapping to the three functions that are all composed
of four variables, as the term of maximum value is15.
2) Using the same methodology of Quine McCluskey algorithm to only one functions, it’s created a
table with all the terms that result in value 1 and X for all three functions, noting next to the term the
(s) functions to which the term belong.

Using 1 and X will generated Boolean expressions type sum of

products.
The list is rearranged in ascending or descending order by groups
according to the number of input variables that have value 1 (or 0) that
make up the input terms of order 0
3) The list sorted by groups is processed. Each and all of the terms of a group are compared to one
and all the terms of the group adjacent to verify that each pair has terms that differ (are different) in
only one variable in the same position.

If this is true a new term is generated in a new list indicating with a –

(dash) the position where the two original terms of order 0 had a different
value for the input variables. Also the terms order 0 numbers and the
functions that were common to both original terms are annotated next to the
new term of order 1.

Each of the two terms that participated in generating the new term in the
new list receives a mark if all the functions to which the term belongs were
covered by the new term of order 1.
The new terms are of order 1 and are defined by (n-1) variables and
have an empty variable in the position where the original generators terms
differed.

4) The resulting list of the previous step generating the terms of order 1
with an empty variable, separated by groups according to the number of
variables with a value of 1, is now processed.
Each and all of the terms of a group are compared to one and all the
terms of the group adjacent to verify that each pair has terms that have an
empty variable in the same position and differ in only one variable in
another same position.
If this is true a new term is generated in a new list indicating the terms
of order 1 that contributed to the generation of the new term of order 2. The
new term has a dash in the position where both terms of order 1 had a dash,
and an extra dash in the position where the variable in which the original
terms of order 1 differed.
Also the functions that were common to both original terms that
generated the new term are indicated.
Each of the two terms of order 1 that participated in generating the new
term in the new list receives a mark if all the functions to which the term
belongs were covered by the new term of order 2
The new terms are of order 2 and are defined by (n-2) variables and
have two empty variables in the positions where the original terms already
possessed an empty variable and a new one in the position where the two
terms of order 1 are different.
5) In each of the steps is required at the end of generation of the new list to
remove the terms that do not cover any of the functions, and also remove
the repeated terms.
These terms were removed from the list, and the table without these
terms is presented below.
The table that present terms of the second order is now processed
generating a new list with the terms of order 3.
The terms used that have all its functions covered by the new term
generated received a check mark.
The list of terms of order 3 shows just a term that covers the F1 function
in only one group. This condition ends this stage of the process.

6) The terms unmarked in the set of all steps are prime implicants terms
for the functions associated with these terms.
They are used to generate the covering table where in the lines are listed
these terms and at the columns are presented the terms order 0 that result in
value 1 to the function.
The terms that result value X to the function are not presented at the
columns because they are optional.
Below is presented the covering table for the functions F1, F2, and
F3.
 The functions F1, F2 and F3 don’t present terms prime implicant
essential.
Analyzing the table it can be observed that the terms 1---along with
the term -1-1 fully cover the F1 function.
The term -1-1 more terms1-10 and 0--1 cover the F2 function.
Withdrawing these term and all terms of order 0 at columns covered
by them, a reduced covering table is constructed.

Analyzing the reduced covering table it is concluded that a choice of

lower cost is given by the terms -00- and 1-0- or any other choice that use
two term with cost 3 capable of covering the values 0, 8 and 13.
Thus we have the end result:

F1: 1---, -1-1

F2: -1-1, 1-10, 0--1
F3: 1-10, 0--1, -00-, 1-0-

Using the terms chosen, results the circuit presented below using logic
gates:

Using the terms chosen, results the circuit presented below using
relays:

Solution for Product of Sums

Solution:
1) For best viewing the three mappings of functions F1, F2 and F3 are

repeated.
2) Using the same methodology of Quine McCluskey algorithm to only one
functions, it’s created a table with all the terms that result in value 0 and X
for all three functions, noting next to the term the (s) functions to which the
term belong.
Using 0 and X will generated Boolean expressions type product of sums.
The list is rearranged in ascending or descending order by groups
according to the number of input variables that have value 1 (or 0) that
make up the input terms of order 0
3) The list sorted by groups is processed. Each and all of the terms of a
group are compared to one and all the terms of the group adjacent to verify
that each pair has terms that differ (are different) in only one variable in the
same position.
If this is true a new term is generated in a new list indicating with a –
(dash) the position where the two original terms of order 0 had a different
value for the input variables. Also the terms order 0 numbers and the
functions that were common to both original terms are annotated next to the
new term of order 1.

Each of the two terms that participated in generating the new term in the
new list receives a mark if all the functions to which the term belongs were
covered by the new term of order 1.
The new terms are of order 1 and are defined by (n-1) variables and have
an empty variable in the position where the original generators terms
differed.
4) The resulting list of the previous step generating the terms of order 1
with an empty variable, separated by groups according to the number of
variables with a value of 1, is now processed.
Each and all of the terms of a group are compared to one and all the
terms of the group adjacent to verify that each pair has terms that have an
empty variable in the same position and differ in only one variable in
another same position.
If this is true a new term is generated in a new list indicating the terms
of order 1 that contributed to the generation of the new term of order 2. The
new term has a dash in the position where both terms of order 1 had a dash,
and an extra dash in the position where the variable in which the original
terms of order 1 differed.
Also the functions that were common to both original terms that
generated the new term are indicated.
Each of the two terms of order 1 that participated in generating the new
term in the new list receives a mark if all the functions to which the term
belongs were covered by the new term of order 2
The new terms are of order 2 and are defined by (n-2) variables and
have two empty variables in the positions where the original terms already
possessed an empty variable and a new one in the position where the two
terms of order 1 are different.
5) In each of the steps is required at the end of generation of the new list to
remove the terms that do not cover any of the functions, and also remove
the repeated terms.
These terms were removed from the list, and the table without these
terms is presented below.
The table that present terms of the second order is now processed
generating a new list with the terms of order 3.
The list of terms of order 3 shows just a term that doesn’t cover any
function. This condition ends this stage of the process.
6) The terms unmarked in the set of all steps are prime implicants terms for
the functions associated with these terms.
They are used to generate the covering table where in the lines are listed
these terms and at the columns are presented the terms order 0 that result in
value 0 to the function.
The terms that result value X to the function are not presented at the
columns because they are optional.
Below is presented the covering table for the functions F1, F2, and
F3.

The functions F1, F2 and F3 don’t present terms prime implicant

essential.
Analyzing the table it can be observed that the terms 0--0 along with
the term -011 fully cover the F1 function.
Withdrawing these term and all terms of order 0 at columns covered
by them, a reduced covering table is constructed:
 Analyzing the reduced covering table it is concluded that a choice of
lower cost is given by the terms -100 and 10-1 or any other choice that has
the same cost for F2.
For the F3 function the term 001- and 111- cover the remainder of the
terms of order 0 that were not yet covered.

Thus we have the end result:

F1: 0--0, -011

F2: 0--0, -011, -100, 10-1
F3: -011, 001-, 111-, 01-0

Using the terms chosen it is presented the circuit using gates

 Using the terms chosen it is presented the circuit using relays

Solved Problems

1) Using Quine McCluskey Algorithm for multiple functions, provide

the minimum forms type product of sums and sum of products for function
presented below.
Show the minimum circuits using logic gates.

F a[1]={1,5,6,7}
F a[X]={0}
F b[1]={0,5}
F b[X]={1,7}

F c[0]={0,1,2,4}
F c[X]={7}

Problem 1: Solution Type Sum of Products:

First the procedure for the terms that result in value 1 and X for the
functions is realized generating expressions type sum of products for the
functions.
A table with the order 0 terms that result in value 1 or X for the
functions, is constructed.
Then the terms are separated into groups according to the number of
input variables with the value 1 (or 0).
The terms of order 0 that do not cover any function are abandoned.

The table with the order 0 terms, separated by groups, is processed

generating a new table with the order 1 term, that present an empty variable
in the position where the original order 0 terms were different.
The functions that are common to both order 0 original terms, are
indicated next to the term of order 1. The terms that do not cover any of the
functions are abandoned.
The original terms that had all its functions covered by the new
generated order 1 term are marked indicating that these terms has already
been totally covered.
 The same procedure is performed for the new table generated with
terms of order 1, which will produce a new table with terms of order 2
defined by two empty variables.
The terms that do not cover any functions are abandoned

All terms that have not received a mark in all process steps, indicating
that they have been covered, are added in a list of prime implicant terms

Using the prime implicants terms as input to horizontal lines and the
values of the terms of order 0 that results in value 1 to the functions as entry
for the columns a covering table is constructed

The terms essential prime implicant are marked at the columns that
they cover.
So the term 00- is essential to the function F-a and F b, and the term
-11 is essential to the function F c and the term 11- is essential to the
functions F-a and F c.
 Withdrawing the essential prime implicant terms from the lines and
the terms order 0 that are covered by them from the columns it is generated
a reduced covering table.

Based on the reduced covering table the term of lowest cost is 1-1 for
F a, F b and F c. This term cover all three functions.
So it is presented the Boolean expression for the three functions:

Below is the circuit using logic gate:

Problem 1: Solution Type Product of Sums:

Following the procedure for the terms that result in value 0 and X for
the functions, is realized generating expressions type product of sums for
the functions.
A table with the order 0 terms that result in value 0 or X for the
functions, is constructed.
Then the terms are separated into groups according to the number of
input variables with the value 1 (or 0).
 The terms of order 0 that do not cover any function are abandoned.

The table with the order 0 terms, separated by groups, is processed

generating a new table with the order 1 term, that present an empty variable
in the position where the original order 0 terms were different.
The functions that are common to both order 0 original terms, are
indicated next to the term of order 1. The terms that do not cover any of the
functions are abandoned.
The original terms that had all its functions covered by the new
generated order 1 term are marked indicating that these terms has already
been totally covered.
The same procedure is performed for the new table generated with
terms of order 1, which will produce a new table with terms of order 2
defined by two empty variables.
The terms that do not cover any functions are abandoned

All terms that have not received a mark in all process steps, indicating
that they have been covered, are added in a list of prime implicant terms
 Using the prime implicants terms as input to horizontal lines and the
values of the terms of order 0 that results in value 0 to the functions as entry
for the columns a covering table is constructed

The terms essential prime implicant are marked at the columns that
they cover.
So the term 01- is essential to the function F-a, and F b, the term -1- is
essential to the function F b and the term 100 is essential to the functions F-
a, F b and F c.
Withdrawing the essential prime implicant terms from the lines and
the terms order 0 that are covered by them from the columns it is generated
a reduced covering table.
 Based on the reduced covering table the terms of lowest cost is 00-
and 0-0 are chosen for F c.
So it is presented the Boolean expression for the three functions:

Below is the circuit using logic gate:

2) Using Quine McCluskey Algorithm for multiple functions, provide

the minimum forms type product of sums and sum of products for function
presented below.
Show the minimum circuits for both solutions, using logic gates.

F a [1]={1,3,5,6,7}
F b [0]={0,2,4,5}
F c [0]={2,4,6,7}

Problem 2: Solution Type Sum of Products:

 First the procedure for the terms that result in value 0 for the functions
is realized generating expressions type sum of products for the functions.
A table with the order 0 terms that result in value 1 for the functions is
constructed.
Then the terms are separated into groups according to the number of
input variables with the value 1 (or 0). The terms of order 0 that do not
cover any function are abandoned.

The table with the order 0 terms, separated by groups, is processed

generating a new table with the order 1 term, that present an empty variable
in the position where the original order 0 terms were different.
The functions that are common to both order 0 original terms, are
indicated next to the term of order 1. The terms that do not cover any of the
functions are abandoned.
The original terms that had all its functions covered by the new
generated order 1 term are marked indicating that these terms has already
been totally covered.
The same procedure is performed for the new table generated with
terms of order 1, which will produce a new table with terms of order 2
defined by two empty variables.
The terms that do not cover any functions are abandoned
 All terms that have not received a mark in all process steps, indicating
that they have been covered, are added in a list of prime implicant terms

Using the prime implicants terms as input to horizontal lines and the
values of the terms of order 0 that results in value 1 to the functions as entry
for the columns a covering table is constructed

The prime implicant terms essential are marked at the columns where
they are the only prime implicant term that cover the column. Also the other
columns that are covered by those prime implicant essential are marked.
Thus the term 0-1 is essential for F a, F b and F c, the term -01 is
essential for F a and F c and the term 11- is essential for F a and F b and
finally the term 00- is essential for F c.
The prime implicant essential terms cover all terms of order 0 of the
three functions. So it’s not necessary to build a reduced covering table.
So it is presented the Boolean expression for the three functions:
Below is the circuit using logic gate:

Problem 2: Solution Type Product of Sums:

Now the procedure for the terms that result in value 0 for the
functions is realized generating expressions type product of sums for the
functions.
A table with the order 0 terms that result in value 0 for the functions is
constructed.
Then the terms are separated into groups according to the number of
input variables with the value 1 (or 0). The terms of order 0 that do not
cover any function are abandoned.
 The table with the order 0 terms, separated by groups, is processed
generating a new table with the order 1 term, that present an empty variable
in the position where the original order 0 terms were different.
The functions that are common to both order 0 original terms, are
indicated next to the term of order 1. The terms that do not cover any of the
functions are abandoned.
The original terms that had all its functions covered by the new
generated order 1 term are marked indicating that these terms has already
been totally covered.
The same procedure is performed for the new table generated with
terms of order 1, which will produce a new table with terms of order 2
defined by two empty variables.
The terms that do not cover any functions are abandoned

All terms that have not received a mark in all process steps, indicating
that they have been covered, are added in a list of prime implicant terms.

Using the prime implicants terms as input to horizontal lines and the
values of the terms of order 0 that results in value 0 to the functions as entry
for the columns a covering table is constructed
 The terms essential prime implicant are marked at the columns that
they cover.
So the term 10- is essential to the function F b, and the term 11- is
essential to the function F c.
Withdrawing the essential prime implicant terms from the lines and
the terms order 0 that are covered by them from the columns it is generated
a reduced covering table.

Based on the reduced covering table the term of lowest cost is 0-0 for
“F a” and “F b”.
The term 100 is chosen to compose F a and F c. The term -10 is
chosen to have lowest cost to compose F c.
So it is presented the Boolean expression for the three functions:

Below is the circuit using logic gate:

Problems to be solved

1) Using Quine McCluskey algorithm for multiple functions provide the

minimal Boolean expressions to F a, F b, and F c, type product of sums and
sum of products.
These three functions are not completely specified.
Present the circuits for the two Boolean expressions using logic gates.

.
2) Using Quine McCluskey algorithm for multiple functions provide the
minimal Boolean expression to F a, and F b, type product of sums.
These two functions are not completely specified.
Present one circuit using logic gates and another circuit using relays.

3) Using Quine McCluskey algorithm for multiple functions provide the

minimal Boolean expression to F a, F b, and F c type product of sums.
These three functions are not completely specified.
Present the circuits using logic gates.

4) Using Quine McCluskey algorithm for multiple function provide the

minimal Boolean expressions to F a, and F b, types sum of products and
product of sums.
These two functions are not completely specified.
Present the circuits using logic gates and relays for both solutions.

5) Using Quine McCluskey algorithm for multiple functions provide the

minimal Boolean expressions to F a, and F b, types sum of products and
product of sums.
These two functions are completely specified.
Present the circuits using logic gates and relays for both solutions.

6) Using Quine McCluskey algorithm for multiple functions provide the

minimal Boolean expressions to F a, F b and F c, types sum of products and
product of sums.
These three functions are completely specified.
Present the circuits using logic gates and relays for both solutions.

7) Using Quine McCluskey algorithm for multiple functions provide the

minimal Boolean expressions to F a, F b and F c, types sum of products and
product of sums.
These three functions are completely specified.
Present the circuits using logic gates and relays for both solutions.

8) Using Quine McCluskey algorithm for multiple functions provide the

minimum Boolean expressions for the decoder functions F a, F b, F c, F
d, F e, F-f, F g, type product of sums and sum of products.
These functions have as inputs variables W, X, Y, Z.
Assume that the LEDs light up segments with logical 1 value.
Present the two circuits using logic gates.
 Chapter 8
NAND and NOR Circuits

Logic Gates

In chapter 2 where Boolean algebra was presented was proven that the
operations “+” (OR) and”.” (AND) are associative and the Boolean
expressions can be written without the use of parentheses.

(a .b).c=a .b .c
(a +b)+c=a +b +c

The fact of the OR and AND operations are associative allows the
expansion of OR gates and AND multiple entries, numbering more than 2.
Usually integrated circuits are manufactured with 2, 3 or 4 entries for these
Boolean algebraic operations.
It is important to note that even after expanded the OR and AND
gates remain associative.

With respect to algebraic operations NAND and NOR the expansion

of OR gates and AND multiple entries allows the addition of an inverter on
the gate output as a single circuit resulting in integrated circuits with 2, 3
and 4 inputs for NAND and NOR operations
However it should be noted that the operations NAND and NOR are
not associative in any case, i.e. even with only two entries they do not meet
the property of associativity.
 The mappings for algebraic operations NAND and NOR for two
inputs are presented here:

The standard circuits for algebraic operations NAND and NOR with
two entries are shown below.
Using the concept of positive logic we have: V + = logical 1 and 0
Volts = 0 logical.

We observed that for the NAND operation the output only has value 0
when all the variables at inputs have 1 value. We can also observe, for NOR
operation, that the output has the value 1, when all the variables at inputs
have value 0.
So we can provide mappings for the two extended algebraic
operations for k entries.
 The standards circuits for algebraic operations NAND and NOR allow
the expansion for k entries by adding more entries with the addition of a
greater number of diodes at the inputs.
Using the concept of positive logic we have for these circuits V + =
logical 1 and 0 Volts = logical 0.

Again we must mention that the algebraic operations NAND and

NOR are commutative but not associative to any number of input terminals.

Sheffer Boolean Algebra

Henri Maurice Sheffer proved in 1913 in an article called "A set of

five independent postulates for Boolean algebras with applications for
logical constants" that a Boolean algebra can be defined using a single
primitive binary operation NAND or its dual NOR operation. The NAND
│
binary operation is symbolized by Sheffer as a vertical bar │ called "Sheffer
Stroke" and an arrow pointing to the bottom ↓ or † called "Dagger Symbol"
to represent the algebraic operation NOR.
We will use the symbol # to represent any one of two operations in
postulates, as they apply to both operations.
A Boolean algebra defined by Sheffer is a mathematical system as
defined below:

Definition: Sheffer Boolean Algebra

Definition: A set B along with the algebraic operation # is a Boolean

algebra if the following properties to set B and the operation # stand as true:

Postulate 1: There are at least two distinct elements in set B.

Postulate 2: If a and b are elements of B, a # b is an element of B.

By definition there is a Unary operation a # a whose result refers to an
element

Postulate 3: If variable “a” is an element of B then:

Postulate 4: If a and b are elements of B then:

Postulate 5: If “a”,” b” and “c” are elements of B then:

Let's assume that this definition of Boolean algebra is equivalent to

the definition presented in Chapter 2 where a Boolean algebra was
presented.
So as a Switching Boolean algebra consists of only two elements 0
and 1 then considering B = {0,1} we have that the group of assumptions in
this chapter can be used to set a switching Boolean algebra.

Verification of Postulates for NAND and NOR Operations

Postulate 1: For this switching logic presented as true B must have two
elements, the elements 0 and 1 i.e. B = {0, 1} for both operations.

Postulate 2: Let’s assume the operation NAND:

How can we verify the NAND operation results in all its lines in an
element of B = {0, 1}
On the other hand the operation “#” results in the complement
element which is also an element B = {0, 1}.
Now we will verify the operation NOR:
 How it can be verified NOR operation results in all its lines in an
element of B = {0, 1}
Furthermore # operation used as a NOR operation results in the
element complement that it is also an element of B= {0, 1}.
So the Postulate 2 is true for both operations NAND and NOR.
Postulate 3: Analyzing the mappings for operations NAND and NOR it can
be observed that:

As defined by Postulate 2.

That is valid for both operations.

Postulate 4: First analyzing for operation NAND

Following analyzing for operation NOR

Postulate 5:

First it will be analyzed operation NAND.

Replacing the sections in brackets

Replacing the remainder of operations #:

Now it will be analyzed operation NOR

Replacing the sections in brackets:
Replacing the remainder of operations #:

Thus we conclude that the switching Boolean algebra defined by

Sheffer is applicable for both NAND and NOR operations.
The most important however is the conclusion that just one of two
operations for this switching Boolean algebra is complete.

Proof of not associativity of Operations │ e ↓

a │ ( b │ c) ≠ ( a │ b ) │ c ≠ a │ b │ c (1)
a ↓( b ↓ c) ≠ ( a ↓ b ) ↓ c ≠ a ↓ b ↓ c (2)
First for the operation │ (“stroke”)

It can be observed that the results are different, i.e. the algebraic
operation │ (“stroke”) is not associative.
Now for operation ↓ (“dagger”)

It can be observed that the results are different, i.e. the algebraic
operation ↓ (“dagger”) is not associative.
 The mappings for algebraic operations NAND and NOR already
presented above show that if the same input variable is connected to the two
inputs of a NAND and NOR circuit the value of the output will be the
opposite of the value applied at the two entries, that are equal.
This can be seen in the two tables showing the output result of the
first circuit when both inputs have a value of 0 and the output result when
both inputs have the value 1.
Another observation is that an opposite result can be obtained by
applying the value logic 1 in one of the entries of NAND operation. In this
case the resulting value in the output is the logical value of the complement
applied to the second input.
The same is true for the NOR operation. Applying the value 0 in one
of the entries, the result at the output will be the complement of the logical
value applied to the second entry.

This had already been defined by Postulate 2.

Analyzing Circuits with the Operations “Stroke” and “Dagger”

First it will be analyzed a circuits that uses algebraic operation type

“stroke”.
 Following it will be analyzed a circuit that uses algebraic operation
type “dagger”.
Synthesis of Circuits using Operations “Stroke” and “Dagger”

The circuit synthesis using only operations "Stroke" or only

operations "Dagger" is performed in a reverse process to the process used in
the analysis.
Initially for operation "Stroke":

The algebraic form calculated is executed by the circuit below.

Now for “Dagger” operation:

 The algebraic form calculated is executed by the circuit below.

It has been shown in the chapter that presented Boolean algebra,

solved problems section, that NAND and NOR operations perform a
Switching Boolean algebra completely, i.e. each one of these operations
NAND or NOR can realize all operations alone.
What is needed to be demonstrated is how to minimize these circuits
using only one of these models of logic gates.

Theorem – Disjunctive Form:

If a minimum form of the disjunctive type (Sum of Products) is

transformed into an algebraic expression using only operations "Stroke", the
resulting algebraic expression is a minimal form of a switching Boolean
function performed using NAND type circuits on only two levels.

Proof: A disjunctive form describes a minimum circuit with two levels

executed by AND operations and followed by an OR operation.
This expression can always be transformed into a minimal operation
using two levels of NAND type gates, because the only OR gate used in the
circuit output can be performed by a NAND gate, since its inputs are all
reversed. However, this inversion is already at the output of NAND gates
used in the first level circuit. Thus the circuit constructed from the
disjunctive form using only NAND gates is a minimum cost circuit.
 If the original form has a disjunctive term with only one variable, this
variable in the circuit using only NAND gates should be reversed using a
NAND gate with the two inputs connected together.

Theorem – Conjunctive Form:

If a minimum form of the conjunctive type (Product of Sums) is

transformed into an algebraic expression using only "Dagger" operations,
the resulting algebraic expression is a minimal form of a switching Boolean
function performed using NOR type circuits on only two levels
.
Proof: A conjunctive form describes a minimum circuit with two levels
executed by OR operations and followed by an AND operation.
This expression can always be transformed into a minimal operation
using two levels of NOR type gates, because the only AND gate used in the
circuit output can be performed by a NOR gate, since its inputs are all
reversed. However, this inversion, is already at the NOR gates outputs, used
in the first level circuit. Thus the circuit constructed using the conjunctive
form using only NOR gates, is a minimum cost circuit.
If the original form have a disjunctive term, with only one variable,
this variable in the circuit using only NOR gates should be reversed using a
NOR gate with the two inputs connected together.

Solved Problems

1) For the F function expressed through a form type Boolean Sum of Products, develop a circuit that
uses only operations "Stroke" with two inputs.
2) For the F function expressed through a form type Boolean Product of Sums, develop a circuit that
uses only operations "Dagger" with two inputs.
Problems to be solved

1) For each of the switching functions represented below by their forms provide the Boolean
expressions using only operations type "Stroke".

Draw the circuits.

2) For each of the switching functions presented in the previous problem provide the expressions
using only operations type "Dagger".

Draw the circuits.

3) For each of the following expressions that represent switching Boolean functions presents sum of
products type forms.

Draw the circuits for each function.

4) For each of the expressions presented in the previous problem that represent switching Boolean
functions present switching Boolean forms type product of sums.

Draw the circuits for each function.

5) For each of the circuits present below provide switching Boolean function type product of sums.
Draw the new circuits.
6) For each of the circuits presented at the previous problem provide a
switching Boolean form type sum of products. Draw the new circuits.

7) Given the Boolean form below, and assuming that only are available operations "Stroke" with 2
entries, provide an expression for each one of the forms, using only this type of operation.

Draw the circuits for each function.

8) Given the Boolean forms of the previous problem, and assuming that only are available "Dagger"
operations with 2 entries, provide an expression for each one of the forms, using only this type of
operation.

Draw the circuits for each function.

 Chapter 9
Function Decomposition

In this chapter it will be presented methods to carry out the

decomposition of Boolean forms for the purpose of reducing costs in the
circuit construction that will accomplish the implementation of Boolean
form.
It will be shown that in many implementations is possible to
decompose a Boolean form in a combination of two or more smaller
Boolean forms that together will implement the Boolean original form with
less cost.

Simple Disjunctive Decomposition

Definition: A set of two Boolean forms

G (y1, y2,….. , y k) and H (G (y1, y2,....., y k), z1, z2, ...., Zn-k)
constitute a single disjunctive decomposition of a digital Boolean function F
(x1, x2, ..., x n) if and only if:

a) Each variable y represents a variable x and each variable z represents a

variable x.

U represents the union of the sets Y and Z forming the set X

and the ø symbol represents an empty set.

d) F(x1, x2,...., x n )=H(G(y1,y2,...., y k ),z1,z2,...., z n-k )

The set of requirements b) and c) indicates that there are no common variables to the y and z sets.

The total of both sets of elements form the set x

Example:

The function F (a, b, c, d) has its mapping shown below:

Its minimum Boolean form type sum of products is:

If we establish the function

And also establish the function:

So the function F will be:

At where: a=z1, b=z2, c=y1, and d=y2

 As specified above G and H are a simple disjunctive decomposition
for the F function whose mapping was presented in this example.
This decomposition is called as “simple” because it has only one sub
function G.
It is also called a disjunctive because each of the variables a, b, c, d is
a variable of group y or a variable of group z, but not of both groups
simultaneously.
As can be observed, there is a significant cost difference between the
construction of the circuit using the minimum Boolean form type sum of
products and the execution using the decomposition of functions.

Propositions:
As established in the definition of the construction characteristics of a
Boolean form by simple disjunctive decomposition, two sets of variables
that have no intersection compose the two sub Boolean forms that will
make the Boolean decomposed original form
It will be presented hereafter three propositions to make it possible to
calculate the number of possibilities for the decomposition of the original
Boolean form using two sub forms.

Proposition:
A set of variables X={x1, x2,..., xn} has 2n possible distinct
partitions.
Assume that Y and Z are both disjoint subsets i.e. that have no
intersection. The variable xk is in one of the subsets but not in both.
So it is possible to establish two ways for where the variable xk is: it
is in the subset Y or it is in subset Z.
Thus there are 2n possible different possibilities to be set where the
variables of set X are.
Proposition:
Let’s suppose that the number of elements in Y is j.
Partitions with j = 0, j = 1 and j = n are trivial to be established.
For j = 0 there are no variables in the set Y, i.e. the Boolean form G
(y1, y2, ....,yk) does not exist.
For j=1 a single variable is assigned to the Y subset, or G (y1) = xi. In
this case we will have n possibilities of choice for xi.
For j = n all variables are allocated to Y. subset i.e. the Z subset is
empty.
Thus for a set X = {x1, x2, x3} according to the previous proposition
it will be possible to have partitions 23 = 8 partitions where 3 + 1 + 1 = 5
are trivial to be established.
So we can present another proposition:

Proposition:
Based on the previous Proposition for a set X = {x1, x2, ....,xn} there
are (2n - n – 2) partitions not trivial.

Proposition:
It is possible to expand a Boolean form with respect to a variable b,
according to the process explained below:
Repeating the Boolean form sum of products type:

It is possible to describe it as:

Where:

In other words, M and N functions can be obtained by the following

process:
Shannon expansion theorem:

It is possible to expand the form of a Boolean form with n variables

with respect to a variable xi where i, according to the process explained
below is using the following process:
Function:

Expansion:

Where for xi =0

And for xi=1

If xi=0:

And if xi=1:

Application of Propositions in Sequence

For the function

 It’s possible to apply the Shannon Expansion Theorem in a sequence
i.e.:
First applying to the c variable:

Following applying for each one of the Boolean sub forms to the d
variable:

Replacing these two latter forms at the previous form the results are:

Where:

Replacing the previous four expressions in F (a, b, c, d) the result

is:

As it can be seeing the result is the same expression obtained at the

beginning of the chapter.
The difficulty that arises it is first determine if a function can be
decomposed in simple disjunctive form and then what are the variables that
will compose G and H

Partition Tables

For the function:

 There are 4 variables. Then it will have 24 different partitions. I.e. it
will have 16 possible partitions for the sets Y and Z.
Four partitions have: G= (y1, y2, y3)
Four partitions have: G= (y1)
Six partition have: G= (y1, y2)
Together with the two trivial partitions 0 and 1 for G, the total will be
16 different partitions.
For didactic reasons all tables, except the trivial 0 and 1 will be displayed.
In practice it is necessary only draw half of partition tables, as we
consider G components such as rows or as columns.

The four partition tables below presented don’t have possibility of

generate
These tables will not generate Boolean forms using simple disjunctive
decomposition.
 The two partition tables presented below can generate Boolean form
using simple disjunctive decomposition.

The final Boolean form for Table A is:

The final Boolean form for Table B is:

The final Boolean form for Table C is:

The final Boolean form for Table D is:

 The four tables of 2 rows and 2 columns partitions cannot have its
simple disjunctive decomposition obtained because the lines have to have
terms with result 1 for the function that can

in the composition of their elements.

For example, the first table has the first row with the elements 4 and 5
with the value 1 and the line 10 has the elements 8 and 9 which form the
complement. But it has more the lines 01 and 11 which have a single
element each. Then this table doesn’t present only the function G and its
complement and 0 or 1 lines.
The other three tables present the same problem.

The following two tables presented with two rows and two columns
have the necessary conditions for generating a Boolean form using simple
disjunctive decomposition.
The final Boolean form for Table E is:

The final Boolean form for Table F is:

As it can be seeing both partition tables are symmetrical and produce

the same result in the end.
It is also important to note that it was only used the form G. Its
complement was not used.

Final Considerations

There were two methods presented in this section to perform a simple

disjunctive decomposition of a digital Boolean form, to any number of
variables.
In the first method the Boolean form is expanded using the Shannon's
expansion theorem using variables chosen in successive operations.
In the second method partition tables were developed and a method of
analysis was used to choose the tables that allow the execution of simple
disjunctive decomposition.
The partition tables allow the definition of the variables that will be
used in the expansion, while the use of Shannon's theorem in successive
expansion operations does not generate an indication of the variables to be
used in each operation.
That is, to have a good result by using only the Shannon Expansion
Theorem is necessary that various attempts are carried out using varying
combinations.
 Also partition table for four variables forms have been developed.
Performing an analysis method using the Shannon Expansion
Theorem or using Partition Tables method, results in the observation that
the processes to generate simple disjunctive decomposition forms are
complicated to perform.
The process for decomposing non-disjunctive becomes much more
complex.
The same is true for not simple decomposition, where the number of
sub functions is greater than one.
But it is important to know that there are methods to perform
decomposition of functions, and normally the application of these methods
greatly reduces the complexity of logic circuits, and allows repeated use of
logic circuits common to several functions.

Solved Problems

1) Present all simple disjunctive decomposition possible for the function

not completely specified given below:

Solution:
Using the partition tables already developed for 4 variables functions
results:

The following tables do not allow trivial simple disjunctive decomposition

for the given function
 The following tables do not allow non-trivial simple disjunctive
decomposition for the given function:

The following partition tables allow trivial simple disjunctive

decomposition to the given function:
 The final Boolean form for Table A is:

The final Boolean form for Table B is:

The final Boolean form for Table C is:

The final Boolean form for Table D is:

The final Boolean form for Table E is:

The final Boolean form for Table F is:

The following partition tables allow non-trivial simple disjunctive

decomposition to the given function:
The final Boolean form for Table G is:

The final Boolean form for Table H is:

Problems to be solved

1) Develop a complete set of partition tables to 3 variables functions.

2) How many trivial partitions and how many non-trivial partitions are
possible for a 3-variable function?

3) Presents a simple disjunctive decomposition for the function given using

only the Shannon Expansion Theorem.

4) Present all the simple disjunctive decomposition possible for the

functions given below:
5) Present all the simple disjunctive decomposition possible for the
functions given below:

6) For the function F(a, b, c,....k) that has k variables prove that the four
given equations are true:

7) Check if the given function can be decomposed. If so, make the

decomposition and provide the circuit for the decomposed function.

F[1] = { 2, 6, 9, 11}
F[X]= { 1,12,13 }

8) Check if the given function can be decomposed. If so, make the

decomposition and provide the circuit for the decomposed function.

F[1] = { 0,2,5,9 }
F[X]= { 10,12,14,15 }

9) Check if the given function can be decomposed. If so, make the

decomposition and provide the circuit for the decomposed function.
F[1] = {0,3,4,7,13,14}
 Chapter 10
Iterative Network

An iterative network is a combinational circuit composed of identical

cells connected in sequence. The following figure shows the typical
structure. Each cell has as inputs external connections and connections with
the previous cell and has as output connections to the next network cell and
external outputs.
There is a particular case where the network cells do not have external
connections on each of the cells and the connection to the next cell is the
output of the circuit.

Iterative Network - 1 Dimension

The results presented in the outbound connection to the next cell of

the network and its own exit to the outside depends of what the inputs of the
cells receive from the previous cell and the inputs of the cell itself.
A typical cell is shown below:

Each cell has k external inputs whose input symbol is given by:

Defined on the set B= {0, 1}.

Each cell has i inputs connected to i outputs of the preceding cell whose

symbol is given by:

Also defined on the set B= {0, 1}.
Each cell has i outputs that will be connected to i inputs of following cell
whose symbol is given by:

Also defined on the set B= {0, 1}.

Each cell has optionally r external outputs whose symbol is given by:

Also defined on the set B= {0, 1}.

The k external inputs are considered as primary inputs and the i inputs
connected to the outputs of the previous cell are considered secondary
entries.
The set formed by the primary and secondary entries is called as
“total set of inputs”.
The i outputs connected to the next cell are considered secondary
outputs. The r external outputs are considered primary output.
The set formed by the primary outputs and secondary outputs is called
as “total set of outputs”.
The total output symbol presented by the cell in its total set of outputs
is dependent of the total input symbol presented to its total set of inputs.
The total symbols are composed by the set of primary and secondary
symbols.

Iterative Network – 2 dimensions

An interactive network composed by 2-dimensional structure is as

shown below:
Typical use of Iterative Networks
The circuits composed by iterative networks are typically circuits that
are of repetitive type.
If the circuit construction using a single circuit would result in a
large-scale circuit, then the circuit is realized using individual cells.
Each cell performs a part of the repetitive process and the circuit for
each cell results in a simple circuit easy to perform.
Typical examples are the transformation of a number into Gray code
for decimal base, the realization of a circuit that performs the addition and
subtraction of binary numbers, a circuit that presents an output with value 1
when all bits presented in their entries have an even number of values 1, etc.

Cells Generation Process

Example 1: Adder and Subtractor

To present the cells Circuit Generation method it will be use the

mappings of the adder and subtractor.
Operations with binary numbers for addition and subtraction have
already been presented in Chapter 1. They are repeated again below:
The mappings for the adder and subtractor are:

The inputs and outputs Symbols table is as follows :

The initial state of secondary entries is indicated by * on the left of

the value of the secondary inputs. In this case we have two possibilities for
the secondary +/- entry. This happens because it is possible to choice
between sum or subtraction operation.
The typical cell diagram is shown below:

As we have three outputs and four inputs considering the total inputs
and outputs, we can build three Karnaugh maps using four variables.

For the map relating to the choice of operation adder / subtractor it

will have to +/- + / - = + / -. That is, the own entrance +/- +/- is repeated on
the secondary output.
This is an expected result because all cells need the information if the
operation being performed is an addition or subtraction.
To carry / borrow the minimal cost Boolean function is given by:

To sd the minimal cost Boolean function is given by:

The circuit of standard cell for the adder and subtractor is presented below:

The network to an adder / subtractor for 4 binary digits is shown

below. This network can be connected to other networks increasing the
number of bits added or subtracted simultaneously.

Example 2: Gray Code to Binary Number Converter using Logic Gates

 In this example it will be presented an iterative network that converts
Gray coded numbers to binary numbers.
If the number in base 10 is required, it must convert the binary
number to base 10.
Let's use the same example presented in Chapter 1 where a binary
number has been transformed into Gray code.

So the number 47 in base 10, whose equivalent in binary base is

0101111, is transformed to the Gray coding resulting in the number 111000
in Gray code.
The iterative network is designed to perform conversion of Gray
coding in a binary number encoding. The process begins with the use of the
leftmost digit.
The result of the operation carried out by the leftmost cell is obtained
by entering the value 0 in the secondary input and comparing this entry with
the value of the primary input of the cell.
Because the first cell start with a 0 value this condition is indicated
with a * in the secondary entrance with value 0, showing that this is the
initial value of the first cell of the network.
If the value of the primary input is 0 the value of the secondary entry
is maintained and displayed in the main output and transferred to the
secondary output. If the value of the primary input is 1, the value of the
secondary input is inverted and presented in primary and secondary outputs,
transferring this result to the next cell
The inputs and outputs Symbols table is presented below:
The diagram of the typical cell is as follows:

The Karnaugh maps for the primary output and secondary output are
as follows:

The Boolean forms that execute the ss and sp functions are:

The circuit for the standard cell is presented below:

An iterative network with the ability to convert a number with up to 4

Gray digits in 4 binary digits is presented below
 If it’s presented at the entrance es4 the value 0 and at the input ep4 the
first leftmost value of Gray number that is 1the cell will present the value 1
at their outputs. Continuing the process using Gray number 111000 it will
result in the binary number 1011112.

Example 3: Parity Generation or Parity Verification using Logic Gates

In the transmission of binary numbers through a communication link,

due to existing noise in the normal means, can be added to the signal errors,
that will appears in the reception of the binary number sent.
To make it possible to check the occurrence of any error in reception
it is added an additional bit to the byte being transmitted. This additional bit
added is called parity and has the value 0 or 1 according to the number of
bits having the value 1 in the byte.
For example, if the number 001100102 is the number that will be
transmitted one additional bit with value 1 is added at the end of
transmission so that the number of bits having value 1 is an even number.
Then the number that will be transmitted will be 1001100102.
If the number to be transmitted is the number 100100112, an
additional bit will be added with the value 0 since the number of bits having
the value of 1 in the byte already has an even number, thus the number to be
transmitted is 0100100112.
It will presented an iterative network that performs the function of
calculating the bit to be added in the transmission or check whether the
number received has been received correctly
The inputs and outputs Symbols table is presented below:
 When the process is started the number of bits having value 1 is zero
then the additional bit to be added will be zero. Then the initial value
indicated with a * is zero at the secondary input.
In the first cell if the bit which appears on the primary input has a
value 1, then the bit to be added will have the value 1 so as to make the total
number of bits having 1 even
If the bit presented in the first cell, on the primary input has a value 0
then the number of bits is already even. Then the value presented at the
outputs will be a 0 value.
If the secondary input indicates that the bit has value 1 and the bit of
the primary entry has value 0, it will be necessary to add a bit of value 1.
If the secondary input indicates that the bit has value 1 and the bit of
the primary entry has value 1, it will not be necessary to add a bit of value
1. Then the outputs will present a 0 value.

The iterative network that calculates the parity bit to be added to the
byte that will be transmitted doesn’t have primary output, as only interests
the result displayed on the secondary output of the last cell.
Thus the table that shows the various symbols of inputs and outputs
does not have a primary output table.
This same table performs the function of checking correct reception
of the binary number.
The difference between the iterative network that calculates the bit to
be added and the iterative network that verifies whether the binary number
has been correctly received, it is in the fact that on the network that
calculates the bit to be added, the first cell gets in its secondary input one
fixed value 0, while on the network that checks if the received byte was
correctly received the first cell receives at its secondary input the value of
the first bit of the received number.
The Karnaugh map that represents the network standard cell is
presented below:

The typical network cell block diagram is presented below:

The Boolean form that performs the functions ss is presented below:

The circuit of each cell is as follows:

The block diagram for a network that it’s capable of verifying a

complete byte is shown below
Example 4: Verification Number of Bits with Value 1 equal 3

The iterative network must receive a byte in their primary inputs and
must provide at the secondary output of the last cell a value of 1 if the
number of bits with the value 1 in the Byte equals 3.
Secondary entries must present the following information:
a) No bit with value 1 so far.
b) 1 bit with value 1 so far.
c) 2-bit value 1 until the moment.
d) More than 3-bit value 1 until the moment.
e) 3 bits with value 1 so far.
The table with the states and input and output symbols is given
below:

As we have five possible situations it will be used 3 bits to encode

the 5 possible states.

Then it’s established:

a) 000 b) 001 c) 010 d) 011 e) 100
 So the most important information is presented in an isolated
line that is the bit of the highest order in the secondary output, i.e. the
secondary output a.
The table with the states and input and output symbols already
with the binary values is given below:

The Karnaugh maps for a, b, and c are as follows:

Following are presented the Boolean forms that perform the functions
a, b, and c:

Below the circuit of the standard cell that makes up the iterative
network:
 The structure of the iterative network to a Byte is shown below:

Example 5: Verification of a bit value 1 after a minimum of 8 bits value

0

In communication performed between devices are commonly used

one or more bytes with value 0 in all bits and communication starts with a
bit 1 in the first position of the first byte of the correct message.
Thus it’s required a circuit to indicate that the bit 1 that has emerged
in communication is the first bit of a correct message.
The following states are possible:
a) 0 bit with 0 values.
b) 1 bit with 0 values.
c) 2 bits with 0 values.
d) 3 bits with 0 values.
e) 4 bits with 0 values.
f) 5 bits with 0 values.
g) 6 bits with 0 values.
 h) 7 bits with 0 values.
i) 8 bits or more with 0 values.
j) 1 bit with value 1 after 8 or more bits with 0 values.
The table with the states and input and output symbols is given
below:

As there are 10 possible situations it’s necessary to use 4 bits to

encode the 10 possible states required:
Then the following binary numbers are established to encode
the 10 possible states:
a) 0000 b) 0001 c) 0011 d) 0010 e) 0110 f) 0111 g) 0101 h) 0100 i) 1100 j)
1000
Thus the most important information is displayed by the value 1000
in the secondary outputs. An AND gate with two inputs and an inverter it is
necessary to distinguish the state i) from the state j).
The Karnaugh maps for a, b, c and d are as follows:
 Below the Boolean forms that perform the functions a, b, c and d:

Below the circuit of the standard cell that makes up the iterative
network:

The structure of the iterative network to 8 bits is given below:

Example 6: Gray Code to Binary Number using Relay Circuit

In this example we will present the same iterative network of

Example 2. That is, it will be developed an iterative network able to convert
numbers into Gray code to binary numbers using relays.
Let's use the same example presented in Chapter 1 where a binary
number has been transformed into Gray code.

So the number 47 in base 10, whose equivalent in binary base is

01011112 is transformed to the Gray coding resulting in the number
111000GRAY in Gray code.
The iterative network that will be designed will perform conversion
of Gray encoding number to a binary encoding number.
The process begins with the use of the leftmost digit.
The result of the operation carried out by the leftmost cell is obtained
by entering the value 0 in the secondary input and comparing this entry with
the value of the primary input of the cell.
Because the first cell start with a value 0 this condition is indicated
with a * in the secondary entrance with value 0, showing that this is the
initial value of the first cell of the network.
If the value of the primary input is 0 the value of the secondary entry
is maintained and displayed in the main output and in the secondary output.
If the value of the primary input is 1, the value of the secondary input
is inverted and presented in primary and secondary outputs, transferring this
result to the next cell
The inputs and outputs Symbols table is presented below:

Binary numbers are assigned to each of the states.

In the case of relays is necessary that the binary numbers assigned to
each of the states has only one bit with value 1.

The Karnaugh maps for the secondary outputs and output are as
follows:

The Boolean forms obtained from the Karnaugh maps are as follows:
 The circuit of the standard cell constructed with relays is shown
below. The cell does not have any relay inside.
Because the binary number of the association to each of the states
contain only one binary digit with value 1, it is always possible to obtain a
Boolean form for each of the secondary outputs such a way that do not
appear inverted input variables.
The only variable that may appear reversed is the main input variable
epi. This is the variable that controls the cell through the epi relay.
The contacts of the epi relay, which will perform Boolean forms of
secondary variable, are normally open type when the ep variable appears
not reversed and will be of the type normally closed when the ep variable
appears reversed.

In circuits constructed with relays a signal connection to the

ground is regarded as one logical. A contact that does not have a connection
to the ground (open) is considered as logic 0.
The first cell far left receives on its inputs a and b values 0 and
1 as this is the initial state for the Gray code converter circuit for binary
number.
So as b gets the value 1 this secondary input of the first cell
must be connected to earth. The secondary input a receives a 0 value then it
will be maintained opened.
 Below is a circuit with six cells capable of converting the
number 111000GRAY to a binary number which it’s known have the value
1011112.
The initial value marked with * is shown in the leftmost cell a =
0 and b = 1
As the value 1 in the logic with relays is represented by ground,
b input receives a ground signal and the input a remains open.
The relays of 6 cells are operated when the value of the GRAY
numerical digit has value 1 and are not operated when the value of the digit
has GRAY numeric value 0.
At s p i outputs a value of 1 will result if the output presents an
earth sign, otherwise, if the output presents an open signal the value is 0.

As can be observed the circuit present the correct values at their

outputs.

Example 7: Adder using Relay Circuit

It will be repeated the example 1 using only the adder part to

demonstrate the iterative network construction method using two relays per
cell.
The initial table to be attended by the circuit is shown below where e
and f states are indicated:
e=carry=0
f=carry=1
 One of the states should be chosen for the first cell.
Usually the first cell receives carry signal 0.
The combination of values to the variables e and f can only
have a binary digit with value 1.
Thus e = 01, f = 10.
The table with the binary values already assigned is shown below:

The Karnaugh maps for the four variables a, b, c (n-1) that is a b

c d are presented below.
Soon after each of Karnaugh maps it is shown the Boolean form
that performs the function.
 The electrical circuit, using relays, for the standard cell is
shown below.
Note that although the variable c-n (carry-n) is an internal
variable to the process, in the last cell it must be available for a possible
circuit that needs this information.
Thus a specific circuit for this output variable also exists in the circuit.
 The relay contact is a bidirectional circuit, so if the ground signal at the
input is transferred to an output, the same signal may return through another
contact that connects the said output to another input, coupling the ground
signal to that input.
This results in an entry that had no ground signal begins to behave as if
it had this sign, including transferring it to the previous cell.
In the previous example this did not happen because the contacts were
complementary clearing a path as it closed another.
But at adder circuit there are two primary inputs, which use two
relays resulting in a high number of return paths from outputs to the inputs c
and d
To solve this problem diodes which are unidirectional for
continuous voltage signals, are used, avoiding that the ground signals on the
outputs are transferred to the inputs.
Problems to be solved

1) Assuming that the correct reception of the bits in a byte results in a 1

value at the output when the number of bits having value 1 in one byte is
odd, develop an iterative network circuit using relays using one cell for
each bit.

2) Develop a circuit using iterative network that executes only the sum of a
digit of binary numbers using logic gates.

3) Repeat the problem number 2 developing a relay circuit.

4) Develop a circuit using iterative network that presents an output value of

1 when in a byte there are exactly two bits with value 1.
Present a circuit using logic gates.

5) Develop a circuit using iterative network that present at its output a value
of 1 when in a byte there are exactly two adjacent bits with value 1. Present
a circuit using logic gates.

6) Build a circuit using iterative network that compares two bytes A and B,
providing three output signals A = B, A> B and A <B.
In the last cell the three outputs must be available.
In every standard cell should be two primary inputs to the bits of bytes A
and B.
Present a circuit for the standard cell using logic gates.

7) Build a circuit using iterative network that compares two bytes A and B,
and presents a value 1 at the output when exactly two bits are different.
Present a circuit for the standard cell using logic gates.

8) Build a circuit using iterative network that presents at its output a value
of 1 when in the byte there are two non-adjacent groups of exactly two
adjacent bits with a value of 0.
Present a circuit for the standard cell using logic gates.
9) Build a circuit using iterative network that presents at its output a value 1
when a byte not have two 0 or two adjacent 1.
Present a circuit for the standard cell using logic gates.
 Chapter 11
Transients and Hazards in Switching Circuits

In previous chapters combinational circuits were studied in the

analysis and synthesis using minimum cost ones, but always analyzing the
stable states. At no time were studied transitions, that is, behavior when the
output of the input changes state from 0 to 1 or 1 to 0.
In an ideal circuit any change of state of the inputs should result in a
stable output. It will remains in the same state or change from 0 to 1 or 1 to
0 immediately.
In this chapter it is assumed that both logic gates and relays have a
reaction time, namely a time of propagation.
When an input of a logic gate circuit changes, the new result at the
output will appears with a delay of few nanoseconds.
In the case of small relays the time of reaction is of the order of 2
milliseconds.
As in a circuit usually there are several parallel signal propagation
paths, it may happen that one of the signals present in an entry of the last
circuit before other signs and produces an improper result momentarily.
.In the case of relays there is the possibility of contacts open or close
late in relation to each other in the same relay.
For example, contacts that are opening may open before the contacts
are closing, or vice versa.
These improper signals appearing during a short moment at the
output may be important or not.
For example, if the output is being used to light a lamp or charge or
discharge a capacitor, an undue sign of nanosecond order in the case of
logic gates or milliseconds in case of relay does not matter.
But if the output is being used as a trigger command of a memory
element, this signal will cause an improper triggering, i.e. an error in the
circuit.
This error is not a failure of the components used to build the circuit,
but actually one generated by the different propagation times of the various
paths that the signals travel in the circuit.
For the development of the analysis it will be supposed that each
element of the circuitry has time to propagate the signal, but it will also be
assumed that the output of one element changes from one state to the other
only once when commanded.
This feature of the outputs is termed the absence of oscillations, or
more commonly output “free of bounce".
Although the existence of "bounce" is more common in relay
contacts, at high-speed circuits with logic gates, if the printed circuit boards
are not well-designed, may arise fluctuations in output during transitions
from 0 to 1 or from 1 to 0.
These oscillations are called "overshoot" in the case of transitions
from 0 to 1 and "undershoot" in the case of transitions from 1 to 0.

So in the studies in this chapter it is supposed absence of "bounce" in

the output due to the inappropriate behavior of each element or electrical
device as relays that make up the circuit, and will be considered only the
propagation times.
It will also be supposed that a change in an input variable is free of
"bounce".
And also that the entries remained stable until occurs a stabilization of
the output in the new state.

Types of Hazards
 There are two possible error or hazard occurring in combinational
circuits:
a) Static Hazard
b) Dynamic Hazard

Static Hazards

The hazard is called static when a change in an entry should not cause
any change in the output, i.e., the state at the output should not be altered
due to the change in input value, and results in a momentary peak with a 0
value or 1 value.
In this case we have two types of static hazard:
a) 0 Static Hazard
b) 1 Static Hazard

For 0 static hazard, the output shows zero, and after the input change
the output must continue to show zero, i.e. the input change of state should
not modify the state of the output. The hazard appears as a brief undue
presence of the value 1 in the output.

For 1 static hazard, the output shows one, and after the input change
the output must continue to show one, i.e. the input change of state should
not modify the state of the output. The hazard appears as a brief undue
presence of the value 0 in the output.
 These improper values are called "glitch". In many cases the signal
does not have full amplitude, namely, the signal does not reach the value of
Vcc, in the case of 0 static hazards or does not reach the ground level in the
case of a 1 static hazards.
But even in these conditions the signal can command the next circuit
that receives the signal of this output.

Dynamic Hazards

In the case of dynamic hazard the output shows a "bounce" in the

event of a transition from 0 to 1 or from 1 to 0. The output should come out
of one of the states and take over the new state without the occurrence of
"bounce", but due the hazard the output changes state, returns for a brief
period to the previous state and then assume the correct state.
The following figure shows the presence of "bounce", i.e. a dynamic
type hazard on an output which has a falling edge transition.

The following figure shows the presence of "bounce" i.e., a dynamic

type hazard in a rising edge transition.
Circuits that present Static Hazards

Static 0 Hazard in logic gates circuit

Circuit using logic gates

 Due to the propagation time of the inverter gate a small propagation
delay occurs at the entrance b that generate b\ at the input of the OR gate
that also receives input c.
When the input b = 0, at the inverter gate its output has a value of 1.
When the b input changes to value 1, the value 1 immediately appears
on the input of OR gate, which also receives the input a, producing at the
output of this OR a value of 1 before the other OR gate, which also receives
input c present a value of 0 at its output due to the propagation time of the
inverter gate, which continues for a short period of time to present a value
of 1 in its output.
So for a short period of time the gate AND at the output receives on
its inputs two values 1, and presents at its output a value of 1 for a short
period of time generating a "glitch" with value 1. In the waveforms the
"glitch" is presented with retardation due to the propagation time of other
logic gates.

Static 1 Hazard in logic gates circuit

Circuit using logic gates

 Due to the propagation time of the inverter gate a small propagation
delay occurs at the entrance b that generate b\ at the input of the AND gate
that also receives input c.
When the input b = 1, at the inverter gate its output has a value of 0.

When the b input changes to value 0, the value 0 immediately appears

on the input of AND gate, which also receives the input a, producing at the
output of this AND a value of 0 before the other AND gate, which also
receives input c present a value of 1 at its output due to the propagation
time of the inverter gate, which continues for a short period of time to
present a value of 0 in its output.
So for a short period of time the gate OR at the output receives on its
inputs two values 0, and presents at its output a value of 0 for a short period
of time generating a "glitch" with value 0. In the waveforms the "glitch" is
presented with retardation due to the propagation time of other logic gates.

Static 0 Hazard in Relay Circuits

Circuit using relays.

 Due to constructive aspects the relay can have four possible output
results
1) A normally open contact closes before a normally closed contact opens.
2) A normally closed contact opens before a normally open contact closes.
3) A normally open contact opens before a normally closed contact closes.
4) A normally closed contact closes before a normally open contact opens.
In the waveforms presented the four hypotheses are covered. We note
that in cases 1) and 4) hazard occurs in the generation of the output of the
circuit.
So for a short period of time the circuit output results in a ground
value due to relay b present the normally open contact closed and the
normally closed contact also closed.
So for a short period of time both b relay contacts are closed and
present at its output a ground value, generating a "glitch" of ground on the
circuit output.

Static 1 Hazard in Relay Circuits

Circuit using relays.

 Due to constructive aspects the relay can have four possible output
results
1) A normally open contact closes before a normally closed contact opens.
2) A normally closed contact opens before a normally open contact closes.
3) A normally open contact opens before a normally closed contact closes.
4) A normally closed contact closes before a normally open contact opens.
 In the waveforms presented the four hypotheses are covered. We note
that in cases 2) and 3) hazard occurs in the generation of the output of the
circuit.
So for a short time interval output of the circuit results in an open
amount due to the relay b present the normally open contact, open and
normally closed contact also open
So for a short period of time both b relay contacts are open and
feature in its output an open value, generating a "glitch" of an open circuit
at the output.

Dynamic Error Rising Edge – Logic Gates

Circuit using logic gates

 Due to the propagation time of the inverter gate a small propagation
delay occurs at the entrance b that generate b\ at the input of the AND gate
that also receives input c.
When the input b = 1, at the inverter gate its output has a value of 0.
When the b input switches to 0, the value 0 appears immediately in
the input of the AND gate that also receives in its input a, producing at the
output of this AND a value of 0 before another AND gate that receives in
its input the variable c presents a value 1 at the output, due to the
propagation time of the inverter gate, which continues for a short period of
time to present a value of 0 on its output.
So for a short period of time the OR gate at the output of the two ports
AND receives on its two input 0 values, and presents at its output a value 0
for a short time interval generating a "glitch" with value 0 in the gate output
OR.
 But due to the fact that the output of Inverter gate enters at the last
gate of the circuit, the output of the inverter gate presents a 1 value at the
input of the last AND gate, before the signal propagates through the
intermediate AND and OR gates of the circuit.
The last gate receives two signals with 1 value before the “glitch”
appears at the output of the OR gate, with a value 1 at the output.
When then the result of the "glitch" appears in the output of the OR
gate, results in a temporary value 0 in the output, and when this "glitch"
output disappears finally the correct 1 value results.
The explained behavior causes a "bounce" of rising edge transition in
the circuit output.

Dynamic Error Falling Edge – Logic Gates

Circuit using logic gates

 Due to the propagation time of the inverter gate a small propagation
delay occurs at the entrance b that generate b\ at the input of the OR gate
that also receives input c.
When the input b = 0, at the inverter gate its output has a value of 1
When the b input switches to 1, the value 1 appears immediately in
the input of the OR gate that also receives in its input a, producing at the
output of this OR a value of 1 before another OR gate that receives in its
input the variable c presents a value 0 at the output, due to the propagation
time of the inverter gate, which continues for a short period of time to
present a value of 1 on its output.
So for a short period of time the AND gate at the output of the two
ports OR receives on its two input 1 values, and presents at its output a
value 1 for a short time interval generating a "glitch" with value 1 in the
gate output AND.

But due to the fact that the output of Inverter gate enters at the last
gate of the circuit, the output of the inverter gate presents a 0 value at the
input of the last OR gate, before the signal propagates through the
intermediate OR and AND gates of the circuit.
The last OR gate receives two signals with 0 value before the “glitch”
appears at the output of the AND gate, presenting a 0 value at the output.
When then the result of the "glitch" appears in the output of the AND
gate, results in a temporary value 1 in the output, and when this "glitch"
output disappears finally the correct 0 value results.
The explained behavior causes a "bounce" of falling edge transition in
the circuit output.

Dynamic Error Falling Edge – Relay Circuit

Circuit using relays.

To perform the mapping it was considered that the d relay operates

when b operates. In static terms the b and e variables can be considered the
same.
 Thus, the variable b appears in place of the d variable and it appears
also representing itself.

Due to constructive aspects the relay can have four possible output
results
1) A normally open contact closes before a normally closed contact opens.
2) A normally closed contact opens before a normally open contact closes.
3) A normally open contact opens before a normally closed contact closes.
4) A normally closed contact closes before a normally open contact opens.

The D is an auxiliary relay in the circuit.

This auxiliary relay in its operation causes a much greater
propagation delay than any contact that closes before another opens or vice
versa.
Then the waveform shows the two possibilities of delay between relay
contacts D. We note that only the hypothesis 1) generates "bounce" in the
output. The two contacts of a and c relays are open in the example. Thus the
output is determined by the normally closed relay contact of relay b and the
two series contact of relay d.
When the relay b operates, the relay d has not had time to operate.
Thus the contact b \ opens and the output shows the open result. When the
relay d acts the hypothesis 1) says that the normally open contact closes
before, resulting in a short ground in output.
Then contact d normally closed opens and the output finally presents
the correct result of normally open.
0 in the relay logic is open at the output. 1 in the relay logic is short to
ground.
In the graphs of the waveforms it is observed the previous stable
situation with ground in output presented as 1 value.
Then a state with value 0, indicating an open state at the output, then
again a ground at the output with value 1 at the graphs and then the return to
steady state with value 0 in the output, presenting in this case dynamic
hazard type falling edge transition.

Dynamic Error Rising Edge – Relay Circuit

Circuit using relays.

 Due to constructive aspects the relay can have four possible output
results
1) A normally open contact closes before a normally closed contact opens.
2) A normally closed contact opens before a normally open contact closes.
3) A normally open contact opens before a normally closed contact closes.
4) A normally closed contact closes before a normally open contact opens.
The d is an auxiliary relay in the circuit.
 This auxiliary relay in its operation causes a much greater propagation
delay than any contact that closes before another opens or vice versa.
Then the waveform shows the two possibilities of delay between relay
d contacts.
We note that only the hypothesis 3) generates "bounce" in the output.
The two contacts of a and c relays are closed in the example. Thus the
output is determined by the normally closed relay contact of relay b that is
in series configuration with two contacts of d relay that are in parallel
configuration.
When the relay b is de energized, the relay d doesn’t have had time to
de energized yet.
Thus the contact b \ closes and the output shows the closed result, i.e.
a ground at the output.
When the relay d opens the hypothesis 3) says that the normally open
contact opens before the contact normally closed closes, resulting in an
open at the output.
Then contact d normally closed closes and the output finally presents
the correct result of normally closed.
0 in the relay logic is open at the output.
1 in the relay logic is short to ground.
In the graphs of the waveforms it is observed the previous stable
situation with open in output presented as a 0 value.
Then a state with value 1, indicating an closed state at the output, then
again an open at the output with value 0 at the graphs and then the return to
steady state with value 1 in the output, presenting in this case dynamic
hazard type rising edge transition..

Detecting Static Hazards

Initially we present the Karnaugh maps for two circuits. The first
circuit is represented by the Karnaugh maps a) and b) and the second circuit
by the maps c) and d).
In Karnaugh maps are shown the cells of order 0 covered by the cells
of order 1.
Constructing a Boolean form using the cells of order 1 that cover the
cells of order 0 that present the value 1 for the function it will result in a
Boolean form for the function.
 Constructing a Boolean form using the cells of order 1 that cover the
cells of order 0 that present the value 0 for the function it will result in a
Boolean form for the function.
The shown Karnaugh Maps for the two circuits have static hazards
because there are cells of order 1 adjacent, and there aren’t any cells of
order 1 or greater that cover the terms of order 0 of these cells that are
adjacent.
It’s is called adjacent, two cells of order 0 that have the same value 0
or 1, and that are defined by variables that has a different value at only one
variable.
When two cells adjacent of order 0 with the same value for the
function, are not covered by a single cell of greater order, can occur when
the state change of the input variable value that is different for the two cells
order 0 a static error.
In all four examples of maps are cells of order 0 that have the same
value 0 or 1 to function, and that are adjacent and differ only in the value of
the input b.
But these two cells of order 0 are not covered by any cell of order 1 or
greater at the same time.

Analyzing the circuit a) we find that there is no term of Boolean

formula covering both cells of order 0 with 0 value, 000 and 010.
So in this case when the variable b changes state from 0 to 1 or from
1 to 0, there is the possibility of occurrence of a static error.
 For the circuit b) the same occurs between the cells of order 0 with 1
value, 101 and 111, when the variable b changes state from 0 to 1 or 1 to 0.

Similarly to the circuit c), the same occurs between cells of order 0
with 0 value, 000 and 010, when the b variable changes state from 0 to 1 or
from 1 to 0.
Finally for the circuit d) the same occurs between cells of order 0
with 1 value, 101 and 111, when the b variable changes state from 0 to 1 or
1 to 0.

Preventing Static Hazards using Karnaugh Maps

To avoid the existence of adjacency between terms with values 1 or 0

that do not have a term covering both adjacent cells simultaneously, it is
necessary to add terms capable of covering simultaneously the adjacent
cells of order 0.
Below are presented Karnaugh Maps where new terms where added.
These terms cover simultaneously the cells of order 0 adjacent that have the
same value 0 or 1.

In the new Karnaugh maps it can observed the terms added so that
there is no adjacency between sets of 0s or 1s with cells of order 0 not
covered simultaneously.
In the Boolean form type product of sums it was added the term (a+ c)
with value 0.
In the Boolean form type sum of product it was added the term (a. c)
with value 1.
These new sets added provide a new path between the inputs and the
output of the circuit in order to maintain the result 0 or 1 at the output when
a input variable, in case variable b, change the state from 0 to 1 or from 1 to
1.

Preventing Static Hazards using Quine McCluskey Algorithm

For circuits with more than six variables the method of Karnaugh
maps is difficult to apply. In this case Quine McCluskey algorithm is used.
It is necessary to make changes to the algorithm so as to avoid the
occurrence of static errors.
The necessary changes are presented using an example to generate a
circuit that will execute a sum of products circuit type.
The mapping for the functions is presented below:
 The terms such as "don’t care" are marked with an X in the mapping.
Throughout the process continues these terms being marked with an X
following the order of cell number 0.
The construction of Coverings table is modified so that the columns
of the table lists the pairs of cells order 0 adjacent which make up the cells
of order 1 that result in value 1 for the function. (or 0 if it’s desired a form
type Product of Sums).
The prime implicants terms are given in table rows.

Only are marked with crosses the terms order 0 in the columns that have
both cell order 0 adjacent covered by the prime implicant term listed in the
row.
Boolean form generated by the algorithm is displayed just below the
covering table.
With modifications to the Quine McCluskey algorithm, this method
ensures that all adjacent cells order 0 making up the 1 cell, are covered
simultaneously by a term that covers both adjacent cells of order 0.
As the function used in the example has only four variables it is
possible to construct a Karnaugh map to perform a comparison of results. It
can be seen that the result does not allow the occurrence of static errors for
all possibilities of adjacent cells order 0
Disjunctive Forms Theorem

If a switching combinational circuit consists of logic gates or relays is

run directly from a disjunctive normal form (sum of products) that is,
without modifications or additional mathematical operations after obtaining
using Karnaugh maps or Quine McCluskey algorithm and is already
contemplated in Boolean form additional terms necessary so that all
adjacencies between order 0 cells with the same 1 value for the function
does have a term that covers those cells simultaneously, thus ensuring that
there will be no static errors of type 1, this circuit is also free of static errors
of type 0 and dynamic errors.

Proof:
In the composition of a disjunctive normal form it was found that this
algebraic form is composed of Boolean terms type product or reduced
product standards, but do not have the same variable in the non-
complemented and complemented form simultaneously on the same
product.
Furthermore, there is a set of cells of order 0 with value 1 which
corresponds directly to product type existing in disjunctive normal form.
It has been shown in previous sections of this chapter that the circuit
constructed according to the statement of the theorem is free of static errors
of type 1.
Now we will prove that this circuit is also free of static errors of type
0.
Let's look at two cells 0 order adjacent that result in 0 for the
function.
 These two adjacent cells have difference in one input variable. For
example, cells 011 and 010 differ in the variable c which changes from 1 to
0 or 0 to 1.
But the adjacent cells that result in value 1 for the function 111, 110
differ with the cells that result in a value of 0 to the function in the variable
a But the variable “a” it’s not having its value changed when the c variable
is changing from 0 to 1 or from 1 to 0.
So changing the cells 011 and 010 will not generate any possibility of
a value of 1 for the function, i.e. possibility of generating any static hazard
type 0.

It remains to prove that the circuit constructed according to the

statement of the theorem is also free of dynamic errors.
To be a change in the output value of the circuit 1 to 0 or 0 to 1 an
input variable between two adjacent cells, which generate different values
for function, should change its value.
So let's assume that the circuit input variables have the value 111
resulting in its output the value 1. Now let's change the “a” variable to 0,
i.e. we will be migrating from cell 111 to the cell 011.
To originate a dynamic error during change the original cell to the
new cell would have to generate an output value of 0 and then present a
"glitch" with value 1, and finally the function to stabilize its output to 0.
For this to happen the change of the variable would have to have a
"bounce" when the change in value occurs. This is the opposite of what was
established that the input variable changes are free of "bounce".
As this hypothesis has been eliminated, then the circuit would have to
hold a temporary passage through a cell that results in a value of 1 for
function.
 But for this happen, another input variable needs to have its value
modified in order to permit an intermediate passage by a cell that could
result in value 1 for the function.
But as only one input variable is undergoing change at a certain
moment this does not occur.
Thus it is proved that the circuit constructed in accordance with the
statement of the theorem is also free of dynamic errors.

Conjunctive Forms Theorem

If a switching combinational circuit consists of logic gates or relays is

run directly from a conjunctive normal form (product of sums) that is,
without modifications or additional mathematical operations after obtaining
using Karnaugh maps or Quine McCluskey algorithm and is already
contemplated in Boolean form additional terms necessary so that all
adjacencies between order 0 cells with the same 0 value for the function
does have a term that covers those cells simultaneously, thus ensuring that
there will be no static errors of type 0, this circuit is also free of static errors
of type 1 and dynamic errors.

Proof:

In the composition of a conjunctive normal form it was found that

this algebraic form is composed of Boolean terms type sum or reduced sum
standards, but do not have the same variable in the non-complemented and
complemented form simultaneously on the same sum.
Furthermore, there is a set of cells of order 0 with value 0 which
corresponds directly to sum type existing in conjunctive normal form.
It has been shown in previous sections of this chapter that the circuit
constructed according to the statement of the theorem is free of static errors
of type 0.
Now we will prove that this circuit is also free of static errors of type
1.
Let's look at two cells 0 order adjacent that result in 1 for the
function.
 These two adjacent cells have difference in one input variable. For
example, cells 100 and 101 differ in the variable c which changes from 1 to
0 or 0 to 1.

But the adjacent cells that result in value 0 for the function 000, 001 differ
with the cells that result in a value of 1 to the function in the variable a
But the variable “a” it’s not having its value changed when the c
variable is changing from 0 to 1 or from 1 to 0.
So changing the cells 100 and 101 will not generate any possibility of
a value of 0 for the function, i.e. possibility of generating any static hazard
type 1.

It remains to prove that the circuit constructed according to the

statement of the theorem is also free of dynamic errors.
To be a change in the output value of the circuit 1 to 0 or 0 to 1 an
input variable between two adjacent cells, which generate different values
for function, should change its value.
So let's assume that the circuit input variables have the value 001
resulting in its output the value 0. Now let's change the “a” variable to 1,
i.e. we will be migrating from cell 001 to the cell 101.
To originate a dynamic error during change the original cell to the
new cell would have to generate an output value of 1 and then present a
"glitch" with value 0, and finally the function to stabilize its output to 1.
For this to happen the change of the variable “a” would have to have
a "bounce" when the change in value occurs. This is the opposite of what
was established that the input variable changes are free of "bounce".
As this hypothesis has been eliminated, then the circuit would have to
hold a temporary passage through a cell that results in a value of 0 for
function.
 But for this happen, another input variable needs to have its value
modified in order to permit an intermediate passage by a cell that could
result in value 0 for the function.
But as only one input variable is undergoing change at a certain
moment this does not occur.
Thus it is proved that the circuit constructed in accordance with the
statement of the theorem is also free of dynamic errors.

Problems to be solved

1) Verify if the following circuit presents static 0 or static 1 hazard.

If the circuit has static hazard present a new circuit without hazards
using logic gates.

2) Verify if the following circuit presents static 0 or static 1 hazard.

If the circuit has static hazard present a new circuit without hazards
using relays.
3) Verify if the following circuit presents static 0 or static 1 hazard.
If the circuit has static hazard present a new circuit without hazards
using relays.

4) Verify if the following circuit presents static 0 or static 1 hazard.

If the circuit has static hazard present a new circuit without hazards
using logic gates.
5) Verify if the following circuit presents static 0 or static 1 hazard.
If the circuit has static hazard present a new circuit without hazards
using logic gates.

6) Verify if the following circuit presents static 0 or static 1 hazard.

If the circuit has static hazard present a new circuit without hazards
using logic gates.

7) Verify if the following Boolean form presents static 0 or static 1 hazard.

If there are hazard, present a new Boolean form without hazards.
Show a circuit that executes the new Boolean form.

8) Verify if the following Boolean form presents static 0 or static 1 hazard.

If there are hazard, present a new Boolean form without hazards.
Show a circuit that executes the new Boolean form using logic gates.
9) Using Karnaugh Maps Method verify if the following circuit presents
static 0 or static 1 hazard.
If the circuit has static hazard present a new circuit without hazards
using logic gates.

10)Using Karnaugh Maps Method verify if the following circuit presents

static 0 or static 1 hazard.
If the circuit has static hazard, uses Quine McCluskey Algorithm and
present a new circuit without hazards using logic gates.

11)Using Karnaugh Maps Method verify if the following circuit presents

static 0 or static 1 hazard.
If the circuit has static hazard present a new circuit without hazards
using relays.
12)Using Karnaugh Maps Method verify if the following circuit presents
static 0 or static 1 hazard.
If the circuit has static hazard present a new circuit without hazards
using relays

13)Using Karnaugh Maps Method verify if the following circuit presents

static 0 or static 1 hazard.
If the circuit has static hazard, using Quine McCluskey Algorithm
presents a new circuit without hazards using logic gates.
14)Verify if the following Boolean form presents static 0 or static 1 hazard.
If there are hazard, present a new Boolean form without hazards.
Show a circuit that executes the new Boolean form using logic gates.

15)Verify if the following circuit presents static 0 or static 1 hazard.

If the circuit has static hazard present a new circuit without hazards
using relays.

16)Verify if the following circuit presents static 0 or static 1 hazard.

If the circuit has static hazard present a new circuit without hazards
using relays.

17)Verify if the following circuit presents static 0 or static 1 hazard.

If the circuit has static hazard present a new circuit without hazards
using relays.
18)Verify if the following circuit presents static 0 or static 1 hazard.
If the circuit has static hazard present a new circuit without hazards
using relays.

19)Verify if the following circuit presents static 0 or static 1 hazard, or

dynamic hazards rising or falling edge.
If the circuit has static or dynamic hazards present a new circuit without
hazards using relays.
20)Verify if the following circuit presents static 0 or static 1 hazard, or
dynamic hazards rising or falling edge.
If the circuit has static or dynamic hazards present a new circuit without
hazards using relays.

21) For the Function represented in the summary form, use the Quine
McCluskey Algorithm to generate a circuit using logic gates type OR of
ANDs, without static or dynamics hazards.
Verify the results using Karnaugh Maps Method.

F[1]={0,1,2,3,4,5,6,9,12,13}

22) Repeat the previous problem generating a circuit type AND of ORs.

23) For the Function represented in the summary form, use the Quine
McCluskey Algorithm to generate a circuit using logic gates type OR of
ANDs, without static or dynamics hazards.
Verify the results using Karnaugh Maps Method.

F[1]={0,2,3,7,8,12,13,15}
F[X]={1,9}

24) Repeat the previous problem generating a circuit type AND of ORs.

25) For the Function represented in the summary form, use the Quine
McCluskey Algorithm to generate a circuit using logic gates type OR of
ANDs, without static or dynamics hazards.
Verify the results using Karnaugh Maps Method.

F[1]={0,2,4,6,13,14,15}
F[X]={9,10}

26) Repeat the previous problem generating a circuit type AND of ORs

27) For the Function represented in the summary form, use the Quine
McCluskey Algorithm to generate a circuit using logic gates type OR of
ANDs, without static or dynamics hazards.
Verify the results using Karnaugh Maps Method
F[1]={0,1,6,12,13,16,17,20,24,28,29,31}
F[X]={7,14,15,21,23}

28) Repeat the previous problem generating a circuit type AND of ORs
 Chapter 12
Threshold Gates

This chapter is the last part of the book devoted to combinational

circuits. In this chapter we introduce some types of technologies that use
devices which work with comparison levels.
It will be presented devices that not necessarily are fully digital
devices.
But they are used as an interface between an external process and the
digital circuit, or perform functions that assist in digital circuits.

Ferrite Rings

Until the end of the 1970s many computers used memories that used
ferrite rings as memory elements.
It is shown in this section the operation of this type of device.
Below the image of a ferrite ring:

A ferrite is a ceramic material containing metallic iron particles

therein. As a ceramic, it can be shaped in different sizes and shapes.
The ferrite possesses magnetic property.
It can be polarized by a magnetic field, guiding the magnetism of its
particles.
In the case of a ferrite ring we can orient their particles through a
magnetic field clockwise or counterclockwise.
The following is the magnetic flow density curve on the vertical axis
versus magnetic field intensity applied on the horizontal axis.
 The magnetic materials, including the ferrites do not have a linear
curve between the intensity of the magnetic field applied by means of a
current injected into a winding composed of copper wire turns and the flux
density which arises inside the material.
The curve presented shows that the flux density only jumps to a
positive value above Br + when the intensity of the magnetic field reaches a
value above Hc + (positive coercive force).
If the magnetic field is zero the flux density remains in the residual
flux density value (Br +).
To the flux density jumps to a negative value below Br- it is necessary
that the intensity of the magnetic field applied reaches a value below Hc-
(negative coercive force)
Again if the magnetic field is zero the flux density remains in the
residual flux density value Br-.
Thus we can observe that the ferrite has the property of maintaining a
positive or negative residual flux density even when there is no magnetic
field applied through a current in a winding composed of copper wire turns

Magnetic Core Memory – Ferrite Ring Memory

This property allows the use of ferrite rings as memory elements.

When the residual flux density is positive a bit with value 1 is stored.
When the residual flux density is negative a bit with value 0 is stored.
 This residual flux density is due to the orientation of iron particles
within the material due to applied magnetic field which remain oriented in
the clockwise or counterclockwise even after reset the intensity of the
external magnetic field.
If using an additional winding composed of copper wire turns, we
observe a positive or negative current in the coil when the flux density
changes from Br- to Br+ or the other way around.
Therefore to check if there is a bit with value 1, a negative magnetic
field intensity, more negative than Hc-(negative coercive force), is applied
and it is observed the additional winding.
If it is observed a current due to the change from positive to negative
flux density it can be concluded that there was a bit of value 1 stored.
But this operation destroys the value 1 of bit stored
Thus an opposite operation is necessary to rewrite the bit with value
1.
If the stored bit was a 0 value, this rewriting operation it is not
necessary.

Explained the characteristics of the ferrite element and its magnetic

properties capable of storing the value of a data bit, a new construction will
now be proposed for the element using ferrite ring.
The windings consist of copper wire on the toroid shape core are
separated into two identical coils A and B. A third winding C will be used
to check the change of direction of the magnetic flux
This third winding is used to check the value of the stored bit.
Using two winding, it is necessary only half of the total current,
applied to each winding, to generate a sufficient magnetic field strength to
produce a change in flux density from positive to negative or other way
around.
 Established that to write it is necessary that the two current, half in
each winding, needs to be summed, it will be suggested the structure shown
below for the construction of a memory array capable of storing four bits.
The current A is applied to the first column. Current B is applied to
the first line and the winding C is read at the cross.
Using this structure it is possible to extend the same for a very large
number of bits equal to the number of columns multiplied by the number of
lines

As quoted at the beginning of this section this structure was used for
the construction of computer memory until the end of the decade of 1970.
The winding of each of ferrite rings was constructed using only one
wire that was passed through the center of the ring. The rings had
dimensions of the order of millimeters.
It is important to note that to achieve a result, that is digitally storing a
0 or 1 value in a bit memory, it is required that two current half-value are
combined in one element.
The equation that represente this operation is:

Two Levels Comparator – Schmitt Trigger

The comparator circuit with two levels was developed by Otto

Herbert Schmitt in 1934.
The circuit became known as Schmitt Trigger.
 Assuming a logic circuit powered by DC voltage Vcc. For the circuit
recognizes the input signal as a logical value 1, it is necessary that the
voltage at its input is greater than a value V1.
After the recognition of input as logic 1, the comparison value for the
input signal to be recognized as logical level 0 became V2.
V2 has a smaller value than the value V1.
If the input signal goes to a smaller value than V2 the output will go
to Vcc, and the comparison value became V1 again that is a greater value
than V2.
The transfer curve executed by the circuit is shown in the following
graphic
At the horizontal axis shows the voltage at the input. And the vertical
axis presents the voltage at the output.
The difference value between the values V1 and V2 is called the
hysteresis voltage.

The chart below shows the characteristics of a wave connected to a

digital input Ve with characteristics of a Schmitt trigger.
Also it is presented the characteristics of the wave that will appear at
the output Vs.
 Many integrated circuits, logic gates or other more complex functions
have in their input Schmitt Trigger circuits in order to prevent noise or
"bounces" to enter in the internal circuit and that could result in a failure in
the logic function executed by the circuit.
The circuit shown below is called comparison circuit.

This circuit has two inputs called V+ and V.

When the voltage applied to V+ is greater than the applied voltage V-,
the output will present a value Vcc that is equal to the power supply value.
When the applied voltage at input V- is greater than the applied
voltage at V+ the output will present a result of 0 Volts, i.e., ground.
The following is a circuit using a comparator that has two comparison
levels.
The circuit performs the function of an inverter gate.
When the input voltage Ve has value 0 the output Vs shows the
voltage value of Vcc. In this case, the RH resistor (Hysteresis resistor) is
presented in parallel with R1,as the output has value Vcc and RH resistor is
connected to the output.
In this case the voltage applied to the V+ terminal is given by:
V1 = (Vcc x10K) / (10K+5K) = 0,66xVcc
 When the input voltage Ve has value Vcc the output Vs presents 0
Volts. In this case the resistor RH is presented in parallel with R2 because
the output displays 0 Volts and RH resistor is connected to the output. In
this case the voltage applied to the V+ terminal is given by V2 = (Vcc
x 5K) / (10K+5K) = 0.33 x Vcc

It was shown the advantage of using circuits with entries that have the
characteristics of a Schmitt trigger, and how it is possible to implement this
type of input using a comparator circuit.

One Level Comparator

One of the uses of single level comparator is the implementation of

the below equation type:

The variables w (weight) are real numbers.

a, b, c are inputs that will receive logical levels 0V or 1 (Vcc).
T (Threshold) is the comparison level.
If the equation is true the logical result at the output will be the 1 logical.
If the equation is not true the logical result at the output will be 0 logical.
 The circuit shown is an example of a circuit that has a value 1 at its
output if two or more entries receive a 1 (Vcc) value.
It can be observed that the comparison level (threshold) has 0.5xVcc value.
At point X appears 0V, 0.33xVcc, 0.66Vcc or Vcc. When only one entry
receives Vcc the value at X will be 0.33xVcc, and the output will present a
logical 0 value.
When two entries receive a logical 1 (Vcc) the value at X will be 0.66xVcc
and the output will present a logical 1 value.
The symbol and the true table are shown below. The value that appears in
each entry is the weight that entry has in that circuit.
The value that appears at output is the comparison level (threshold).

OR Operation

The following presented circuit performs the OR operation.

 The comparison level is 0.2Vcc. It is enough that only one entry has 1
logical value to the function output present 1 logical.
The logical symbol for the operation is also shown.

AND Operation

The following circuit performs the operation AND.

The comparison level is 0.8Vcc. It is necessary that the three entries
have logical value 1 to the function output present 1 logic value.
The logical symbol for the operation is also shown.

Inverter Operation

The following presented circuit performs the inverter operation (Not)).

 To a 0 value in the input, result in a 0 value internally. This value is
greater than -0.5. Thus a logical value 1 appears at output. To a value 1 in
the input results in a -1 value internally. This value is smaller than -0.5.Thus
a logical 1 value appears at the output.
Together with the function AND and OR already presented a
complete Boolean algebra is implemented.

Comparator using Weighting Factors

The following presented circuit performs the function:

a x 4 + b x 2 + c x 1 > 4.5

The level of comparison is 0.64Vcc.

For each input unit the increase is 0.142Vcc.
Applying a logic value 1 at input a, and inputs b and c with logic
value 0 the result at point X is 0.57Vcc. For inputs a and c with logic value
1 and b input with logic value 0 the result at point X is 0.71Vcc.
So when the input has a greater numerical value than 4 the output will
present logic value 1.

Problems to be solved

1) Using ferrite rings design a memory that has the total capacity of 8
bytes, 8 bits each.
2) Using a two level comparator design a circuit that has a 0.7Vcc
comparison level at rising edge and 0.3Vcc comparison level at falling edge
in it input signal.

3) Using one level comparator design a circuit that executes the function of
a full adder.
The circuit will have three inputs: bit A, bit B, carry (n-1) and two outputs:
sum, carry n.

4) Design a circuit using a comparator with single level that has 4 inputs
with weights 1,2,4,8, and display output value 1 when the numerical input
value is greater than 9.