CMOS Integrated Circuits ELEC212

CMOS Integrated Circuits

REVISION + Design Assignment
Dr Ivona MITROVIC

Department of Electrical Engineering and Electronics

1
Re-cap & Plan Week 5
CMOS Inverter
Fabrication of CMOS
Week 1
Properties of Si
Weeks 6-7
Fabrication of CMOS.
Week 2 Layout and Design Rules
PN junction

Weeks 7-8
Week 3 CMOS Circuits
MOS capacitor Design Assignment
(3 weeks to complete)

Week 4
MOSFET
Lectures 6, 7-9 and 10 important for
Design Assignment.
CMOS Integrated Circuits. Revision ELEC212 2
Plan

Week 8
Advanced digital CMOS
circuits: pseudo n-MOS,
dynamic and domino logic

Week 9
Revision. Preparation for
Examination

Week 10
Q&A office hour session.
Design Assignment
submission 28th April

CMOS Integrated Circuits. Revision ELEC212 3

Design Assignment (2023)

You are required to design a simple CMOS circuit consisting of a two-

input NOR gate. You are required to show the layout (plan view) of the
circuit, after calculating the aspect ratio (W/L) of the transistors. The
layout of the circuit should include the VDD and ground lines.

Marks will be awarded for the calculations, the explanation of the

calculations, the layout, and the quality of the drawing of the layout.
You must also hand in, with the layout, a summary of your
calculations with full explanation.

Specification:
VDD=4V, |VT|=0.25V, Co=5x10-4 Fm-2, electron mobility 0.1 m2V-1s-1,
hole mobility 0.05 m2V-1s-1, minimum feature size 0.2 µm, maximum
alignment error 0.1 µm. The area of the circuit should be a minimum.

CMOS Integrated Circuits. Revision ELEC212 4

Remarks on DA requirements

ü Prepare your work on A4 fine-grid paper

or printed on A4 using one of the drawing software
programmes (CorelDraw, Microsoft Designer etc.)

ü Make sure to include LEGEND

(what is poly-, metal, n-well, n+ diffusion, p+
diffusion etc.)
+ SCALE (either µm or using l-rule)

CMOS Integrated Circuits. Revision ELEC212 5

On marking

50%: layout (2 pages MAX: 1 page layout + 1 page explanation

of design rules you used)
(basic 35%, -5% for non-catastrophic, and -10% for catastrophic
mis-alignment), design rules (10%), general extras (using
software, quality of drawing, using colours, originality, explanations
using various masks 5%)

50%: calculations (2 pages MAX)

(if all derivations correct with ratios W/L for p vs n correct 45%, 5% -
choice of ratios for actual design)
If all regimes of all transistors correct, but not followed further: 25%
If derivations done from design rules, then 25%.

CMOS Integrated Circuits. Revision ELEC212 6

 Vout
Hints to help you with DA calculations 1 2 3
Vout=Vin
A B

D
E
VTn VDD/2 VDD -|VTp|
Vin

Vth = Vin = Vout = VDD/2

Id3=Id4= 2Id1 Write the equations

for drain current
depending on if
Id1 = Id2 transistor works in
saturation or linear
regime.

You will get the number for this as (W/L)p = k(W/L)n, k is the ratio that is asked for you to
derive from calculations part of your Design Assignment.

The full derivation with choice of each Wn, Ln, Wp and Lp will give you score of 50%.

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What if I do not derive exact ratio between
(W/L)p and (W/L)n?

ü You can use approximate formula given in your Lecture notes 10.
It states that (W/L)p~2.5N(W/L)n for CMOS NOR circuit.

ü This means, the two pMOSFETs are in series then the size has to be Nx
bigger than the minimum size, and on top of that you need to account the
ratio of mobilities μn/μp, which is 2.5 in your Lecture notes 10.
ü Note that in your Design assignment, μn/μp = 2, then your approximate
formula is
(W/L)p~2x2x(W/L)n ~ 4(W/L)n

ü Then as an example, you can define Ln=Lp=2lambda, and

Wn=2Ln=4lambda, and Wp=8Lp=16lambda and this will conclude the
choice of the W and L for all transistors using approximate formula.

If you use approximate formula rather than derivation, you score 25%.
For the choice of Wn, Ln, Wp and Lp you score extra 10%.

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Drawing Design Assignment and DA rules

ü You are to draw it using ruler and graph paper; you need to specify
the grid either in lambda or micrometres. Or use drawing software
and specify grid and legend. Make sure to include correct spacing
between n-well, active regions, contacts, extension of polysilicon
gate over the active area, width and length of each transistor. The rule
of 5lambda from n-well to nMOSFETs active area assumes straight
line in figure 10a in your Lecture notes 7-9; also, the 3lambda is
surrounding the pMOSFET active area from n-well fully in the same
figure, so there is no confusion.

ü You do NOT need to calculate the area of your NOR circuit; just
choose the optimal min ratios as suggested above: Ln=Lp, Wn=2Ln
and Wp from your calculations or approximate formula.

ü Be creative!

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Reminder Example
a) Find the threshold voltage
(Vth) of the CMOS inverter in
Fig. P1. (W/L)p=1.8/0.6
Assume µn=545 cm2/Vs and
µp=130 cm2/Vs, VTn=0.8V,
VTp=-0.9V and VDD=3.3V.
b) What will be the value of Vth
if both transistors are of the
same size?
c) Calculate the Vth if
(W/L)p=4.2(W/L)n. (W/L)n=1.2/0.6

CMOS Integrated Circuits. Revision ELEC212 10

The threshold voltage of the inverter

Vth=Vin=Vout (W/L)p=1.8/0.6

Vout
1 2 3

A B
(W/L)n=1.2/0.6
C

D
E
VTn VDD/2 VDD-|VTp|
Vin

CMOS Integrated Circuits. Revision ELEC212 11

Solution
µ n Co W
I D -n = ( ) n (VGSn - VTn ) 2 =
2 L
µ n Co W
= ( ) n (Vth - VTn ) 2
2 L

µ p Co W µ p Co W
I D- p = ( ) p (VGSp - VTp ) =
2
( ) p (Vth - VDD - VTp ) 2 =
2 L 2 L
µ p Co W
= ( ) p (VDD - Vth + VTp ) 2
2 L

I D-n = I D- p

CMOS Integrated Circuits. Revision ELEC212 12

Solution

µ p (W / L) p
VTn + (VDD + VTp )
µ n (W / L) n
Vth = =
µ p (W / L) p
1+
µ n (W / L) n
= 1.40V

CMOS Integrated Circuits. Revision ELEC212 13

In summary…

In your Design Assignment, you are not calculating switching threshold, it

is known from the start that for optimal working of your circuit it should sit
in the middle where Vin=Vout=Vdd/2; this formula will help you to identify
the regimes of operation of individual transistors and then calculate the
ratio between pMOSFETs and nMOSFETs.

Then you proceed with drawing your design using design rules.

CMOS Integrated Circuits. Revision ELEC212 14

Further work – imp for your design!
v Calculate Vth for a NOR and NAND gate.

CMOS Integrated Circuits. Revision ELEC212 15