The design, simulation and characterisation of a class-B audio power

amplifier

G. Jolley
email [email protected]

March 12, 2017

Abstract
In this report I describe the design, simulation and characterisation of a novel, high performance, medium
power (≈ 50 W) class-B audio amplifier. Following a general discussion of amplifier characteristics and design
goals, the amplifier schematic is presented and described in detail. SPICE simulation results verify the design
and provide further understanding of circuit behaviour. A brief discussion on the methodologies of good
PCB design is followed by a presentation of the key experimental characteristics of the amplifier along with
a comparison to the characteristics derived by simulation. An amplifier control board which responds to
thermal and short-circuit faults and adds radio and alarm clock features is briefly discussed. The final section
‘recommendations for future work’ is a reflection upon the strengths and weaknesses of the amplifier design
and suggest possible means of improvement.

1 Amplifier characteristics and design goals

Conceptually, an audio amplifier has a rather simple task to perform; it must faithfully reproduce an input
signal at a larger output power. Audio amplifier parameters of particular interest from a user perspective are:
• Cost
• Continuous/momentary output power capability
• Noise and hum
• Thermal performance and reliability
• Speaker short-circuit tolerance/detection
• Closed-loop frequency response
• Closed-loop gain
• Electrical efficiency
• Distortion
From a design perspective the following six parameters are also of particular interest:
• Open-loop gain and phase delay as a function of frequency
• Margin of electrical stability under various load conditions
• Slew rate
• Power supply rejection ratio
• Thermal stability of quiescent currents
• Open-loop linearity
Ultimately, the main design goals of the amplifier described here are: low-noise, low distortion, fast slew rate
and good margin of electrical stability. It must be noted that the average human ear can not identify the
distortion content of sound for distortion values below about 1%. In addition, typical distortion values of a
speaker are of the order of 1%. For these reasons the pursuit of very low distortion audio amplifiers is usually
of academic interest rather than of practical importance. Nothing more will be mentioned regarding topics of
an audiophile nature.

1
Figure 1: Single-input, single-output negative feedback control loop where Vd represents the effects of non-
linearity or noise.

Amplifier design methodology

Open-loop non-linearity can be minimised to some degree, however, the inherent non-linearity of transistors and
other components prevent a high degree of open-loop linearity. Also, load impedances usually have a frequency
dependence and a possible degree of non-linearity. Therefore, the design of a low distortion amplifier mandates
the implementation of a negative feedback circuit. A negative feedback circuit with a large loop gain minimises
the impact of both non-linearity and noise sources by correcting for the effects of these perturbations. Take into
consideration Fig. 1, which is a block diagram of a negative feedback system that consist of linear sub-systems
H(s) and F(s). Vd is a disturbance voltage which represents the effects of non-linearity or electrical noise.
Considering the influence of Vd , there is a change in the output voltage which is dependent upon the loop-gain,
∆Vout 1
= (1)
Vd 1 + F (s)H(s)
The disturbance voltage, Vd , can be considered to be the result of noise or non-linearity. In either case the
output voltage will reproduce the input voltage to a high degree of fidelity provided the loop-gain, H(s)F(s), is
large. As a consequence of Eq. 1, the noise of an amplifier is usually dominated by the noise of those sources
that fall outside of the loop, i.e. the input components. The noise characteristics of the amplifier described in
this report are measured and analysed in the characterisation section 6. Another consequence of Eq. 1 is the
weak dependence of the closed-loop gain, A, on frequency,
Vout H(s)
A= = (2)
Vin 1 + H(s)F (s)

provided H(s)F(s) >> 1, and the feedback function, F(s) is independent of frequency, which is usually the case
where F(s) is simply a voltage divider consisting of resistors. The above equations suggest the cascading of
several amplifier stages such that a huge open-loop gain is achieved, thereby, a low-noise, low distortion amplifier
will result. However, the electrical stability of a negative feedback circuit needs to be ensured, otherwise it may
oscillate or have excessive amounts of overshoot. The stability of a negative feedback circuit is dependent on
both the loop-gain and phase delay. With increasing frequency the loop phase delay inevitably increases and
the loop-gain decreases. A condition for stability is a loop-gain, H(s)F(s), of less than 1 at the frequency where
the phase delay has increased to 180 degrees. The frequency at which the loop-gain decreases to unity is defined
as the cross-over frequency, ωc , and the phase margin is defined as 180 − φdelay (ωc ). As an example see Fig.
2 which is a plot of gain and phase of the OPA350 opamp which is unity gain stable since the phase delay is
about 120 degrees (phase margin of 60 degrees) at the cross-over frequency of 38 Mhz.

Figure 2: Open-loop gain and phase delay as a function of frequency of the OPA350 opamp.

2
 Stabilisation of an amplifier is usually achieved by including a compensation capacitor which reduces the
amplifier gain with increasing frequency such that at the crossover frequency the phase margin is somewhere
about 50 degrees or more. A high-performance amplifier has a large loop-gain for the frequencies of interest,
and therefore the crossover frequency should be relatively high so that the gain of the amplifier is not excessively
curtailed by the action of the compensation capacitance within the frequency band of interest. As a consequence
of the necessity of electrical stability, adding an arbitrarily large number of gain stages to an amplifier is not a
strategy that produces good results since this will result in excessive phase delay. A larger phase delay requires a
smaller cross-over frequency to maintain stability. Therefore, the gain within the audio band will be excessively
limited by the compensation capacitance.

Miller capacitance

Figure 3: Circuit schematic that is referred to in the discussion of miller capacitance with SPICE simulations
shown in Fig. 4.

Before discussing the amplifier schematic the effect of miller capacitance will be quantified since it has a con-
siderable impact upon amplifier design and performance through the phase delay that it induces. Referring to
figure 3, and labelling the AC component of the voltages,
vs (t) = VS eiωt (3)
iωt iφB
vb (t) = VB e e (4)
ve (t) = vb (t) (5)
iωt iφC
vc (t) = VC e e (6)
the output voltage, vc (t), as a function of frequency is,
 
β 1
−RL β+1 RE − iωC
vc (t) = vS (t) h   i (7)
RS 1 RS
1+ RE β+1 − iω RL C 1 + R E
+ RS C − 2ω 2 C 2 RL RS

For the above equation it is assumed that the transistor has a finite current gain, β, but is otherwise ideal and
has an infinite frequency response. As such, the miller effect and frequency response is modelled by the external
capacitor, C as shown in the schematic of Fig. 3. For small ω,
β RL
β+1 RE
vc (t) = −vs (t) RS 1
(8)
1 +R E β+1

For β >> 1 and RS << βRE the gain is closely described by the familiar relationship, RL /RE . The cut-off
frequency is,
1
ω=   (9)
RS
RL C 1 + R E
+ RS C
If RL >> RE , i.e. the single transistor has significant low-frequency gain the cut-off is approximately inversely
proportional to the voltage gain multiplied by the capacitance and input resistance, RS . The phase delay is,
     
RS
ωRL C R1E RL 1 + R E
+ RS + 2ω 2 C 2 RL RS − 1
φ = tan−1   (10)
RL RS 1 2 2 2 2
RE 1 + RE β − ω C RL RS + RL ω C (RL + RS )

3
Taking the 1st order ω terms the above equation approximates to,
   
RS
φ = tan−1 ωC RL 1 + + RS (11)
RE

The bandwidth of the single transistor amplifier is determined by C, which is transistor dependent, the voltage
gain and input resistance, RS . The important point to note is the phase delay increases with increasing voltage
gain and input resistance. It is important to consider the phase properties of the voltage amplification stage
of an amplifier and eliminate any unnecessary voltage amplification of all other stages. SPICE simulations of
the single transistor amplifier shown in Fig. 3 with and without additional external capacitance are plotted in
Fig. 4, demonstrating the impact of voltage gain on phase delay and bandwidth. The MMBT6429 transistor is
a small signal type with a gain-bandwidth in excess of 300 MHz under the bias conditions of the simulations,
however, the phase delay is 38 degrees at 10 Mhz for a voltage gain of 23.3 (red trace).

0 0
-2 -10

Phase delay [degrees]

-20
-4
I RL [dB, A.U.]

-30
-6 -40
RL = 0, C = 0
-8 RL = 1 kΩ, C = 0 -50
RL = 0, C = 10 pF -60
-10 RL = 1 kΩ, C = 10 pF -70
-12 -80
105 106 107
Frequency [Hz]
Figure 4: SPICE simulations that demonstrate the impact of miller capacitance on the bandwidth and phase
of the circuit shown in Fig. 3. Solid lines plot the current signal through RL and dashed lines plot the phase
delay.

2 Amplifier Schematic description

The schematic of the amplifier as constructed and characterised is shown in Fig 5. It consists of four stages,
two differential, an output driver, and output stage. The differential gain stages operate in a transconductance
mode, i.e. neither are required to generate a significant voltage signal, rather, they are viewed as producing
a current signal in response to a small magnitude input voltage signal. The output driver stage consisting of
transistors KSA1220A (Q19) and KSC2690A (Q21) is the voltage amplification stage (VAS) and the output
stage is a unity gain buffer. C16 (47 pF) connected between the output and the 1st differential stage output is
the compensation capacitance. The closed-loop gain is 27k/(470×2) = 28.7 = 29 dB, hence, full-power (50 W
into 8 Ω) corresponds to input voltages of 700 mV RMS.
The first differential stage incorporates a current mirror which allows straight forward coupling to the 2nd
stage input. In addition, the current mirror doubles the transconductance of the 1st stage and hence the low-
frequency open-loop gain. Both differential stages are biased by constant current sources and the quiescent
current of the 2nd differential stage biases the output driver stage which in-turn biases the output transistors.
Therefore, the quiescent current of the 2nd differential stage determines the quiescent current of the output
driver stage. Hereafter, the quiescent currents of the 1st differential, 2nd differential, output driver and output
stages are labelled I1 , I2 , ID , and IO respectively. The two constant current sources of the 2nd stage are assumed
to be near equal in magnitude. These constant current sources are adjusted by trimmer potentiometers (R21
and R28) such that ID is set to a desired value.

4
 1 2 3 4 5 6 7 8
+15V +15V +40V COP9
P9 +40V

1
PIP901
+40V PIC102 1u PIC202 68n PIR502 PIR702 PIC302 220n PIC402 1u PIC1702 1u PIR2101 PIC2402 1u PIR2902 PIR30 2 PIR3102 PIR3202 PIR3402 PIC2601 C27COC27PIC2701
PIR602 COR32 12 PIC2502

+
COR21PIR2102100 1n8
R21

R29

R31
COR29 COR31

619
R30

R32

R34
COR30 1K COR34
R5

R7

PIC101 C1 PIC201 C2 COR5 681 681 COR7 PIC301 COC3 PIC401 PIC1701 BC860C PIC2401 COC24 1K33 1K33 PIC2602 C26
PIR102 COC1 COC2 1K COR6 COC4 COC17 PIQ10 E PIC2501 COC25 COD10 PIQ2 0E COC26 PIC2702
R6

C3 C4 C17 C24 C25 D10

PIR501 PIR701 COQ10
Q10 PIR2103 37 PIR2901 PIR30 1 PIR3101 PIR3201 PIR3401
21K5
R1

A COR1 GND PIR601 GND GND PIQ100B GND PIR3301COR33

R33PIR3302 PID100K PID100A PIQ220B A
PIQ30E PIQ50E

68u 50V
68u 50V
PIR101 PIQ10C BC860C BC860C PIQ10 C PIQ1 0E PIQ180E PIQ190E 110 COQ22
Q22 PIQ2 0C GND
BD139 PIQ30B PIQ50B BC860C BC859C KSA1220
PIQ10B PIQ110B PIQ180B PIQ190B
COQ1
Q1 COQ3
Q3 COQ5
Q5 MMBTA56
16V - DZ2J160

COQ11
Q11 COQ18
Q18 COQ19
PID10K COD1
D1 PIQ10E PIQ30C PIQ50C COR22 PIR2202
GND PIR2201R22
PIQ1 0C PIQ180C PIQ190C
Q19
PIR202 PIQ40E 27K 17mA
PID60A PIR3502
BC860C COC16 COD6
PID10A C16 D6

R35
80mA
PIQ40B 10K COR35
R2

COR2 15 COQ4
Q4 PID60K
PIQ40C PIC1601 PIC1602 Vout PIR2302 PIR2402 COP3
P3 PIR3501
GND PIR201 PIC1802 10n COR23 PIC1902 270p PIP303 3 B NPN PIP701
R23

R24
+15V 47p 68R1 121 COR24
GND PID70K +40V PIP302 2
C

1
PIC502PIC501 COC5C5 PIC1801 COC18
C18 PIR2301 PIR2401 PIC1901 C19
COC19 15V
PIP301 1 COP7
+ 220u 25V COD7
D7 E NJW0281G P7
GND PID70A Fault +ve
+ PIC602 220u 25V PIQ120E BC860C
PIQ130E 1n PIR3602
PIC601PIC602
PIC601
COC6
C6 BC860C
PIQ120B PIQ130B PIC2801PIC2802
PIC2801 PIC2802

R36
-7V COQ12
Q12 COQ13
Q13 COC28
C28 0R1 COR36 PWR GND
GND PIR302 +6V supply for PIQ120C PIQ130C PIR3601

Figure 5: Amplifier schematic diagram

DA2J10100 COP11
P11
2nd differential stage
8V2 - DZ2J082

R3

COR3 15
PID20K COD2
D2 GND PID30A PID30K
COD3
D3
Iq
GND PIP1101 1
B PIR301 +15V +6V B
PID20A PIQ20E PID40K PID40A COD4
D4 PIR4601 BD139 Vout

20mA
200
BD140

R46
PIQ20B
COQ2
PIR1902 +15V DA2J10100
COR46PIR4602 PIP403 3 B PIP5022
Q2
2K37

PIR402 PIP402 2 C Audio Output

R19

PIQ20C COR19 0u22 PIR4603 PIC2902 PIP401 1

PIC30 2 5n PIP5011
34K8

+6V 100u 16V PIC2001 PIC2002 GND E COP5

R4

COR4 PIR1901 COC20 PIC2901 COP4 PIC30 1 COC30

C30 P5
PIQ140C C20 PIQ150C P4
PIR3702 GND
PIR401 PIR20 2
MMBT6429 COC29
C29 1u
1u MMBT6429

R37
Vout PIQ140B PIQ150B
PIC1402 PIC1501 COQ15
Q15 COR37 10
+
PIR3802
1K62
R20

-40V COR20 PIC1401 C14 PIC1502 COC15 PIQ140E COQ14

Q14 PIQ150E PIR3701

R38
PIR802 COC14 C15 0R1 COR38
1p2 PIC10 2 PIR20 1

5
1n
27K

PIR3801
R8

COC10
C10 COR8 GND
PIC10 1
PIC2102 10n PIR2502 PIR2602 PIC3102 PIC3101
GND
33uF PIR801 PIQ60C PIQ70C PIC2 02 270p COC31
C31

R25
COR25

R26
C7 470 470 COR26
Audio Input

COC7 68R1 121

1 PIP201 PIC701
PIC701PIC702 PIR901 COR9
PIC702PIR901 R9 PIR902 PIR1001COR10
R10PIR1002 PIQ60B
MMBT6429 MMBT6429
PIQ70B
PIC2101 COC21
C21 PIC2 01 COC22
C22
2 PIP202
COQ6
Q6 COQ7
Q7
PIR1603 PIR2501 PIR2601 PID80K COP6
P6
PIR1202 PIQ60E PIQ70E 30V
COP2 15n PIC901 PIR1302 10K
PIC1202 1u PIP601 1 E PNP
R16
P2 error COR16PIR1602 Fault -ve
R12

COD8
1K COR12 COR13 PID80A
COC9
C9 D8 -40V PIP602 2 C
R13

PIC902 3K16 PIC1201 COC12 GND COP8

P8
C PIC801 PIR1201 PIR1601 C12
0R18 PID50K 6V8 PIP603 3
B NJW0302G C

1
1u error
PIC802 PIR1 01 COP12
P12 PIR1301 COR18PIR1802
PIR1801R18 error PIR2702 D5
COD5 PIP801
COC8 PIR1702 PID50A

80mA
C8 error 10n PIC1302 PIR4502

R27
2PIP1202 GND
R11

6R65 COR11 10K COR27 17mA PID90A

R17
COR17

R45
GND
1PIP1201 GND 10mA PIC1301 6R65 COD9
D9 10K COR45
PIR1 02 meas PIR1402 COC13
C13 PIR2701 PIQ160C
PIR1701 MMBT6429 PID90K PIR4501
R14

P12: U.FL open-loop COR14 46K4 PIQ160B PIQ20 C PIQ210C

68u 50V
68u 50V
GND COQ16
Q16 MMBT6429 KSC2690 MMBTA06L
gain test socket GND PIQ170C PIQ160E
PIR1401 PIQ80C MMBT6429 COQ20
Q20
PIQ200B PIQ210B
COQ21
Q21 COQ23
Q23
PIQ80B
MMBT6429
PIQ170B GND PIQ20 E PIQ210E 110 PIQ230C GND
Q8
COQ8 COQ17
Q17 GND
PIQ170E PIR2801 PIR4301 COR43 PIR4302 PID110A
R43 PID110K PIQ230B
MMBT6429
PIQ90C PIQ80E 35
PIC2302 1u PIC3202 1u PIR3902 PIR40 2 PIR4102 PIR4202
PIC3 02 1n8 COD11
D11
PIR4 02
PIQ230E PIC3401 COC35 C35
PIC3501

R40

R41

619

+
R28

R39

R42

R44
COQ9
Q9
PIQ90B GND 100 COR28PIR2802 PIC3201 COC32 COR39 1K33 COR40 1K COR41 1K33 COR42 12 COR44
PIQ90E PIR1503 56 PIR2803 PIC2301
COC23
C23 C32
PIR3901 PIR40 1 PIR4101 PIR4201 PIC3 01 C33
COC33 PIR4 01 PIC3402 COC34
C34 PIC3502
PIC1 02 1u

R15
100 COR15PIR1502 PI 10 1
PIC1 01 C11 -7V -40V COP10
P10 -40V

1
COHS1
HS1 COC11
PIHS101
PIR1501
COHS2
HS2 PIHS201
Heatsinks on -7V
Q1, Q2, Q19, Q21 Title : Audio Amplifier
D D
COHS3
HS3 PIHS301
COHS4
HS4 PIHS401 Size Number Revision : 1.2
A4
Date: 2/8/2017 Sheet :1of 1
File: C:\Users\..\amplifier_V2.SchDoc Drawn By: Greg Jolley
1 2 3 4 5 6 7 8
 IO is limited by a BD139 transistor placed across the bases of the output transistors. The BD139 should
be in close thermal contact with the output transistors so that there are minimal variations to the relative VBE
across temperature, therefore, the sensitivity of IO to temperature change is minimised. The sensitivity of IO
to temperature has been measured, see the characterisation section 6. The two differential stages operate from
supply voltages that are different to that of the VAS and output stage. These supply voltages are generated by
zener diode based reference voltages that are buffered by transistors. The positive and negative supplies have
nominal voltages of 15V and -7V respectively. Separate supplies keep the thermal dissipation of the differential
stage transistors to within acceptable limits, reduces voltage stress and broadens the set of transistors that can
be utilised by the differential stages.
The input is filtered by a simple RC network (R9, C9) which serves two purposes; firstly it attenuates
frequency components of the input signal that lie beyond the upper end of the audio band, secondly it blocks
high frequency signals on the input that originate from radiated emissions. The second point is important since
a possible amplifier oscillation mode results from the emission of EM radiation via the output cabling, which is
picked up by the input cabling. Therefore, the simple RC network may be required to prevent high-frequency
oscillations.
Ground currents have the potential to induce hum on the amplifier output, an issue that may be the result
of a poor PCB layout. The amplifier input is driven by a separate control board which contains a volume
control I.C. (PGA2311). If ground currents produce a small potential difference between the ground planes of
the amplifier and control boards, this will result in hum since the control board output signal is with respect
to a potential that is slightly different to the amplifier ground potential. The amplifier contains input circuitry
which essentially eliminates the possibility of the above mentioned source of hum. The ground potential of the
control board is feed into the inverting input of the amplifier, and a portion of it which comes from the R17,
R18 voltage divider is feed into the non-inverting input. As such, any ground potential differences do not result
in an amplifier output voltage with respect to its ground potential.
As mentioned previously, maintaining a large gain within the audio band while minimising phase delay is a
necessary requirement for the design of a high performance amplifier. The amplifier phase delay is minimised
about the unity loop-gain point through 2 main mechanisms; the minimisation of the miller capacitance effect
and the phase lead resulting from capacitors placed within the second differential stage and the output driver
transistor emitter capacitance. C2 and C3 of the 1st differential stage increase the open-loop gain at about
10 kHz. The impedance ratio of C3 in parallel with R7 (C3||R7) and C2||R5 becomes significant at about 10
kHz, therefore the current signal of Q5 is greater than Q3. At higher frequencies the dynamic impedance of
the emitter-base junctions of Q3 and Q5 become greater than C3||R7 and C2||R5, therefore the current signals
in the current mirror become more symmetrical. C19 and C22 of the 2nd differential stage increase the phase
margin about the cross-over frequency. Likewise, C25 and C33 (output driver stage) improve the phase margin,
but to a leaser extent. Miller phase delay is minimised by the direct coupling of the two differential stages and
the voltage amplification stage at higher frequencies through C18, C21, C28 and C31.
The 1.2pF capacitor (C10) that is in parallel with the feedback resistor (R8) greatly improves the stability
margin of the amplifier. It is expected that the base capacitance of the input transistor, Q6, in addition to any
parasitic capacitance induces a phase delay at its base. This contribution to the phase delay can be eliminated
by including a small capacitance in parallel with the feedback resistor. The MMBT6429 data sheet indicates
that the typical collector-base capacitance is less than 2 pF at VCB = 5 V. Given the small voltage signal on
the collector of Q6, the 1.2 pF capacitor must enhance stability primarily because of a generated phase lead.
The quiescent currents I1 , I2 , ID , and IO , have an impact upon circuit performance and stability. Increasing
I1 increases the open-loop gain across the entire frequency span and increases the slew rate since the transcon-
ductance of the 1st stage is proportional to I1 . The slew rate is ultimately limited by the amount of current
that the 1st differential stage can provide to offset the current through the compensation capacitor,
dv I1
= (12)
dt 47 pF

Since the 2nd differential stage requires little input current (in comparison with I1 ), even when the output
is driving a large voltage across an 8 Ω load, the actual slew rate is expected to be close to the value given
by Eq. 12. For I1 = 10 mA this equates to a slew rate of 213 V/µs. Essentially, I1 should be set to larger
values provided stability is not compromised. The phase delay of the driver stage is dependent on ID since the
gain-bandwidth product of Q19 and Q21 peak at a particular value of IC and the collector-base capacitance has
a dependence on collector current. It is found that ID = 80 mA is a good compromise between minimising phase
delay without setting an excessive quiescent current. Through SPICE simulations it is found that reducing ID
increases the phase delay around the cross-over frequency while having less impact upon the open-loop gain,
therefore the phase margin decreases. There appears to be no point to setting IO beyond a small value. When
both output transistors are conducting the transconductance of the output stage is double that of when only a

6
single transistor is conducting. Transitions between these two transconductance modes is a source of distortion.
The open-loop gain and phase, hence, stability depend upon both the magnitude and phase of the load
impedance. Speakers and cabling represent quite an unpredictable load. A common practice is to isolate the
speaker load at high frequencies and add an additional load with properties that ensure stability. R37 and C30
result in a resistance of 10 Ω across the amplifier output at high-frequencies, aiding in stability.
The amplifier incorporates basic speaker short-circuit protection to prevent damage to the output transistors
and power supply that may otherwise occur if the output is short-circuited. Q22 and Q23 detect excessive driver
transistor current and turn on. These signals are detected by the amplifier control board in the form of a MCU
interrupt, resulting in rapid shutdown of the amplifier power supply.
More analytic detail on the amplifier gain is found in the Appendix 9.

3 SPICE simulations
The circuit for SPICE analysis is shown in Fig. 6, all references to components in this section are with respect
to this schematic diagram and the component values for all simulations are as they appear unless otherwise
stated. LTspice (www.linear.com/designtools/software) was used for all SPICE simulations. Small signal
AC transfer simulations of the closed-loop gain and phase for the optimised component values as shown in the
simulation schematic is shown in Fig.7. In-addition, plots are shown for the feedback capacitor, C15=0. The
benefits of C15 are clearly evident by the elimination of gain peaking at about 8 MHz and reduction of the
phase delay at about the cross-over frequency. Transient simulations indicate that the full-power bandwidth is
a little over 1 MHz.
The open-loop gain and phase for the optimised component values is shown in Fig.8. The two differential
gain stages results in a very large voltage gain of 130 dB at frequencies less than 100 Hz. The gain reduces with
increasing frequency beyond 100 Hz due to the 47 pF compensation capacitor. The reduction of open-loop gain
with increasing frequency (aside from the influence of other capacitors such as C1 and C2) can considered as
the result of the reduction of the load impedance at the output of the 1st differential stage,
1 1
gain ∝ = (13)
Z ω × 47 pF
which equates to -6 dB per octave. The inclusion of capacitors C1 and C2 pushes the gain at 10 kHz to a
little over 100 dB. The cross-over frequency is modified by C16 which increases the closed-loop gain at higher
frequencies to 27k/470 = 57 = 35 dB, giving a cross-over frequency a little under 10 MHz and a phase margin
of 80 degrees, though the phase margin minimum is 69 degrees at 170 kHz.
The frequency at which the open-loop gain begins to decrease is given by the relationship,

ω × 47 pF × gm2 × gmD × rmO = Zout1 (14)

Where gm2 is the transconductance of the 2nd stage, gmD is the transconductance of the driver stage, rmO is
the transresistance of the output stage and Zout1 is the impedance as seen at the output of the 1st differential
stage. Zout1 is the result of the early voltage of Q5 and the load impedance of the 2nd stage input. For more
detail see the appendix.
Various transient waveforms for a 1 kHz input signal are shown in Fig 10. What is interesting is the very
non-sinusoidal waveforms of the 1st stage output and the base voltage of Q17. It turns out that the rather
small early voltages of the output transistors is the primary influence on the shape of these waveforms. As
a function of collector current the current gain of the output transistors are very linear, however, the current
gain has quite a strong dependence on VCE leading to a output stage transresistance that is non-linear and
dependent on the amplifier output voltage. The voltage on the base of Q4 is close to sinusoidal because the
compensation capacitance linearises the load on the 1st stage output. Simulations were performed for a 50 Hz
sine wave input of several different magnitudes such that the compensation capacitance has negligible influence
on the gain. The low-frequency was chosen to investigate the gain of the various stages of the amplifier as a
function of output magnitude.

7
Figure 6: Amplifier schematic diagram for LTspice simulations

8
 Vout VB Q4 (µV) VB Q10 (mV) IC Q11+Q13 (mA) IC Q17 (mA) IC Q22 (mA)
10 3.5 27.5 0.278 3.18 3.51
20 7.68 60.9 0.616 7.18 7.84
30 12.8 102 1.03 12.3 13.2
40 19.2 153 1.55 18.8 20.0
50 27.3 219 2.21 27.2 28.6
60 38.1 305 3.07 38.4 40.0

Table 1: Summary of various signals, all magnitudes given as peak-peak values.

Vout Av 1st-stage gm 2nd-stage AI driver rm output stage total open-loop gain (dB)
10 7860 0.0101 25.3 1490 129.4
20 7930 0.0101 25.5 1330 128.3
30 7970 0.0101 25.7 1180 127.4
40 7970 0.0101 26.0 1030 126.4
50 8020 0.0101 25.9 896 125.3
60 8010 0.0101 26.6 765 123.9

Table 2: Summary of gain for various output voltage magnitudes. Av 1st-stage, gm 2nd-stage, AI and rm output
stage are the voltage gain of the 1st differential stage, transconductance of the 2nd stage, current gain of the
driver and transresistance of the output stage respectively. The transconductance of the 2nd stage is calculated
by adding the collector signal current of both Q10 and Q12.

A summary of the peak-peak magnitudes of various signals is shown in table 1 and stage gains are shown in
table 2. The voltage gain of the 1st differential stage is given by,
∆VB Q10
(15)
∆VB Q4
The transconductance of the 2nd stage is given by,
∆IC Q11
(16)
∆VB Q10
The current gain of the driver stage is given by,
∆IC Q17
(17)
∆IC Q13
The transresistance of the output stage is given by,
∆Vout
(18)
∆IC Q17 + ∆IC Q22
It is evident that the gain of all stages apart from the output are largely independent of output magnitude.
The transresistance of the output stage depends on the load impedance and current gain of the output transistors
which is dependent on VCE . The early voltages of the driver transistors have little impact upon the combined
transresistance of the driver and output stages due to the emitter resistors, R25 and R31.

The response to a square wave input with the input filter capacitor (C16) removed is shown in Fig. 11
indicating a slew rate of 230 V/µS which is is close to the upper limit calculated in the amplifier schematic
description section.
A long transient simulation with a small time-step was performed for a 10 kHz input and a FFT was taken
of the output waveform to obtain an indication of the amount of amplifier distortion, see Fig. 12

9
 0

35 20
Closed-loop gain [dB]

Phase delay [degrees]

40

30 60

80

25 100
C15=0
C15=1p2 120
20
10 3 10 4 10 5 10 6 10 7
Frequency [Hz]

Figure 7: Closed-loop gain and phase for optimised component values and for C18 = 0. The advantage of
including a 1.2 pF capacitor within the feed-back loop is clearly seen by the reduction of gain peaking and
improved phase margin for frequencies around cross-over.

180
120

160
100
Phase margin [degrees]
Open-loop gain [dB]

140

80
120

60
100

40 80

20 60
101 102 103 104 105 106 107
Frequency [Hz]

Figure 8: Open-loop gain and phase margin for optimised component values.

10
 120

100
Gain [dB]
80
C1 = C2 = 0
60 C4 = C6 = 0
Optimised
40

20

180
160
140
Phase [degrees]

120
100
80
60
40
20
0
101 102 103 104 105 106 107
Frequency [Hz]

Figure 9: Open-loop gain and phase plots for optimised, C1 = C2 = 0 and C3 = C4 = 0

11
 −6.08×10−3

−6.10×10−3 a)

−6.12×10−3

−6.14×10−3

−6.16×10−3

−6.18×10−3

6.2
6.15
b)
6.1
6.05
6
5.95
Voltage [V]

5.9
37.9
37.8
c)
37.7
37.6
37.5
37.4
37.3
30

20
d)
10

−10

−20

−30
0 0.5 1 1.5 2
Time [mS]

Figure 10: Various transient voltages; a) Q4 base voltage, b) 1st stage output voltage, c) Q17 base voltage,
d) amplifier output voltage.

12
Figure 11: Response to a square wave input, the slew rate is 230V/µS for both the rising and falling edges
between 10% and 90% of the final output value.

Figure 12: Fourier transform of a 50W output signal (8 Ω load) in response to a 10kHz sinewave input. The
3rd harmonic magnitude is 0.00032% of the fundamental.

Simulations were performed to investigate the dependence of the amplifier output voltage on the error voltage
(V7). It was found that there is a negligible output voltage in response to V7 (simulation results not shown).

4 Component Selection
The components that have a significant impact upon the amplifier performance thought choice of their type
are;
• Output transistors
• Output driver transistors
• 1st and 2nd differential stage transistors

13
Output transistors
NJW0281 (npn) and MJW0302 (pnp) are ideal output stage transistors due to their excellent gain linearity
(gain matching within 10% from 50 mA to 3 A), exceptionally safe operating area and high transition frequency.
The high transition frequency and a relatively small output capacitance of 400 pF (VCB =10 V) minimises the
phase delay at higher frequencies. However, their small early voltage is a significant source of non-linearity.

Output driver transistors

The KSA1220A (pnp) and KSC2690A (npn) are ideal choice as the driver transistors due to their small output
capacitance of 19 pF (VCB =10 V), large gain, and a gain-bandwidth-product of 155 MHz (VCE = 5V, IC = 0.2
A).

Differential input pair transistors

MMBT6429 transistors have been chosen for the NPN differential stages due to the following reasons:
• Very large gain

• Gain-bandwidth product of about 350 MHz at 5 mA and VCE = 5 V.

• High Early voltage
• Low-noise

Supply rail decoupling capacitors

The power supply must be decoupled with capacitors that exhibit a low impedance at high frequency otherwise
oscillations may result due to an unintentional feedback path. When a load is driven at high frequency, mod-
ulation of the supply voltage resulting from a supply impedance may be fed back into the input resulting in
oscillations. Both supply rails are decoupled by two 68 µF polymer electrolytic capacitors, manufacturer part
number 50SVPF68M.

Feedback resistors
Common resistor technologies (either thin or thick film) are suitable for the majority of the amplifier resistors.
Amplifier noise is dominated by the noise of the input transistors and associated input resistors, therefore there
is some motivation for the use of resistors with low excesses-noise.

5 PCB layout
Consideration of the PCB layout is essential since an inadequate layout can be a major contribution to amplifier
hum, electrical instability and distortion. An understanding of the following phenomena is needed in order to
design a good layout:
• Inductive coupling - time dependent current loops can induce voltages around other trace loops.
• Capacitive coupling - traces undergoing voltage transitions can induce voltage fluctuations on other traces.

• Ohmic trace resistance - current will induce a voltage drop across a trace.
• Parasitic inductance and capacitance - can result in an unintentional impact upon the magnitude and
phase of analog signals.

14
 0R1

feedback
trace resistance

output load
0R1

Figure 13: A diagram demonstrating how trace resistance can lead to distortion.

At worst, inductive coupling can result in unintentional feedback paths pushing the amplifier into an unstable
electrical state and otherwise can be a significant source of distortion and noise. Wires and traces carrying the
large currents that drive the output load should be inductively isolated from the small signal differential stages.
Isolation can be achieved through distancing the differential stages from large current loops and by the use of a
ground plane to shield the input stages. In addition, minimising trace length and the area of current loops will
minimise inductive coupling. Similar techniques minimise the impact of capacitive coupling between the input
and output stages of the amplifier. Fig. 13. is a diagram of an output stage and depicts a potential impact that
trace resistance can have on amplifier distortion. The feedback trace is not directly connected to the output and
the asymmetry leads to a predominantly 2nd order harmonic content. A little bit of trace resistance may seem
trivial, however, a simple calculation suggests that the impact can be greater than expected. Consider the case
where the feedback trace is isolated from the output by a trace of length 3 cm with a width of 5 mm resulting
in a trace resistance of about 3 mΩ (1 oz/ft2 ). For a load impedance of 8 Ω driven by a peak voltage of 24 V
(load current 3 A) this results in a feedback error voltage of 9 mV between the positive and negative voltage
cycles. 9 mV in 24 V is 0.0375% and, therefore, possibly the greatest source of distortion in an amplifier! The
potential impact that parasitic capacitance can have on the feedback phase can be calculated by considering the
case of the feedback trace (length 6 cm, width 0.3 mm) running over a ground plane. For a PCB thickness of
1.2 mm this results in a capacitance of 2.8 pF. If the feedback resistor (27 KΩ) is placed directly at the output
this results in an additional phase delay of about 4.6 degrees at 10 MHz. The top and bottom copper layouts
are shown in figures 14 and 15. The high current output stage is isolated from the input sections and no large
ground current loops influence the input sections.

15
Figure 14: PCB top copper layer with top-layer silk screen

16
 Figure 15: PCB bottom copper layer with top-layer silk screen

6 Amplifier characterisation
Electrical stability
The electrical stability of the amplifier as a function of I1 , I2 (hence ID ) and IO was experimented with and
the stability was found to be excellent. As explained in section 2, the open-loop gain across all frequencies,
and therefore, stability depend on I1 . Therefore, stability can be examined by performing measurements as a
function of I1 , in particular the response to a square wave input. The response to a square wave input with the

17
 Heatsink temperature [◦ C] Current (mA)
29 20
49 38
66 58
89 104

Table 3: Output stage quiescent current for various heatsink temperatures.

input filter capacitor (C9) removed showed insignificant overshoot over the current range I1 = 5 → 15 mA.

Thermal stability - quiescent current drift

The output stage quiescent current temperature dependence was measured by driving an 8 Ω load with a sine
wave for a period of time sufficient for thermal steady state. The heatsink temperature and IO are recorded in
table 3. IO has a temperature dependence that is a little excessive, a suggestion to address this issue is made
in section 8.

Noise and hum

The output noise of the amplifier was measured over the 20-1 kHz band using a low-noise amplifier with a gain
of 10 000 connected to the output. Wide-band noise was measured with the power amplifier connected to a
regulated power supply. The low-noise amplifier was connected to a spectrum analyzer (analog discovery 2,
Digilent). The noise spectrum obtained with the amplifier input connector, P2, shorted is shown in Fig 16. The
wide-band noise of the amplifier due to the thermal noise of the input resistors is calculated to be,
v " #
u  2  2
u 27k 1670 27k + 725
vnoise (RMS) = 4kB T 725
t +p + 27k (19)
725 1 + (ω1670 × 10−6 )2 725

where 725 is R9+R10 in parallel with R13, 1670 is the resistance setting of trimmer R16, and 10−6 is the
capacitance of C12. The frequency dependent term becomes significant for frequencies less than about 100 Hz.
For √
frequencies greater than about 200 Hz the calculated noise density due to resistor thermal noise is 131
nV/ Hz √
The flat band noise of the amplifier is measured to be -51 dB/10000 = 282 nV/ Hz. Upon multiplication
by the low-noise amplifier gain, the noise spectral density due to resistor thermal noise is calculated to be −57.7
dB. The 6.7 dB difference is consistent with
√ the noise figure of the MMBT6429 transistor. The noise voltage
over the 20 Hz - 20 kHz band is about 20000 − 20 × 282 nV = 40 µV RMS. Note, the peaks at 50 Hz +
harmonics originate from EM interference of the low-noise amplifier input cabling.

Open-loop gain
Open-loop gain measurements were successfully performed by connecting a low-noise amplifier with a gain of
7500 to the U.FL test connector of the amplifier board. Waveforms captured with an oscilloscope for a 10 kHz
input signal are shown in Fig 17. The measured gain of 106 dB compares quite well with the calculated value
of 102 dB. At 1 kHz the measured gain is 113 dB and the calculated gain is 116 dB.

18
Noise spectrum x 10 000 [dB V/√Hz]

-46

-48

-50

-52
0 2x102 4x102 6x102 8x102 103
Frequency [Hz]

Figure 16: Measured noise spectrum of the amplifier output.

Figure 17: Measured waveforms for open-loop gain determination. At 10 kHz the gain is 106 dB.

19
Slew rate

Figure 18: Measured slew rate.

Slew rate measurements were performed by injecting a square wave into the input with the filter capacitor (C9)
removed. The output waveform is shown in Fig 18 indicating a slew rate of about 130 V/µS. This value is
significantly less than the calculated slew rate, the difference is attributed to the rise time of the square wave
oscillator.

Distortion measurements
Work is in progress to design and construct circuitry capable of measuring low levels of distortion...

7 Control board
At a minimum an amplifier of more than minimal cost should be immune to catastrophic damage under the
event of an output short-circuit or excessive thermal stress. These requirements can be effectively implemented
by a cheap microcontroller circuit. Considering the overall cost of the amplifier which is dominated by the
transformer, heatsinks, output transistors and case etc, from a design and component cost perspective there
is motivation to add functionality to an amplifier which is of relatively low cost. A control board which
protects the amplifier from short-circuit and thermal faults and includes radio, alarm clock, and volume control
functionality has been designed and constructed and is briefly described below. Incorporating radio and time
keeping functionality allows for alarm clock functionality through software development.

Volume control
A PGA2311 I.C. is chosen as the volume control device due to its low-noise and distortion, simple SPI digital
interface and ability to drive 600Ω loads directly. The PGA2311 has a wide gain and attenuation range; +31.5
dB to -95.5 dB with 0.5 dB steps, however, the range that is useful to the amplifier is likely to be +31.5 dB to
about -20 dB. It should be noted that the digital supply of the PGA2311 is +5V, however, it is driven directly
by the 3.3V I/O pins of the MCU since the data sheet indicates that the minimum high-level input voltage of
the PGA2311 is 2V.

FM radio receiver
A Si4703 I.C. is chosen as the radio receiver due to one feature in particular - it is essentially a complete radio on
a chip. It integrates all tuner functions from antenna input to stereo audio output. Basically, when designing the
amplifier and control board I was not interested in designing something that required RF techniques. However,
the Si4703 is a very attractive option due to its high performance characteristics. Its most significant features
are:

20
 • Simple 2 or 3-wire digital interface
• Worldwide FM band support (76–108 MHz)

• Seek tuning
• Automatic frequency control (AFC)
• Automatic gain control (AGC)

• Excellent overload immunity

• Signal strength measurement
• Programmable de-emphasis (50/75 µs)
• Adaptive noise suppression

• Line-level analog output

A separate PCB was constructed for the Si4703 which plugs into the control board.

Real-time clock
A PCF2127 I.C. is chosen as the time keeping device. Its most notable feature is an integrated temperature
compensated crystal oscillator. It incorporates a host of features that are not utilised by the control board,
however, it is included in the control board since I intend to use it for other projects as such the PCF2127
software I write for the control board will be reused later.

Temperature sensors
MAX31820 sensors are chosen as the amplifier temperature monitoring devices. An attractive feature of these
devices is their 1-wire interface which reduces MCU pin count requirements and PCB routing requirements.

Display
The NHD-C12864LZ-FSW-FBW-3V3 LCD is chosen as the display device since it has sufficient resolution
(128 X 64) to display the volume, temperature, radio and clock parameters, has an LED back-light and has
an appropriate active area. Also, this LCD can operate from a SPI port which reduces the MCU pin count
requirements.

MCU
The PIC18F47J13 is chosen for the microcontroller device for reasons that include:

• It is a simple 8-bit MCU which simplifies the writing of code

• A MCU with a small computational throughput is ideal for the control device
• Peripheral pin select - simplifies PCB routing
• SPI port with direct memory access - simplifies writing routines for the LCD

• A change in an I/O pin state can trigger an interrupt for interface to the amplifier current fault detection
circuit
• Interrupt sources can be assigned to one of two priorities, therefore, a current fault can interrupt any
low-priority interrupts that are in service

• An internal ADC allows measurement of the amplifier output voltage

Audio source selection

Circuitry is needed to switch between the Si4703 and external audio sources. This is achieved by the use of
opamps with a shutdown feature that puts the output into a hi-impedance state, see figure 22.

21
User commands
The control board accommodates 3 push button switches for user commands. Two of these switches generate a
low-priority interrupt, while the 3rd switch is polled while the MCU is actively responding to user commands
when the low-priority interrupt occurs. The control board schematic is shown in figures 19 to 23.

22
 1 2 3 4 5 6
COP5
P5
P7 - Ifault plug interfaces to amplifier current fault circuit 3V3_ISO Programming header
A COU9B A
3V3_ISO U9B
2
1

fault
100n
3V3
PIP502 PIP501 8
PIU908 VDD1 EP
45
PIU9045 56PIP605
COP6
P6
COC43
C43 COC41 PIC4202 COC42 29 6 PGC COR32PIR3202
PIR3201R32 5
PIC4301 PIC4302
PIC4102 C41 C42 PIU9029
7
VDD2 VSS1 PIU906
31
GND
PGD PIR3301R33
56PIP604
COR33PIR3302 4
PIC4101 0u22 PIC4201 0u22 PIU907 AVDD1 VSS2 PIU9031
PIR3802 28 30 GND PIP603 3
PIU9028 AVDD2 AVSS1 PIU9030
3V3_ISO PIP602 2
56PIP601
R38
10K

COR38 3V
GND GND
PIC18F47J13-I/ML MCLR COR34
PIR3401R34 PIR3402 1
COD4
D4 PROG
PIR3801
PID40K PID40A
PIR4102 COP7
P7 COU9A
U9A
2 PIP702 COR36
PIR3601 R36PIR3602 19 9
R41

COR41
100

AR PIU9019 RA0/AN0/C1INA/ULPWU/PMA6/RP0 RB0/AN12/C3IND/INT0/RP3 PIU909

Figure 19: Control board schematic - MCU

1 PIP701 2K15 20 10
PIR4101 AL PIU9020 RA1/AN1/C2INA/VBG/CTDIN/PMA7/RP1 RB1/AN10/C3INC/PMBE/RTCC/RP4 PIU9010 rad_SEN
Ifault 21 11
PIU9021 RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF RB2/AN8/C2INC/CTED1/PMA3/REFO/RP5 PIU9011 rad_SDIO
22 12
B PIU9022 RA3/AN3/C1INB/VREF+ RB3/AN9/C3INA/CTED2/PMA2/RP6 PIU9012 rad_SCLK B
14
PIQ80C 24
RB4/CCP4/PMA1/KBI0/RP7 PIU9014
15
rad_GPIO2
COQ8 fault PIU9024 RA5/AN4/C1INC/SS1/HLVDIN/RP2 RB5/CCP5/PMA0/KBI1/RP8 PIU9015 FET
Q8 PIQ80B 33 16
LED_MCU PIU9033 RA6/OSC2/CLKO RB6/CCP6/KBI2/PGC/RP9 PIU9016 PGC
32 17
PIQ80E PGA_CS PIR5001 COR50
R50PIR5002PIU9032 RA7/OSC1/CLKI RB7/CCP7/KBI3/PGD/RP10 PIU9017 PGD
PIR3101 COR31 1K
R31PIR3102 34 38
SCL PIU9034 RC0/T1OSO/T1CKI/RP11 RD0/PMD0/SCL2 PIU9038 A0
35 39
3V3 619 SDI PIU9035 RC1/CCP8/T1OSI/RP12 RD1/PMD1/SDA2 PIU9039 !RST
36 40
470 !CS PIU9036 RC2/AN11/C2IND/CTPLS/RP13 RD2/PMD2/RP19 PIU9040 RTC_CS
37 41
RTC_SCL PIR5101 COR51
R51PIR5102PIU9037 RC3/SCK1/SCL1/RP14 RD3/PMD3/RP20 PIU9041
COP10
P10
42 2
Audio magnitude

23
RTC_SDO PIU9042 RC4/SDI1/SDA1/RP15 RD4/PMD4/RP21 PIU902 RTC_INT MCLR_ISO
BAV20WS PIR5201COR52
43 3
RTC_SDI R52PIR5202PIU9043 RC5/SDO1/RP16 RD5/PMD5/RP22 PIU903 SW3
44 4 MCLR

2
1
PID60A PID60K 470 DQ PIU9044 RC6/CCP9/PMA5/TX1/CK1/RP17 RD6/PMD6/RP23 PIU904 rad_RST
PIC4 02 PIR3502 RTC_RST PIU901
1
RC7/CCP10/PMA4/RX1/DT1/RP18 RD7/PMD7/RP24
5
PIU905
PIP10 2 PIP10 1
100K

COD6
D6 COC44
C44
R35

PIC4 01 0u22 COR35 25 18

C PIU9025 RE0/AN5/PMRD MCLR PIU9018 C
GND
PIR3501 AL SD_MCU
26
PIU9026 RE1/AN6/PMWR VDDCORE/VCAP
23
PIU9023 PIC5001 PIC5002 GND
COP8
P8 PIR3702 27
PIU9027 RE2/AN7/PMCS NC
13
PIU9013 10u
1 PIP801 PIC4602
R37

COR37
8K8

COC46
C46 COC50
C50
2 PIP802 PIC18F47J13-I/ML
Ain PIR3701 PIC4601 10n
COU10 MCP809
U10
SW1, SW2, SW3 - user interface switches
GND 3V3_ISO PIU1003 IN !RST PIU1002
BAV20WS 3V3_ISO 3V3_ISO 3V3
3V3 Vss
PID80A PID80K
PIC4702 PIR3902 PIR4702 PIR4802 PIR4902 PIU10 1
COD8 COC47 PIR4502
100K
D8 C47
PIC4701 R39
COR39

100K

100K

100K
R47

R48

R49
0u22 COR47 COR48 COR49 GND

R45
3K9 COR45

MAX31820
COP16
P16
GND PIR3901 AR PIP1601 1
1K
PIR4701 COP17
P17 1K
PIR4801 COP18
P18 1K
PIR4901 COP19
P19
PIR40 2 DQ PIR5301COR53
PIR4501
R53 PIR5302 PIP1602 2
PGC PIR6001COR60
R60 PIR6002PIP1702 2 PGD PIR6101COR61
R61PIR6102PIP1802 2 SW3 COR62 PIR6202PIP1902 2
PIR6201R62
PIC4902

8K8
PIP1701 1 PIP1801 1 PIP1901 1

R40
D
COR40 C49
COC49 100 PIP1603 3
D
PIC4901 GND SW1 GND SW2 GND SW3
PIR40 1 10n GND
GND
1 2 3 4 5 6
 1 2 3 4 5 6

Vp COHS1
HS1
9V MCP1755 5V 5V
A PIR1602 PIHS101 A
1 5
Heatsink
PIC2402 Vin
VoutPIU505
PIU501
PIC2102 PIC2 01 PIC2301 PIC5602 COC56
C56
21K5

COC21
C21 COC22
C22 COC23
C23
R16

COR16 COC24 3
C24 PIU503 !SHDN
4
PWRGDPIU504
PIR1601 PIQ50C PIC2401 1u PIC2101 1u PIC2 02 0u1 PIC2302 0u1 PIC5601 0u1
GND
COQ5
Q5
PIQ50B
BD139 GND COU5
U5 PIU502 GND
Vp

2
2200uF 63V COQ1
Q1
PID20K PIQ50E

D
9V

S
10 PIQ10S PIQ10D
COD2
D2
PIR1901COR19
GND COC3 COC4 COC5 PIR102
PID20A R19 PIR1902
PIC301 C3
PIC401 C4
PIC501 C5 PIQ10G Si7461DP

100K

G
10V

R1
PIC2801 COR1
+

10V
B
PIC2802 COC28
C28 PIC302 PIC402 PIC502 PIR101 B
GND 100uF 9V MCP1755 3V3 3V3
GND
GND 1
Vin
PIU701
5
VoutPIU705
PIR202 MMBTA56L
PIC3102 PIC3202

237K
R2
COC31 3 4 COR2 3V3_ISO
GND
PIC3101 C31 PIU703
1u
!SHDN PWRGDPIU704
PIC3201 COC32
C32
1u
COP3
P3
3 PIP303 PIR201
DA2J10100L PIQ20E
COP4
P4
GND PID10K PID10APIR402
PID10APIR402 COR4
R4 PIR401 PIQ20B
GND Vin 2 PIP302 GND PIQ30C COQ2
Q2 PIP4011
PIC3401 GND COU7
U7 PIU702 GND
1 PIP301 COD1
D1 100K PIQ20C GND PIP4022 Vout
+

FET PIR302 COR3

R3 PIR301PIQ30B
COD3
PID30K 15
PIC3402 COC34
C34 100K COQ3
Q3 PIR601 3
PIP403
D3 PIQ30E

56K2
PIR2701 COR27
R27PIR2702 100uF GND

R6
C MMBTA06L COR6 C
10V PID30A PIQ70E -9V
PIQ70B
COQ7
Q7 GND PIR602
BD140 GND
-9V COU8
U8 MC79L05 -5V
PIR30 2 PIQ70C COHS2
HS2 PIR10 2
IN OUT PIU803 PIC1801 PIC1701 PIC1901
R30
47K

+
PIU802
COR30

23K7
R10
PIHS201
PIC3702 COC37
C37 PIC3802 PIC3901 PIC40 1 COR10 COQ4
Heatsink GND COC38
C38 COC39
C39 COC40
C40 PIC1802 C18
COC18 PIC1702 C17
COC17 PIC1902 COC19 Vn PIQ40G Q4

SG
PIR30 1 PIC3701 1u
PIU801 PIC3801 1u PIC3902 0u1 PIC40 2 0u1 C19
PIR10 1

D
PIQ40S PIQ40D
Vn 2200uF 63V BSC100N06
GND
D D

1 2 3 4 5 6

Figure 20: Power supply and amplifier switching circuitry of the control board.

1 2 3 4 5 6

COU1
U1 Audio output to amplifier boards
GND
5V PIU101ZCEN VinLPIU1016 Ain_L COC1
C1 COC2
C2 COP1
P1
0u1 PGA_CS PIU102!CS AGNDLPIU1015 GND 0u1 PIC102 PIC201 10u 16V GND PIP102 2
+

A 5V A
COC6
C6 RTC_SDI PIU103SDI VoutLPIU1014 An_L An_L PIP101 1
COC8
C8 PIU104VD+ VA-PIU1013
PIC101 PIC202 -5V An_L
PIC801 PIC602
+

GND PIU105DGND VA+PIU1012

10u 16V PIC10 2 PIC901 5V
+

PIC802 PIC601 RTC_SCL PIU106SCLK VoutRPIU1011 An_R COP2

P2
C10 PIC10 1 PIC902 C9
PIU107SDO AGNDRPIU1010 GND An_R PIP202 2
COC10 COC9
GND 5V PIU108!MUTE VinRPIU109 Ain_R 0u1 10u 16V GND PIP201 1
PGA2311 GND An_R

B GND GND B
External Si4703 board headers
100n 10u
PIC1 02 COC11
C11 PIC1202 COC12
C12 3V3 COP13
P13 COP14
P14
COU3
U3 1 PIP1301 rad_RST 1 PIP1401 GND
PIC1 01 PIC1201 330
+

RTC_SCL PIU301 SCL VddPIU3016 PIR701 COR7

R7 PIR702
PIR802 2 PIP1302 rad_SEN 2 PIP1402 rad_L
100K

3 PIP1303 rad_SDIO 3 PIP1403 rad_R

R8

RTC_SDI PIU302 SDI VbatPIU3015 Vbat 10n COR8

4 PIP1304 rad_SCLK 4 PIP1404 5V
RTC_SDO PIU303 SDO BBS PIU3014
PIC1501 PIC1502 GND COC15
C15
RTC_CS PIU304 SDA/!CE !INTPIU3013
PIR801 RTC_INT
5 PIP1305 rad_GPIO2 5 PIP1405 3V3
Rad1 Rad2
GND PIU305 IFS !RSTPIU3012 RTC_RST
PIU306 !TS PFIPIU3011 GND
C PIU307 CLKOUT !PFOPIU3010 C
GND PIU308 Vss TESTPIU309 COP9
P9
1K
PCF2129 !RST COR54
PIR5401R54 PIR5402
PIP901 1
A0 COR55 1K
PIR5501R55 PIR5502
PIP902 2
3V3 PIP903 3
Vbat COR56 1K
!CS PIR5601R56 PIR5602
PIP904 4 To external LCD board
2K7
COR57 PIR5702
LED_MCU PIR5701R57 PIP905 5
PIB10Vp COB1
B1
PIC2602 100n SDI
220
COR58 PIR5802
PIR5801R58 PIP906 6
COC26
C26 GND PIP907 7
PIB10Vn Battery PIC2601 SCL COR59 220
PIR5901 R59PIR5902
PIP908 8

D LCD D
GND

1 2 3 4 5 6

Figure 21: Volume control, realtime clock, LCD connections and Si4703 board connections.

24
 1 2 3 4 5 6

Audio source selection circuit, either an external audio source or the internal radio source are routed to the volume control I.C
5V

A
PIR502 A
Ain_L and Ain_R interface with PGA2311 audio input

178K
COC13
C13

R5
Ext connector is external audio source input COR5
0u22
rad_L and rad_R interface with the Si4703 audio output PIR501
GND PIC1301 PIC1302
PIR902

178K
COC14

R9
GND C14 COR9 COU2A
SD PIU205SD5V U2A
0u1 MAX4253
PIR4202 COC52
C52 PIR901 PIU2010
rad_L COR11
PIR1102 R11 PIR1101
PIC1401 PIC1402 PIU203 +
PIC5202 15n COU4

16K2
PIU408 SD5V
U4 V+

R42
COC53 COR42 SD 2K61 PIR1302 COC20
C20 PIU201 Ain_L
C53 MAX9632 V-
215 PIC5201 PIC20 2 520p PIU202 -

75K
R13
COP12
P12
1u
PIC5301 PIC5302 PIR4301COR43
R43 PIR4302
PIR4201 PIU403 +
PIU407 COR13 PIU204
B
1 PIP1201
V+
PIU406 Ain_L PIR1301 PIC20 1 B
V- GND
2 PIP1202 GND PIU402 -
3 PIP1203 215 PIU404 COR15
PIR1502R15 PIR1501
COR44 GND
Ext PIC5401 PIC5402 PIR4401R44 PIR4402 21K5
COC54
C54
PIR4602 PIC5 02 -5V
16K2

1K96 5V
R46

1u COR46 PIC5 01 C55 PIR1802COR18

R18 PIR1801 10p
PIC2501 PIC2502
COC55
PIR4601 15n PIR20 2 COC25
C25

178K
COC29

R20
GND
PIC2701PIC2702
PIC2701 PIC2702
COC27
C29
0u22
COR20
C27
PIR20 1
GND PIC2902 PIC2901
C
SD PIU608 SD
5V COU6
U6 PIR2 02 C

178K
MAX9632 COU2B
U2B

R22
5V
PIU607 COC30
C30 COR22 SD PIU206SD
5V
PIU603 + 0u1 MAX4253
PIR1702 V+
PIU606 Ain_R
2K61 PIR2 01 PIU2010
V- rad_R COR24
PIR2401 R24 PIR2402
PIC3001 PIC3002 PIU207 +
5K62

PIU602 - V+
R17

COR17 PIU604 PIR2602 COC33

C33
V-
PIU209 Ain_R
PIC3 02 520p PIU208 -

75K
R26
PIR1701 SD -5V COR26 PIU204
SD_MCU PIQ60C 1K96 PIR2601 PIC3 01
GND
COR21
PIR2101 R21 PIR2102
PIQ60B
COQ6
Q6
PIR2802COR28
R28 PIR2801
100K COR29
PIR2902 R29PIR2901
PIQ60E GND
21K5
PIC3601PIC3602
PIC3601 PIC3602
D COC36
C36 D
GND PIC3501 PIC3502
10p
COC35
C35
1 2 3 4 5 6

Figure 22: Audio source selection circuitry.

25
 1 2 3 4 5 6

3V3 5V
A COC7
C7 A
PIC102 100n PIC202 22n PIC302 22n PIC702 PIC701 GND
PIC101 COC1
C1
PIC201 COC2
C2 PIC301 COC3
C3 GND
22p
ANT 4p7
COP1 COC5 PIC502
C5 COU1
GND GND P1 U1
1n
1 PIP101
PIC401 PIC402
PIC501 2
PIU102 FMIP LOUT
14
PIU1014 LOUT
COC4
C4 13
B Headers to control board ROUT PIU1013 ROUT B
9
PIU109 RCLK 32.768k xtal
COP3
P3 19 GPIO2PIX102
GPIO1 PIU1019 330 COX1
X1
1 PIP301 3V3 330 COR1 7 18
SCLK PIR101 R1 PIR102 PIU107 SCLK GPIO2 PIU1018PIR601 COR6
R6 PIR602
2 PIP302 5V
SDIO
330
PIR201 COR2 8
R2 PIR202 PIU108 SDIO
17
GPIO3 PIU1017
PIX101
3 PIP303 LOUT 330 6
4 PIP304 ROUT
SEN PIR301
330
COR3
R3 PIR302 PIU106 SEN
5
PIC602
RST PIR401 COR4
R4 PIR402 PIU105 RST COC6
C6
5 PIP305 GND
GND
10K
PIR501 COR5
R5 PIR502
PIC601 22p
C CONN_5 1
PIU101 NC C
COP2 20 3 GND
P2 PIU1020 NC RFGND PIU103 GND
4
1 PIP201 RST GND PIU104
10 12
2 PIP202 SEN 3V3 PIU1010 VIO GND PIU1012
16 15
3 PIP203 SDIO 5V PIU1016 VA GND PIU1015
11 21
4 PIP204 SCLK 5V PIU1011 VD GND PIU1021
5 PIP205 GPIO2
Si4703-C19-GM
CONN_5
D D

1 2 3 4 5 6

Figure 23: Radio board schematic

26
Figure 24: Control PCB top layer

27
Figure 25: Control PCB bottom layer

28
8 Future work
There are two promising and simple modifications that may improve the amplifier design which are now de-
scribed. Experimental characterisation of the amplifier indicated that the output stage quiescent current, IO ,
has an excessive dependence on temperature. It is likely that a small modification to the circuit that limits
IO will greatly reduce the sensitivity to temperature, namely, the utilisation of a thermistor or similar. A
thermistor in close thermal contact with the output transistors can be used to make a temperature dependent
modification to the resistance of potentiometer (R46) such that the sensitivity of IO to temperature is reduced.
Two independent constant current sources bias the 2nd differential stage. These two current sources are set
approximately equal in magnitude so that the driver stage current is balanced when minimal current is supplied
to the 2nd stage input. A more convenient approach replaces one of the current sources with a current mirror
such that only a single constant current source is required to bias the 2nd stage.

9 Appendix
Low-frequency gain
The low-frequency gain of the various stages is calculated and the results are added to obtain the open-loop
gain of the amplifier. The transconductance of the 1st differential stage is,
I1
(20)
2nVT
Therefore, the voltage gain of the 1st stage is,
I1
R1 (21)
2nVT
where R1 is the load resistance present on the output of the 1st stage. There are two contributions to the load,
the input of the 2nd stage and the Early voltage of the 1st stage transistor, Q7. Note, the Early voltage of
current mirror transistor, Q5 has an insignificant contribution due to its emitter resistor, R7. The impedance
due to the Early voltage is,
VEarly
(22)
0.5 I1
The Early voltage of Q7 (MMBT6429) is very large, its SPICE model file indicates a value of 804 V, giving a
load resistance of,
804
= 1.61 × 105 Ω (23)
5 × 10−3
The load resistance due to the 2nd stage input is,

(R23 + R24)βQ12 ||(R25 + R26)βQ14 = 9.83 × 104 ||2.36 × 105 = 6.94 × 104 (24)

Therefore, the total load resistance on the 1st stage output is,

6.94 × 104 ||1.61 × 105 = 4.85 × 104 Ω (25)

The voltage gain of the 1st stage becomes,

 −1  −1
2nVT 4 0.0537
+ Re × 4.85 × 10 = + 0.184 × 4.85 × 104 = 8.73 × 103 V /V (26)
I1 0.01

The transconductance of the 2nd stage is,

1
= 5.29 × 10−3 A/V (27)
68.1 + 121
The transconductance of the driver stage is approximately the ratio of the load resistance on the 2nd differential
stage output, i.e. the collectors of Q13 and Q15 to the resistance on the emitter of Q19 and Q21 (12 Ω). A
correction to this approximation needs to be made because the dynamic resistance of the LEDs, D6 and D9 are
significant. The dynamic resistance of D6 and D9 are,
nVT 9.63 × 0.026
= = 143 Ω (28)
I 1.75 × 10− 3

29
The transconductance becomes,
 " −1 #−1 −1
1  1 1 1 1
+ + + + 143 
12 1k33 1k 1k33 12βQ19
(29)
 −1 " −1 #
1 1 1 1
× + / + + 143
1k33 12βQ19 1k33 12βQ19

The 1st line is the load resistance divided by 12 and the 2nd line is a voltage divider correction due to the LED
dynamics resistance. The datasheet suggests the current gain of Q19 and Q21 β are equal to about 200 which
gives a driver stage transconductance of 25.9 A/A.
The output stage transresistance when driving an 8 Ω is simply 8β. For small output voltages, VCE of the
output transistors is about 40 V and the current gain is close to 200, therefore, the transresistance is 1600. The
total open-loop gain of the amplifier is calculated to be,

8.73 × 103 × 5.29 × 10−3 × 2 × 25.9 × 1600 = 131.7 dB (30)

These values can be compared to those listed in table 2 which are derived by simulation.

Thermal dissipation of the output transistors - reactive load

The real power delivered to a linear load driven by a sinusoidal voltage waveform is given by,
Z T
1 hp i 1 p
dt Vpk sin(2πt/T )Ipk 1 − α2 sin(2πt/T ) + α cos(2πt/T ) = Vpk Ipk 1 − α2 (31)
T 0 2

where Vpk and Ipk is the peak load voltage and current and T is the period of the sinusoidal waveform. The
parameter α takes on values from -1 to 1, representing the fact that the load current may have an arbitrary
phase with respect to the load voltage depending on how inductive or capacitive the load is. The thermal
dissipation of each output transistor (ignoring the small contribution of the quiescent current) is given by,
Z T /2
1
Pth = Vsupply Ipk sin(2πt/T) dt (32)
T 0
1 p
− Vpk Ipk 1 − α2 (33)
4
where Vsupply is the output transistor collector voltage, i.e. the supply voltage. The integral is the power
delivered to both the load and output transistor and the 2nd term is the real power delivered to the load. For
a load impedance of ZΩ the thermal power dissipated by each output transistor becomes,

Vsupply Vpk V2pk p

Pth = − 1 − α2 (34)
π Z 4Z

30
 Figure 26: Power dissipated by each output transistor.

Figure 26 is a plot of the thermal power dissipated by each output transistor for Vsupply = 40V and Z = 8 Ω.
The maximum power dissipated for α = 0 is about 20 W, which increases to 55 W for α = 1.

31