Computer Organization and Architecture

Unit 1 Notes

Compiled by- Prof. Mukesh Raj

Unit 1-Syllabus
Introduction:
Functional units of digital system and their interconnections, buses, bus architecture, types of
buses and bus arbitration. Register, bus and memory transfer. Processor organization, general
registers organization, stack organization and addressing modes

BOOKS:
1. Computer System Architecture- Third Edition By M. Morris Mano
2. Computer Organization And Architecture-Designing For Performance, Eighth Edition
By William Stallings
3. Computer Organization And Embedded Systems, Sixth Edition, By Carl Hamacher,
Zvonko Vranesic, Safwat Zaky, Naraig Manjikian.

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 COMPUTER
Computer is an electronic device that processes the data.
Computer is an electronic digital device that takes input from input device, processes that
input and sends the result to the output device.

Functions of a computer:
 Data Processing
 Data Storage
 Data Movement
 Control

Types of computer
 Analog
 Digital
Analog vs. Digital Computer
 Analog Computers work on the analog signals.
 Analog signals are continuous in nature.
 Digital computers work on digital signals.
 The digital signals are discrete in nature.
Image [1]

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Types of Computer
 Embedded computers
 Personal computers
 Servers and Enterprise systems
 Supercomputers and Grid computers

Embedded computers
 Embedded computers are integrated into a larger device or system in order to
automatically monitor and control a physical process or environment.
 They are used for a specific purpose rather than for general processing tasks.
 Typical applications include industrial and home automation, appliances,
telecommunication products, and vehicles.

Personal computers
 Personal computers are used in homes, educational institutions, and business and
engineering office settings, primarily for dedicated individual use.
 They support a variety of applications such as general computation, document
preparation, computer-aided design, audiovisual entertainment, interpersonal
communication, and Internet browsing.

Servers and Enterprise systems

 Servers and Enterprise systems are large computers that are meant to be shared by a
potentially large number of users who access them from some form of personal
computer over a public or private network.
 Such computers may host large databases and provide information processing for a
government agency or a commercial organization.

Supercomputers and Grid computers

 Offer the highest performance.
 The most expensive and physically the largest category of computers
 Supercomputers are used for the highly demanding computations needed in weather
forecasting, engineering design and simulation, and scientific work.
 Grid computers provide a more cost-effective alternative. They combine a large
number of personal computers and disk storage units in a physically distributed high-
speed network, called a grid.
 By evenly distributing the computational workload across the grid, it is possible to
achieve high performance on large applications ranging from numerical computation
to information searching.

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COMPUTER ORGANIZATION vs. COMPUTER ARCHITECTURE

Computer Architecture:
Computer architecture refers to those attributes of a system visible to a programmer or those
attributes that have a direct impact on the logical execution of a program.
Examples of architectural attributes include the instruction set, the number of bits used to
represent various data types (e.g., numbers, characters), I/O mechanisms, and techniques for
addressing memory.
Computer Organization:
Computer organization refers to the operational units and their interconnections that realize
the architectural specifications. Organizational attributes include those hardware details
transparent to the programmer, such as control signals; interfaces between the computer and
peripherals; and the memory technology used.

Computer Organization vs. Computer Architecture:

For example, it is an architectural design issue whether a computer will have a multiply
instruction. It is an organizational issue whether that instruction will be implemented by a
special multiply unit or by a mechanism that makes repeated use of the add unit of the
system.

Difference between Computer Organization and Computer Architecture:

Computer Architecture Computer Organization
Architecture describes what the computer Organization describes how the computer
does does it.
CA deals with the functional behaviour of the CO deals with the structural relationship
computer
CA deals with high level design issues CO deals with low level design issues
For designing a computer, its architecture is For designing a computer organization is
fixed first decided after its architecture.

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Computer Architecture Models:
There are two basic types of architecture.
• Von-Neumann Architecture
• Harvard Architecture

Von-Neumann Architecture:
Instruction and data use the same signal pathways and memory.
It uses Stored Program Principle. Example: PC
Harvard Architecture:
Harvard Architecture uses the physically separate storage and signal pathways for their
instructions and data
Example Micro controller based Computer

Von-Neumann Architecture

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 FUNCTIONAL UNITS & INTERCONNECTIONS
A computer consists of five functionally independent main parts: input, memory, arithmetic
and logic, output, and control units. The input unit accepts coded information from human
operators using devices such as keyboards or from other computers over digital
communication lines. The information received is stored in the computer’s memory, either
for later use or to be processed immediately by the arithmetic and logic unit. The processing
steps are specified by a program that is also stored in the memory. Finally, the results are sent
back to the outside world through the output unit. All of these actions are coordinated by the
control unit. An interconnection network provides the means for the functional units to
exchange information and coordinate their actions.

Input Unit: Computers accept coded information through input units. Examples of input
devices are keyboard, touchpad, mouse, joystick, trackball, microphones and, cameras.

Output Unit: With the help of output unit computer results can be provided to the user.
Examples of output devices are printer, plotter, speaker, and graphic displays

Central Processing Unit: Controls the operation of the computer and performs the
processing functions. Processor has the following components:

 ALU: performs the data processing functions such as execution of arithmetic and
logic operations.
 CU: controls the operations of the CPU.
 Registers: provide internal storage to CPU as temporary storage of data.
 Internal interconnection: some communication mechanism among ALU, CU and
registers

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Memory Unit: Memory unit is used to store the data and program. CPU works with the
information stored in memory (primary memory or main memory). The memory used at
various levels in the computer given below:

Secondary memories are another kind of memories used for the permanent storage of the data
and program. Examples of secondary memories are Hard disk, floppy disk, magnetic tapes,
and optical disks.

Volatile Memory and Non-Volatile Memory

Volatile Memory is also referred as temporary memory. The data within the volatile
memory is stored till the system is capable of, but once the system is turned off the data
within the volatile memory is deleted automatically. Examples are RAM (Random
Access Memory) and Cache Memory.

Non-volatile memory is computer memory that can retain the stored information even
when not powered. Examples of non-volatile memory include read-only memory (see
ROM), flash memory, most types of magnetic computer storage devices (e.g. hard
disks, floppy disc and magnetic tape), and optical disc.

System interconnection: An interconnection network provides the means for the functional
units to exchange information and coordinate their actions. Example: system bus.

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 INTERCONNECTION SYSTEM

Interconnection System:

The interconnection structure must support the following types of transfers:

 Memory to processor
 Processor to memory
 I/O to processor
 Processor to I/O
 I/O to or from memory

Memory to processor: The processor reads an instruction or a unit of data from memory.
Processor to memory: The processor writes a unit of data to memory.
I/O to processor: The processor reads data from an Input device via an I/O module.
Processor to I/O: The processor sends data to the output device an I/O module.
I/O to or from memory: For these two cases, an I/O module is allowed to exchange data
directly with memory, without going through the processor, using direct memory access
(DMA).

BUS System:

A bus is a communication pathway connecting two or more devices. A key characteristic of a

bus is that it is a shared transmission medium. Multiple devices connect to the bus, and a
signal transmitted by any one device is available for reception by all other devices attached to
the bus. If two devices transmit during the same time period, their signals will overlap and
become garbled. Thus, only one device at a time can successfully transmit.

Typically, a bus consists of multiple communication pathways, or lines. Each line is capable
of transmitting signals representing binary 1 and binary 0. Over time, a sequence of binary
digits can be transmitted across a single line. Taken together, several lines of a bus can be
used to transmit binary digits simultaneously (in parallel).
For example, an 8-bit unit of data can be transmitted over eight bus lines.

Computer systems contain a number of different buses that provide pathways between
components at various levels of the computer system hierarchy.

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System Bus:

A bus that connects major computer components (processor, memory, I/O) is called a system
bus. The most common computer interconnection structures are based on the use of one or
more system buses.

Bus Structure

A system bus consists, typically, hundreds of separate lines. Each line is assigned a particular
meaning or function. Although there are many different bus designs, on any bus the lines can
be classified into three functional groups
• Data Lines.
• Address Lines.
• Control Lines.
In addition, there may be power distribution lines that supply power to the attached modules.

Data Lines:

The data lines provide a path for moving data among system modules. These lines,
collectively, are called the data bus. The data bus may consist of 32, 64, 128, or even more
separate lines, the number of lines being referred to as the width of the data bus.

The width of the data bus is a key factor in determining overall system performance. For
example, if the data bus is 32 bits wide and each instruction is 64 bits long, then the processor
must access the memory module twice during each instruction cycle.

Address Lines

The address lines are used to designate the source or destination of the data on the data bus.
For example, if the processor wishes to read a word (8, 16, or 32 bits) of data from memory,

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it puts the address of the desired word on the address lines. Clearly, the width of the address
bus determines the maximum possible memory capacity of the system.

Control Lines

The control lines are used to control the access to and the use of the data and address lines.
Because the data and address lines are shared by all components, there must be a means of
controlling their use. Control signals transmit both command and timing information among
system modules.

Timing signals indicate the validity of data and address information. Command signals
specify operations to be performed.

Typical control lines include

 Memory write: Causes data on the bus to be written into the addressed location
 Memory read: Causes data from the addressed location to be placed on the bus
 I/O write: Causes data on the bus to be output to the addressed I/O port
 I/O read: Causes data from the addressed I/O port to be placed on the bus
 Transfer ACK: Indicates that data have been accepted from or placed on the bus
 Bus request: Indicates that a module needs to gain control of the bus
 Bus grant: Indicates that a requesting module has been granted control of the bus
 Interrupt request: Indicates that an interrupt is pending
 Interrupt ACK: Acknowledges that the pending interrupt has been recognized
 Clock: Is used to synchronize operations
 Reset: Initializes all modules

Bus Operation:

The operation of the bus is as follows. If one module wishes to send data to another, it must
do two things:

(1) Obtain the use of the bus, and

(2) Transfer data via the bus.

If one module wishes to request data from another module, it must (1) obtain the use of the
bus, and (2) transfer a request to the other module over the appropriate control and address
lines. It must then wait for that second module to send the data.

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Bus Types:

Bus lines can be separated into two generic types:

 Dedicated
 Multiplexed.

Dedicated Bus Line

A dedicated bus line is permanently assigned either to one function or to a physical subset of
computer components.

Functionally Dedicated

An example of functional dedication is the use of separate dedicated address and data lines.

Physically Dedicated

Physical dedication refers to the use of multiple buses, each of which connects only a subset
of modules.

A typical example is the use of an I/O bus to interconnect all I/O modules; this bus is then
connected to the main bus through some type of I/O adapter module.

The potential advantage of physical dedication is high throughput, because there is less bus
contention.

A disadvantage is the increased size and cost of the system.

Multiplexed Bus:

For example, address and data information may be transmitted over the same set of lines
using an Address Valid control line. At the beginning of a data transfer, the address is placed
on the bus and the Address Valid line is activated. At this point, each module has a specified
period of time to copy the address and determine if it is the addressed module. The address is
then removed from the bus, and the same bus connections are used for the subsequent read or
write data transfer. This method of using the same lines for multiple purposes is known as
time multiplexing.

The advantage of time multiplexing is the use of fewer lines, which saves space and, usually,
cost.

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The disadvantage is that more complex circuitry is needed within each module. Also, there is
a potential reduction in performance because certain events that share the same lines cannot
take place in parallel.

Synchronous and Asynchronous Bus

TIMING
Timing refers to the way in which events are coordinated on the bus. Buses use either
synchronous timing or asynchronous timing.

Synchronous Timing
With synchronous timing, the occurrence of events on the bus is determined by a clock.
The bus includes a clock line upon which a clock transmits a regular sequence of alternating
1s and 0s of equal duration.
A single 1–0 transmission is referred to as a clock cycle or a bus cycle and defines a time
slot. All other devices on the bus can read the clock line, and all events start at the beginning
of a clock cycle.

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In this simple example,
The processor places a memory address on the address lines during the first clock cycle and
may assert various status lines.
Once the address lines have stabilized, the processor issues an address enable signal.

For a read operation,

The processor issues a read command at the start of the second cycle. A memory module
recognizes the address and, after a delay of one cycle, places the data on the data lines. The
processor reads the data from the data lines and drops the read signal.

For a write operation,

The processor puts the data on the data lines at the start of the second cycle, and issues a
write command after the data lines have stabilized.
The memory module copies the information from the data lines during the third clock cycle.

Asynchronous Timing
With asynchronous timing, the occurrence of one event on a bus follows and depends on the
occurrence of a previous event.

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For Read Operation:
In the simple read example of the shown image (a),
The processor places address and status signals on the bus.
After pausing for these signals to stabilize, it issues a read command, indicating the presence
of valid address and control signals.
The appropriate memory decodes the address and responds by placing the data on the data
line.
Once the data lines have stabilized, the memory module asserts the acknowledged line to
signal the processor that the data are available.
Once the master has read the data from the data lines, it deasserts the read signal. This causes
the memory module to drop the data and acknowledge lines.
Finally, once the acknowledge line is dropped; the master removes the address information.
For Write Operation
Image (b) shows a simple asynchronous write operation.
In this case, the master places the data on the data line at the same time that is puts signals on
the status and address lines.
The memory module responds to the write command by copying the data from the data lines
and then asserting the acknowledge line.
The master then drops the write signal and the memory module drops the acknowledge
signal.

Synchronous timing is simpler to implement and test. However, it is less flexible than
asynchronous timing. Because all devices on a synchronous bus are tied to a fixed clock rate,
the system cannot take advantage of advances in device performance.
With asynchronous timing, a mixture of slow and fast devices, using older and newer
technology, can share a bus.

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 BUS ARBITRATION

Arbitration
There are occasions when two or more entities contend for the use of a single resource in
a computer system. For example, two devices may need to access a given slave at the same
time.
In such cases, it is necessary to decide which device will access the slave first. The decision
is usually made in an arbitration process performed by an arbiter circuit. The arbitration
process starts by each device sending a request to use the shared resource. The arbiter
associates priorities with individual requests. If it receives two requests at the same time, it
grants the use of the slave to the device having the higher priority first.

To illustrate the arbitration process, we consider the case where a single bus is the shared
resource. The device that initiates data transfer requests on the bus is the bus master. It is
possible that several devices in a computer system need to be bus masters to transfer data. For
example, an I/O device needs to be a bus master to transfer data directly to or from the
computer’s memory. Since the bus is a single shared facility, it is essential to provide orderly
access to it by the bus masters.

A device that wishes to use the bus sends a request to the arbiter. When multiple requests
arrive at the same time, the arbiter selects one request and grants the bus to the corresponding
device.

Types of Bus Arbitration:

There are two approaches to Bus Arbitration
A. Centralized Bus Arbitration: in centralized, a single hardware device, referred to as a
bus arbiter, is responsible for allocating the time on bus. The arbiter device may be a separate
module or the part of processor. Single bus arbiter performs the required arbitration.
B. Distributed Bus Arbitration: Devices participate in the selection of the next master. In
distributed scheme, there is no central controller logic. Rather, each module contains the
access control logic and the modules act together to share the bus.

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Centralized Bus Arbitration Techniques:
 Daisy Chaining Method
 Polling Method
 Independent Request Method

A) Daisy Chaining Method

 All bus masters use the same line for Bus Request.
 If the Bus Busy line is inactive, the Bus Controller gives the Bus Grant signal.
 Bus Grant signal is propagated serially through all masters starting from the nearest
one.
 The bus master, which requires the system bus, stops this signal, activates the Bus
Busy line, and takes control of the system bus.

Advantages of Daisy Chaining Method

 The design is simple.
 The number of control lines is less.
 Also adding new bus masters is easy.

Disadvantages of Daisy Chaining Method

 The priority of bus masters is rigid and depends on the physical proximity of the bus masters
with the bus arbiter i.e. The one nearest to the Bus Arbiter gets the highest priority. Therefore, it
has poor performance.
 The bus is granted serially and hence a propagation delay is induced in the circuit. Therefore, it
has poor priority mechanism.
 Failure of one of the devices may fail the entire system. Therefore, it has poor reliability.

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 B) Polling Method
 Here also all bus masters use the same line for Bus Requests.
 Here the controller generates a binary address for the master. E.g: To connect 8 bus
masters we need 3 address lines (23= 8).
 In response to a Bus Request, the controller "polls" the bus masters by sending a
sequence of bus master addresses on the address lines. Eg: 000, 010, 100, 011 etc.
 The selected master activates the Bus Busy line and takes control of the bus.

Advantages
 This method is also quite simple.
 The priority is flexible and can easily be changed by altering the polling sequence.
 If one module fails, the entire system does not fail.

Disadvantages
 Adding more bus masters is difficult as it increases the number of address lines of the
circuit. E.g: In the above circuit to add the 9th Bus Master we need 4 address lines.
 Time Consuming

Non productive polling sequence: the arbiter generated the polling sequence for the
module which did not request the bus.

C) Independent Request Method

 Here, all bus masters have their individual Bus Request and Bus Grant lines.
 The controller thus knows which master has requested, so the bus is granted to that
master.
 Priorities of the masters are predefined so on simultaneous Bus Requests, the bus is
granted based on the priority, provided the Bus Busy line is not active.

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  The Controller consists of encoder and decoder logic for the priorities.

 Bus Arbitration is a fast and dynamic priority is also possible.

 The speed of Bus Arbitration is independent of the number of devices connected.
 Better Performance

 The number of control lines required is more (2n line required for n devices).
 Hardware cost is high as large number. of control lines is required.

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 REGISTER, BUS AND MEMORY TRANSFER
Register Transfer
The internal hardware organization of a digital computer is best defined by specifying:
1. The set of registers it contains and their function.
2. The sequence of microoperations performed on the binary information stored in the
registers.
3. The control that initiates the sequence of microoperations.

The operations executed on data stored in registers are called microoperations. A

microoperation is an elementary operation performed on the information stored in one or
more registers. The result of the operation may replace the previous binary information of a
register or may be transferred to another register. Examples of microoperations are shift,
count, clear, and load.

Register Transfer Language:

The symbolic notation used to describe the microoperation transfers among registers is called
a register transfer language. The term "register transfer" implies the availability of hardware
logic circuits that can perform a stated microoperation and transfer the result of the operation
to the same or another register.
Computer registers are designated by capital letters (sometimes followed by numerals)

Register Transfer:
Information transfer from one register to another is designated in symbolic form by means of
a replacement operator. The statement
R2 R1
denotes a transfer of the content of register R1 into register R2. It designates a replacement of
the content of R2 by the content of R l. By definition, the content of the source register R1
does not change after the transfer. A statement that specifies a register transfer implies that
circuits are available from the outputs of the source register to the inputs of the
destination register and that the destination register has a parallel load capability.

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Normally, we want the transfer to occur only under a predetermined control condition. This
can be shown by means of an if-then statement.

If (P = 1) then (R2 R1)

where P is a control signal generated in the control section. It is sometimes convenient to

separate the control variables from the register transfer operation by specifying a control
function. A control function is a Boolean variable that is equal to 1 or 0. The control function
is included in the statement as follows:
P: R2 R1
The control condition is terminated with a colon. It symbolizes the requirement that the
transfer operation be executed by the hardware only if P = 1.

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Figure shows the block diagram that depicts the transfer from R1 to R2. The n outputs of
register R1 are connected to the n inputs of register R2. Register R2 has a load input that is
activated by the control variable P. It is assumed that the control variable is synchronized
with the same clock as the one applied to the register. in the timing diagram, P is activated in
the control section by the rising edge of a clock pulse at time t . The next positive transition
of the clock at time t + 1finds the load input active and the data inputs of R2 are then loaded
into the register in parallel. P may go back to 0 at time t + 1; otherwise, the transfer will occur
with every clock pulse transition while P remains active.

Memory Transfer:

Memory Read:
Consider a memory unit that receives the address from a register, called the address register,
symbolized by AR. The data are transferred to another register, called the data register,
symbolized by DR . The read operation can be stated as follows:

Read: DR M [AR]
This causes a transfer of information into DR from the memory word M selected by the
address in AR.

Memory Write:
The write operation transfers the content of a data register to a memory word M selected by
the address register.
Write: M [AR] DR

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 Encoder and Decoder

An encoder is combinational circuit that accepts an active (or high or 1) on one of its 2n
inputs and converts/ encodes it into n-bit binary coded output.

A decoder is a combinational circuit that converts/decodes n-bit binary input to one of its 2n
outputs.

For both the encoders and decoders enable input E has the important role.
If Enable E =0 then encoder or decoder is in inactive state
If Enable E =1 then encoder or decoder is in active state

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Role or Applications of encoders in computer organization:
 Code conversions
 Priority encoders/ priority handling in bus arbitration
 Priority encoders/ priority handling in Interrupts
 To reduce the number of bits

Role or Applications of decoders in computer organization:

 Memory address decoding
 Code conversions
 General register organization
 Designing of a common bus using tri-state buffers
 Instruction decoding
 Implementation of vertical micro-instruction format

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 Multiplexer and De-multiplexer

4x1 Mux:

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Applications of multiplexers:
 General register organization
 Designing of a common bus using multiplexers
 Communication system
 Telephone networks
 Parallel to serial conversion

Applications of de-multiplexers:
 Communication system
 Telephone networks
 Serial to Parallel conversion

BUS transfer
A typical digital computer has many registers, and paths must be provided to transfer
information from one register to another. A more efficient scheme for transferring
information between registers in a multiple-register configuration is a common bus system.

A bus structure consists of a set of common lines, one for each bit of a register, through
which binary information is transferred one at a time. Control signals determine which
register is selected by the bus during each particular register transfer.
Common Bus Structure can be implemented by:
 BUS System Using Multiplexers
 BUS System Using Tri-State Buffer

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BUS System Using Multiplexers:
In general, a bus system will multiplex k registers of n bits each to produce an n-line common
bus.
The number of Multiplexers required= size of registers
The size of multiplexer= Numbers of register x 1

Question: Construct a common bus for 4 registers of 4-bit each.

Number of multiplexers required= 4

Size of each multiplexer= 4x1
Number of selection lines=2

 Each register has four bits, numbered 0 through 3.

 The bus consists of four 4 x 1 multiplexers.
 Each Multiplexer has four data inputs, 0 through 3, and two selection inputs, S1 and
S0
 The diagram shows that the bits in the same significant position in each register are
connected to the data inputs of one multiplexer to form one line of the bus.
 Thus MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four
1 bits of the registers, and similarly for the other two bits.
The two selection lines S1 and S0 are connected to the selection inputs of all four
multiplexers. The selection lines choose the four bits of one register:

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Question: Draw the common bus using multiplexers for 8 registers each having 3-bit
size.
Question: Draw the common bus using multiplexers for 16 registers each having 2-bit
size.

BUS SYSTEM USING TRI-STATE BUFFER

Bus System Using Tristate Buffer:
A bus system can be constructed with three-state gates instead of multiplexers.
A three-state gate is a digital circuit that exhibits three states:
 Logic 1
 Logic 0
 High impedance

Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate. The third
state is a high-impedance state. The high-impedance state behaves like an open circuit, which
means that the output is disconnected and does not have logic significance. The graphic
symbol of a three-state buffer gate is shown

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The control input determines the output state. When the control input is equal to 1, the output
is enabled and the gate behaves like any conventional buffer, with the output equal to the
normal input. When the control input is 0, the output is disabled and the gate goes to a high-
impedance state, regardless of the value in the normal input.

Construction of a bus system with three-state buffers:

For designing of a bus using tri-state buffer the following formulas will be used
Number of stages= size of register
Number of tri-state buffers used for a single stage =number of registers
Number of decoders used= number of stages = size of register
Number of output lines in a decoder = number of tristate buffer in a stage= number of
registers
Size of decoder = n x number of register

Question:
Construct a common bus with three-state buffers for 4 registers of 2-bit each. Or
Calculate the following for a common bus with three-state buffers for 4 registers of 2-bit
each.
Number of stages= size of register =2
Number of tri-state buffers used for a single stage =number of registers =4
Number of decoders used= number of stages = size of register =2
Number of output lines in a decoder = number of tristate buffer in a stage= number of
registers =4
Size of decoder = n x number of register = n x 4
Size of decoder = 2 x 4
Selection Table:

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The construction of a bus system with three-state buffers is demonstrated in the following
figure:

The outputs of four buffers are connected together to form a single bus line. The control
inputs to the buffers determine which of the four normal inputs will communicate with the
bus line.
No more than one buffer may be in the active state at any given time. One way to ensure that
no more than one control input is active at any given time is to use a decoder.
When the enable input of the decoder is 0, all of its four outputs are 0, and the bus line is in a
high-impedance state because all four buffers are disabled. When the enable input is active,
one of the three-state buffers will be active, depending on the binary value in the select inputs
of the decoder.
To construct a common bus for four registers of n bits each using three state buffers, we need
n circuits with four buffers in each. Each group of four buffers receives one significant bit
from the four registers. Each common output produces one of the lines for the common bus
for a total of n lines. Only one decoder is necessary to select between the four registers.

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 PROCESSOR ORGANIZATION
The processor with the system bus has been shown in the following figure:

What are the functions of a processor?

 Fetch instruction
 Interpret instruction (or decode the instruction)
 Process data
 Write data
Fetch instruction: The processor reads an instruction from memory.
Interpret instruction (or decode the instruction): The instruction is decoded to determine
what action is required.
Process data: The execution of an instruction may require performing some arithmetic or
logical operation on data.
Write data: The results of an execution may require writing data to memory or an I/O
module.

Note: The basic operations are addition, shifting, and complement.

The arithmetic operations such as subtractions, multiplication and division are performed
with the help of these basic operations.

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What is the internal structure of the processor?

Components of the processor:

 ALU (Arithmetic and Logic Unit)
 CU (Control Unit)
 Registers
 Internal Bus system
The ALU does the actual computation or processing of data. ALU (Arithmetic and Logic
Unit) is a group of circuits that performs arithmetic (addition, increment/decrement or
complement) and logic (AND, OR, NOT, X-OR etc) operations.
The control unit controls the movement of data and instructions into and out of the processor
and controls the operation of the ALU. A control unit is a group of circuits that provides
timing and signals to all the operations in the computer and controls the data flow.
A minimal internal memory, consisting of a set of storage locations, called registers.An
internal processor bus is needed to transfer data between the various registers and the ALU

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because the ALU in fact operates only on data in the internal processor memory. Some
mechanism that provides for communication among the control unit, ALU, and registers

Register organization:
 User-visible registers
 Control and status registers

User-visible registers: used by the machine language or assembly language programmer.

User-visible registers:
 General purpose
 Data
 Address
 Condition codes
General-purpose registers can be assigned to a variety of functions by the programmer.
Data registers may be used only to hold data and cannot be employed in the calculation of an
operand address.
Address registers may themselves be somewhat general purpose, or they may be devoted to
a particular addressing mode.
Examples of address registers include the following:
 Segment pointers
 Index registers
 Stack pointer
• Segment pointers: In a machine with segmented addressing, a segment register holds the
address of the base of the segment. There may be multiple registers: for example, one for the
operating system and one for the current process.
• Index registers: These are used for indexed addressing and may be auto-indexed.
• Stack pointer: If there is user-visible stack addressing, then typically there is dedicated
register that points to the top of the stack. This allows implicit addressing; that is, push, pop,
and other stack instructions need not contain an explicit stack operand.

Condition codes
A final category of registers, which is at least partially visible to the user, holds condition
codes (also referred to as flags). Condition codes are bits set by the processor hardware as the

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result of operations. For example, an arithmetic operation may produce a positive, negative,
zero, or overflow result

Control and Status Registers

Control and status registers: Used by the control unit to control the operation of the processor
Four registers are essential to instruction execution:
• Program counter (PC): Contains the address of an instruction to be fetched
• Instruction register (IR): Contains the instruction most recently fetched
• Memory Address Register (MAR): Contains the address of a location in memory where a
word of data to be written to or read from.
• Memory buffer register (MBR) or Memory Data register (MDR): Contains a word of
data to be written to memory or the word most recently read.

Program Status Word (PSW):

Many processor designs include a register or set of registers, often known as the program
status word (PSW), that contain status information.
The PSW typically contains condition codes plus other status information. Common fields or
flags include the following:
 Sign Flag  Overflow Flag
 Zero Flag  Interrupt Enable/Disable Flag
 Equal Flag  Supervisor Flag
Sign: Contains the sign bit of the result of the last arithmetic operation.
Zero: Set when the result is 0.
Carry: Set if an operation resulted in a carry (addition) into or borrow (subtraction) out of a
high-order bit. Used for multiword arithmetic operations.
Equal: Set if a logical compare result is equality.
Overflow: Used to indicate arithmetic overflow.
Interrupt Enable/Disable: Used to enable or disable interrupts.
Supervisor: Indicates whether the processor is executing in supervisor or user mode. Certain
privileged instructions can be executed only in supervisor mode, and certain areas of memory
can be accessed only in supervisor mode.

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 GENERAL REGISTER ORGANIZATION

When a large number of registers are included in the CPU, it is most efficient to connect them
through a common bus system. The registers communicate with each other not only for direct
data transfers, but also while performing various microoperations. Hence it is necessary to
provide a common unit that can perform all the arithmetic, logic, and shift microoperations in
the processor.
A bus organization for seven CPU registers is shown in the following figure:

Steps:

1. The output of each register is connected to two multiplexers (MUX A and MUX B) to
form the two buses A and B. [Each Mux have 8 inputs: 7 Registers and 1 Input]
2. The selection lines in each multiplexer select one register or the input data for the
particular bus.
The three bits of SELA select a source input for the A input of the ALU.
The three bits of SELB select a source input for the B input of the ALU.

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 3. The A and B buses form the inputs to a common arithmetic logic unit (ALU). The
operation selected in the ALU determines the arithmetic or logic microoperation that
is to be performed. The five bits of OPR select one of the operations in the ALU.
4. The result of the microoperation is available for output data and also goes into the
inputs of all the registers.
5. The register that receives the information from the output bus is selected by a 3*8
decoder.
6. The decoder activates one of the register loads inputs, thus providing a transfer path
between the data in the output bus and the inputs of the selected destination register.
The three bits of SELD select a destination register.

The control unit that operates the CPU bus system directs the information flow through the
registers and ALU.

Control Word:
Control word specifies the binary selection inputs in the unit. For this example of 8 inputs(7
register one external input) and given 5 operation bits, the control word has been shown
below.
The length of control word = 3+3+3+5= 14 bits

Register Selection Table:

Table of operations performed by the ALU in this example:

Here 5 operation bits can specify maximum 32 operations. The following table specifies
some selected operations.

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For example, to perform the operation R1  R2 + R3, the control word will be:

Question:

A bus organized CPU which has 64 Registers with 8 bits in each, an ALU, and a destination
decoder. Solve the following:
a. How many multiplexers are there in a common bus?
b. What is the size of each multiplexer?
c. How many selection inputs are needed for MUX A and MUX B?
d. How many inputs and outputs are in decoder?
Formulate the control word for the system assuming the ALU has 127 operations.

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Compiled by‐ Mukesh Raj Page 38
 STACK ORGANIZATION

What is Stack?
A stack is a list of data elements, usually words, with the accessing restriction that elements
can be added or removed at one end of the list only. This end is called the top of the stack,
and the other end is called the bottom.
The following figure shows the example stack of 4 books.

A stack is a storage device that stores information in such a manner that the item stored
last is the first item retrieved.

Last-in–First-out (LIFO) Principle: The last data item placed on the stack is the first one
removed when retrieval begins. In other way, we may call it as First-in-Last out (FILO)
principle; the first data item placed on the stack will be removed in the last.
The structure is sometimes referred to as a pushdown stack.

How to work with Stack? Or

What are the operations to be performed onto the stack?
The terms push and pop are used to describe placing a new item on the stack and removing
the top item from the stack, respectively.
Push: To insert an element into Stack
Pop: To remove the topmost element from the stack

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A register is used to store the address of the topmost element of the stack which is known as
Stack pointer (SP). The stack pointer register SP contains a binary number whose value is
equal to the address of the element that is currently on top of the stack.

What are types of Stack?

 Register Stack
 Memory Stack

REGISTER STACK:
 A stack can be placed in a portion of a large memory or it can be organized as a
collection of a finite number of memory words or registers.
 Two one-bit registers namely FULL and EMPTY will be used to get the status of
stack such as whether the stack if full (containing all the elements according to the
capacity) or empty (containing no element).
 Numbering for N registers in a register stack: 0 to (N-1).
Example: the registers will be number from 0 to 7 in 8-register stack.

Overflow: An error condition occurs during insertion a new element when stack is full.
This condition is called overflow)
Underflow: An error condition occurs during removal of an element when stack is
empty. This condition is also called underflow)

Example: A register stack of 64 words or registers

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FULL is a one-bit flag register for showing the status of stack whether it is Full (containing
all 64 elements) or not.
 FULL=0 (Stack is not full)
 FULL=1 (Stack is full)
EMPTY is also a one-bit flag register for showing the status of stack whether it is Empty
(containing no element) or not
 EMPTY =0 (Stack is Not empty)
 EMPTY = 1 (Stack is Empty)

DR is the data register that holds the binary data to be written in to or read out of the stack.
Initially:
 FULL=0
 EMPTY=1
 SP=0

The above figure shows the organization of a 64-word register stack. The stack pointer
register SP contains a binary number whose value is equal to the address of the element that
is currently on top of the stack.

Suppose number of bits in register can be stored = k

Size of the register = k bits
Number of the registers in Stack = N
Then, value of k,

2k = N
K= ⌊log2 (N) ⌋ + 1

Example: In a 64-word stack, the stack pointer contains 6 bits because 26 =64

Initially, SP is cleared to 0, Empty is set to 1, and Full is cleared to 0, so that SP points to the
word at address 0 and the stack is marked empty and not full. If the stack is not full, a new
item is inserted with a push operation.

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PUSH Operation: The push operation is implemented with the following sequence of micro-
operations.

SP ←SP + 1 (Increment stack pointer)

M [SP] ← DR (Write item on top of the stack)
if (SP=0) then (Full ← 1) (Check if stack is full)
Empty ← 0 (Marked the stack not empty)
The stack pointer is incremented so that it points to the address of the next-higher word. A
memory write operation inserts the word from DR into the top of the stack. Note that SP
holds the address of the top of the stack and that M [SP] denotes the memory word specified
by the address presently available in SP.

Note:
The first item stored in the stack is at address 1.
The second last (or prior to last) item stored in the stack is at address 63.
The last item is stored at address 0

Initially, SP points to 0. The first item stored in the stack is at address 1. The last item is
stored at address 0, if SP reaches 0; the stack is full of item, so FULL is set to 1. This
condition is reached if the top item prior to the last push was in location 63 and after
increment SP, the last item stored in location 0. Once an item is stored in location 0, there are
no more empty register in the stack. If an item is written in the stack, obviously the stack
cannot be empty, so EMTY is cleared to 0.

Example: Insertion of items into the stack:

Add element ‘A’ to the Stack

 Initially: • Push an element:

FULL=0 EMPTY=1 SP= SP+1 = 0+1 =1
SP=0 M[SP] DR ( M[1]=A)
If (SP==0) No
EMPTY=0

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The following figure shows the Stack after inserting item ‘A’

The following figure shows the Stack after inserting item ‘B’

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The following figure shows the Stack after inserting item ‘C’

Three items are placed in the stack: A, B, and C in the order. Item C is on the top of the stack
so the SP points to address 3.

How does a stack pointer move across the ends of the stack?

How does SP points to address 0 from address 63 after incrementing SP by 1?

In a 64-word stack, the stack pointer contains 6 bits because 26 =64.
Since SP has only six bits, it cannot exceed a number greater than 63 (111111 in binary).
When after 63, SP is incremented by 1, the result is 0 since 111111 + 1 =1000000 in binary
according to the binary addition, but SP can accommodate only the six least significant bits i.e.
SP=000000.
How does SP points to address 63 from address 0 after decrementing by 1?
SP =0= 000000 (in binary)
SP=SP-1 =000000-1

The subtraction in digital computer system will be done using 2’s complement method. So, the
subtraction will be converted into binary addition like
SP = SP + (-1)
SP = SP + 2’s complement (+1)
= 000000 + 111111
= 111111
=63

How 2’s complement of 1 is calculated?

6-bit binary representation of 1 in binary is 000001
2’s complement (1) = 1’s complement (1) +1

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Compiled by‐ Mukesh Raj Page 45
POP Operation: The pop operation is implemented with the following sequence of micro-
operations.
DR← M [SP] (Read item from the top of stack)
SP ← SP-1 (Decrement stack Pointer)
If (SP=0) then (Empty ← 1) (Check if stack is empty)
FULL ← 0 (Mark the stack not full)
The top item is read from the stack into DR. The stack pointer is then decremented. If its
value reaches zero, the stack is empty, so Empty is set to 1. This condition is reached if the
item read was in location 1. Once this item is read out, SP is decremented and reaches the
value 0, which is the initial value of SP.
Note that if a pop operation reads the item from location 0 and then SP is decremented, SP
changes to 111111, which is equal to decimal 63. In this configuration, the word in address 0
receives the last item in the stack. Note also that an erroneous operation will result if the stack
is pushed when FULL=1 or popped when EMTY =1.
Example of removal of an element or pop operation:

 Given  Pop an item

Full = 0 DR← M [SP]  DR= M[3]= C
Empty= 0 SP= SP-1  SP=3-1= 2
SP=3 If (SP==0)  NO
M[SP]=C FULL=0

1. To remove the top item, the stack is popped by reading the memory word at address 3 and
decrementing the content of SP. Item B is now on top of the stack since SP holds address
2. Note that item C has read out but not physically removed. But it is logically out of the
stack. This does not matter because when the stack is pushed, a new item is written in its
place.

MEMORY STACK:
A stack can exist as a stand-alone unit or can be implemented in a random access memory
attached to CPU. The implementation of a stack in the CPU is done by assigning a portion of
memory to a stack operation and using a processor register as a Stack Pointer.

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Figure given below shows a portion of computer memory partitioned in to three segments
program, data and stack.

The Program Counter PC points at the address of the next instruction in the program.
The Address Register AR points at an array of data.
The Stack Pointer SP points at the top of the stack.
The three register are connected to a common address bus, and either one can provide an
address for memory. PC is used during the fetch phase to read an instruction. AR is used
during the execute phase to read an operand. SP is used to push or POP items into or from the
stack.
The initial value of SP is 4001 and the stack grows with decreasing addresses. Thus the first
item stored in the stack is at address 4000, the second item is stored at address 3999, and the
last address that can be used for the stack is 3000. No provisions are available for stack limit
checks. We assume that the items in the stack communicate with a data register DR.

Push Operation:
A new item is inserted with the push operation as follows.
SP← SP-1 (Decrement stack Pointer)
M [SP] ← DR (Write item on top of the stack)

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The stack pointer is decremented so that it points at the address of the next word. A Memory
write operation inserts the word from DR into the top of the stack.
Pop Operation:
A new item is deleted with a pop operation as follows.
DR← M [SP] (Read item from the top of stack)
SP←SP + 1 (increment stack Pointer)
The top item is read from the stack in to DR. The stack pointer is then incremented to point at
the next item in the stack.

Most computers do not provide hardware to check for stack overflow (FULL) or underflow
(Empty). The stack limit can be checked by using two processor register:
One to hold upper limit and other hold the lower limit. After the pop or push operation SP is
compared with lower or upper limit register.

Note:
In case of memory stack, stack may grow in direction of increasing addresses or decreasing
addresses of memory. It depends on the design of the system.

What are the applications of a Stack in a computer system?

There are the following applications in computer architecture.
• Subroutines Call
• Zero-address Instruction Implementation
• Infix notation to Post-fix notation conversion
• Evaluation of Arithmetic Expressions

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 Addressing Modes:
The operation field of an instruction specifies the operation to be performed. This operation
will be executed on some data which is stored in computer registers or the main memory.
The way any operand is selected during the program execution is dependent on the
addressing mode of the instruction. The purpose of using addressing modes is as follows:
 To give the programming versatility to the user.
 To reduce the number of bits in addressing field of instruction.
The addressing mode specifies a rule for interpreting or modifying the address field of
the instruction before the operand is actually referenced.
Simple instruction format:

Types of Addressing Modes:

Immediate Mode
Register Mode
Register Indirect Mode
Direct Addressing Mode
Indirect Addressing Mode
Displacement Addressing Modes:
 Relative Addressing Mode
 Base Addressing Mode
 Indexed Addressing Mode

Implied or Implicit Addressing Mode

Stack Addressing Mode
Auto-increment Addressing Mode
Auto-decrement Addressing Mode

Auto-decrement
NOTE: EffectiveAddressing
Address Mode
is the location where operand is present.
( ) parentheses denotes “the content of ”

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Immediate Mode
In this mode, the operand is specified in the instruction itself. An immediate mode instruction
has an operand field rather than the address field.
For example: ADD 8, denotes Add 8 to contents of accumulator. 8 is the operand here.
Advantages
No memory reference other than the instruction fetch is required to obtain the operand.
Disadvantages
Limited operand magnitude

Register Mode
In this mode the operand is stored in the register and this register is present in CPU. The
instruction has the address of the Register where the operand is stored.
The content of register will be operand in the register addressing mode
If the content of the register address field in an instruction is 5, then register R5 is intended
address, and the operand value is contained in R5.

Advantages
Shorter instructions and faster instruction fetch.
Faster memory access to the operand
No memory reference
Disadvantages
Very limited address space

Register Indirect Mode:

The address field of instruction specifies a register whose contents give the effective address
of the operand in the memory.
Effective address EA = (R)

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Advantages:
Fewer bits to select a register than a memory reference
Large address space
Disadvantage
Extra memory reference

Direct Addressing Mode:

In this mode, effective address of operand is present in instruction itself.
Effective Address = A
Advantages:
Single memory reference to access data
No additional calculations to find the effective address of the operand.
Disadvantage: Limited address space

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