Instruction decoding and execution

Mod I, Part IV
 Data Path
• The processing unit consists of data-path and control Unit.
• Simple computer architecture is decomposed into:
• Datapath for performing operations
• Control unit for controlling the data path operations
• A data-path is specified by:
• A set of registers to hold data
• functional units, such as arithmetic logic units and shifters, to
operate on data
• The microoperations performed on the data stored in the registers
• A control interface

2
 Datapath
• The set of registers
• Collection of individual registers
• A set of registers with common access resources called a
register file
• Microoperation implementation
• Buses - shared transfer paths
• Arithmetic-Logic Unit (ALU) - shared resource for
implementing arithmetic and logic microoperations
• Shifter - shared resource for implementing shift
microoperations

3
 Datapath Example

• Four parallel-load
Load enable A select B select
Write A address B address
registers (R0-R3) D data n

Load
• Two mux-based n
R0
n
2 2

register selectors
Load
• Register destination
R1
0
n 1
decoder n
2
MUX

0 3
• Mux B for external Load
1
2
MUX
R2
constant input n n
3

• Buses A and B with external Load R3

address and data outputs 0 1 2 3 n
n n
Register file
• ALU and Shifter with
Decoder
A data B data
D address
2 Constant in n n
Mux F for output select Destination select n 1 0
MB select
• Mux D for external data input Bus A
MUX B
Bus B
n
n
Address
Out
Data
• Logic for generating status bits
A B n Out
G select H select B
4 A B 2
V, C, N, Z V
S2:0 || Cin
Arithmetic/logic 0
S
IR Shifter IL 0
C unit (ALU)
G H
N n
n
Z Zero Detect
0 1
MF select MUX F Function unit
F
n n Data In
0 1
4 n
MD select
Bus D
MUX D
Datapath Example: Performing a Microoperation
Load enable A select B select

• Microoperation: R0 ← R1 + R2 Write
D data n
A address B address

▪ Apply 01 to A select to place Load R0 2 2

contents of R1 onto Bus A n n

▪ Apply 10 to B select to place Load

R1
0
contents of R2 onto B data and n 1
MUX
2
apply 0 to MB select to place n
0 3

B data on Bus B Load

R2
1
2
MUX

▪ Apply 0010 to G select to perform n n

3

addition G = Bus A + Bus B Load R3

n n
▪ Apply 0 to MF select and 0 to MD 0 1 2 3
Decoder
n Register file
A data B data
select to place the value of G onto 2
D address
Constant in n n

BUS D Destination select

MB select
n 1 0

▪ Apply 00 to Destination select to

MUX B Address
Bus A n
Bus B n Out
Data
enable the Load input to R0 G select
A B
H select
n
B
Out

4 A B 2
▪ Apply 1 to Load Enable to force the V
S2:0 || Cin
Arithmetic/logic 0
S
IR Shifter IL 0
unit (ALU)
Load input to R0 to 1 so that R0 is N
C
G
n
H
n
loaded on the clock pulse (not shown) Z Zero Detect
0 1
MF select MUX F Function unit
▪ The overall microoperation requires F
n n Data In

1 clock cycle MD select

Bus D
0 1
MUX D
n
 Arithmetic Logic Unit (ALU)
• Decompose the ALU into:
• An arithmetic circuit
• A logic circuit
• A selector to pick between the two circuits
• Arithmetic circuit design
• Decompose the arithmetic circuit into:
• An n-bit parallel adder
• A block of logic that selects four choices for the B input to the adder

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 Arithmetic Logic Unit (ALU)
Ci Ci Ci +1

Ai Ai
One stage of
Bi B i arithmetic
circuit 2-to-1
S0 S0
0 MUX
S1 S1
Gi

1
Ai S
B i One stage of
logic circuit
C in S0
S1

S2

• Most significant select signals, S0 for the arithmetic circuit and S1 for the
logic circuit, are wired together, completing the two select signals for the
logic circuit.