146 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO.

6, JUNE 1994

A Four-Quadrant CMOS Analog Multiplier for Analog Neural Networks

Navin Saxena and James J. Clark

Abstract- A four-quadrant CMOS analog multiplier is pre- four-quadrant multiplier presented in this paper has single
sented. The multiplier uses the square-law characteristic of an ended inputs. Thus, it can be more easily integrated as a
MOS transistor in saturation. Its major advantage over other module in a large system. Also, its area is much smaller than
four-quadrantmultipliersis its combination of small area and low
power consumption. In addition, unlike almost all other designs all of the four-quadrant multipliers mentioned above. These
of four-quadrant multipliers, this design has single ended inputs properties, along with its low power consumption, make it
so that the inputs do not need to be pre-processed before being very suitable for use in the implementation of large systems
fed to the multiplier, thus saving additional area. These properties like neural networks.
make the multiplier very suitable for use in the implementatior In this paper, the principle of operation and design of
of artificial neural networks. The design was fabricated through
MOSIS using the standard 2 pm CMOS process. Experimental the multiplier is first described. In this section, the design
results obtained from it are presented. of the multiplier, as well as how to arrive at the range of
operation of the multiplier, is described. In the next section, the
experimental results are presented. A summary of the achieved
I. INTRODUCTION
results is presented in conclusion.

R ECENTLY, analog multipliers have found use in the

area of artificial neural networks [3]-[6], [14]. These
massively parallel analog systems have demonstrated potential
11. PRINCIPLE OF OPERATION AND DESIGN
for solving a wide range of difficult problems, and thus analog The basic principle of operation of the proposed multiplier
computing techniques have become more widespread. Along is based on the well-known identity:
with this, the use of analog multipliers has also increased.
However, while high linearity is the prime issue for the
multipliers in conventional applications like modulation, de-
In our multiplier, the squaring is achieved using the square
modulation, frequency translation, etc., neural systems require
relationship between the gate-to-source voltage and the drain
their multipliers to be small and modular, and have low power
consumption. current on an MOS transistor in saturation. The following sub-
sections describe the circuit design and the range of operation
In the past, several designs of analog CMOS multipliers
of the multiplier.
have been proposed [l], [2], [7]-[13], 1151-[19]. However,
most of these multipliers were designed with the conventional
applications in mind. Of these, the multipliers in [l], [8], A. Design of the Four-Quadrant Multiplier
[12], [13], [15], [16], [18] use resistors, which are area- The circuit diagram of the multiplier is shown in Fig. 1.
intensive in VLSI layout, and hence are unsuitable for neural It consists of two current mirrors and five n-MOSFET's,
network applications. Some multipliers use switch-capacitor MI-5, which have the same aspect ratios. We assume that
techniques [7], [19], but the area of the capacitors cause the the five transistors are in the saturation region of operation.
multipliers to become large. The multipliers in [2], [lo], [17] Also, their sources and substrates are tied together so the
have differential inputs, requiring the values being fed to the body-effect is not important. According to the square-law
multiplier inputs to be generated from the actual values that characteristic of an MOS transistor in saturation, the drain
have to be multiplied by shifting andor inverting them. This currents 11 and 1 2 , flowing through transistors MI and M2,
makes the design non-modular because the user has to be respectively, are given by
aware of the biasing conditions and has to pre-process the
values to be multiplied before feeding them to the multiplier. 11 = K(V;,,1 va
- - VT)2 (1)
Only the multipliers in [ l l ] , [9] were designed specifically 1 2 = K(Vn2 - & - VT)2 (2)
for neural systems. However, the one in [ l l ] is limited
to two quadrant operation only, while the multiplier in [9] where Vnl and vn2 are the inputs to the multiplier, Vi is a
has differential inputs and output, which requires additional bias voltage (see Fig. l), V, is the threshold voltage of the
hardware and consequently more silicon area. In contrast, the transistors, and K is the transconductance parameter, which
is the same for the transistors because their aspect ratios
Manuscript received October 13, 1993; revised February 22, 1994. This
work was supported by the Joint Services Electronics program grant no. are same. Because of current mirror Cl, the current flowing
NOOO14-89-5-1023 and the NSF Center of Excellence in Systems Research, through transistor M5 is the same as that through transistor
University of MarylandMarvard University System Research Center grant no. M I , and since all other parameters are the same for the two
CDR-85-00108.
The authors are with the Division of Applied Sciences, Harvard University, transistors, their gate to source voltages must be equal. Hence,
Cambridge, MA 02138.
IEEE Log Number 9402124. vD5 = v n l + Vn2 - vb = vG3 (3)
0018-9200/94$04.00 0 1994 IEEE
~

SAXENA AND CLARK A FOUR-QUADRANT CMOS A" MULTIPLIER FOR ANALOG NEURAL NETWORKS 747

7Vdd 1
For M4 to be in saturation,
1
I
< -vT.
12
c2
' I c1
1 v
b (9)
since the first condition can always be satisfied by design. M5
t +I1 t I 2

4-
J
I1
is always in saturation because its gate and drain are connected.
However, the drain voltage of M5 should be such as to keep
the transistors in current mirror C1 in saturation. If C1 and C2
M5 I1 t are cascode current mirrors, the drain voltage of M5, MD5, has
to satisfy the following condition,
V D ~< VDD- VT - 26V, (10)

+
Vb
I
SV -
VGS- VT where, is equal to for the transistors in the
clirrent mirror. For a given current, SV depends on the aspect
ratio of the transistors in the current mirrors. Putting (3), (S),
Fig. 1. Circuit diagram of four-quadrant multiplier. and (10) together, we get:

where, v D 5 is the drain voltage of M5 and v G 3 is the gate

V, + VT < Knl + Kn2 < VDD- 2 6 V A + V, - VT (1 1)
voltage of M3. The currents 4 (using (3)) and 14, flowing where SV,,, is the maximum value of SV. Conditions de-
through transistors M3 and M4 are given by: scribed by (7) and (11) limit the range of operation of the
multiplier.
+
13 = K(Kn1 Kn2 - v b - VT)' (4) An example would explain how the range of operation can
14 = K(-& - VT)' ( 5 ) be obtained from these biasing constraints. Let VDDbe 5
V, V, be -2.4 V and SV, be 0.1 V. From the fabrication
where we assume that I$ < -VT. Current mirrors C1 and C2
parameters, we find VT to be 0.8 V. Substituting these values
feed currents I1 and 12 respectively onto the output node.
Thus, the output current Iout is given by:
+
in (11) we get lKnl Kn21 < 1.6 V. Thus, for symmetric
four-quadrant operation, we have (Knl,Kn21 < 0.8 V.
+
Iout = I1 I2 - I3 - 14. If one of the inputs is always positive (say 0.8 V > Knl >
0 V ). then by changing v b to - 2.0 V, we can make the
On substitution of I 1 , 4 ,I3 and I4 from (l), (2), (4), and ( 5 ) multiplier operate for l K n 2 ) < 1.2 V. If both the inputs are
into the above equation we obtain always positive, then by changing vb to - 0.8 V, we can
operate the circuit for the input range 1.6 V > K n l , KnZ > 0
Iout = -2KKn1Kn2. (6)
V. Similarly, the range can be changed to 0 V > K n l , K n 2 >
Thus, (6) gives four-quadrant multiplication for single ended -1.6 V, if both the inputs are negative. In this manner, by
inputs. changing the bias voltage v b we can operate the circuit at
In this design, the two inputs are not symmetrical because various input ranges. This fact can be used to increase the
the source at Knz has to sink current while the source at Knl overall range of the multiplier by changing v b depending on
does not. If we have a current mirror that gets current I1 from the sign of the input voltages.
current mirror Cl and sinks the same current from the node
at I&, the source at K n 2 will not have to sink current since 111. EXPERIMENTAL RESULTS
the current flowing in and out of the node will be the same.
The circuit shown in Fig. 1 was fabricated with a 2 pm
However, this will result in a slight increase in the area and
p-well standard CMOS fabrication process through MOSIS.
power consumption of the multiplier.
Fig. 2 shows a photograph of the fabricated chip. The active
chip area in 97 pm x 110 pm. The sources of all the n-MOS
B. Range of Operation
transistors are connected to their local substrate by putting
For an nMOS transistor to be in saturation, two conditions them in individual p-wells wherever necessary. The W/L ratio
have to be satisfied: for the five transistors is 4 p d 2 0 pm and cascode current
1. VDSshould be greater than VGS- VT mirrors were used.
2. VGS - VT > 0 For obtaining the dc-characteristics of the multiplier, the
where, VDSand VGSare the drain-to-source voltage and gate- bias voltage v b was chosen to be -2.4 V. VT for each
to-source voltage, respectively, of the transistor. For transistors nMOSFET was approximately 0.8 V. The supply voltage,
MI and M z , the first condition can always be satisfied by VDDwas 5 V. The dc transfer characteristics of the multiplier
design. For the second condition to be satisfied, are shown in Fig. 3, where Kn1 is varied between -1 V
and 1 V, for various values of which was also varied
K n 1 7 K n 2 > V, + VT- (7) between - 1V and 1V. As is expected, the multiplier shows an
approximately linear characteristic except when IKn1 + K n 2 I >
For M3 to be in saturation,
1.6 V, which is represented by the upper-left and upper-right
+
Knl K n z - V, - VT > 0. (8) part of the graph.
748 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. 6, JUNE 1994

Vinl(in Volts. peak to peak)

Fig. 2. Photograph of analog multiplier chip. Fig. 5. Total Harmonic Distortion (THD) analysis of multiplier output.

-
4 Modulated
output
I
1 -0.6 0.2 0.2 0.6 1

Vinl (in Volts)

Fig. 3. Output characteristic of four-quadrant multiplier.

Fig. 6. Modulated output, one input 2 liHz and the other 85 WIZ.

sine wave of 2 kHz is applied to vnl

and the other input
voltage is kept constant. Fig. 5 shows the THD as a function
of the peak-to-peak voltage of Kn1 for a constant vnz
of 0.8
V. As can be seen from the graph, the THD is less than 2%
for the given range, except when the peak-to-peak voltage of
vnl exceeds 1.6 V. In that case, the linearity is decreased
+
because the condition for saturation, vn1 Knz < 1.6 V, is
not satisfied. Even when the p-p voltage of Vn1 is 2 V, the
-le-06 THD is less than 3%. While this accuracy is modest, it is
0 0.3 0.6 0.9 1.2 1.5
sufficient for most neural network applications.
Vinl (in Volts) We investigate the behavior of the circuit as a modulator
Fig. 4. Output characteristic of multiplier for positive inputs only.
by feeding it a sinusoidal voltage of 2 kHz and peak-to-peak
voltage of 0.8 V at one input, and another sinusoidal voltage of
frequency 85 kHz and of peak-to-peak voltage 1 V at the other
To demonstrate how the input range can be adjusted, we input. The current at the multiplier output is passed through a
make the bias voltage Vb equal 0.8 V and measure the dc current-to-voltage converter and displayed on an oscilloscope.
characteristics of the circuit with both inputs varying from Fig. 6 shows the modulated output as seen on the oscilloscope.
0 to 1.6 V. The dc characteristics are shown in Fig. 4. The -3 dB bandwidth of the multiplier was measured to be
Thus the input range of the multiplier has been shifted from 115 kHz. The simulated -3 dB bandwidth was 4.5 MHz. The
Ivnl,vn21 < 0.8 V to 0 V < vnl,vn2< 1.6 V. anomaly is explained by the fact that during measurement,
The non-linearity of the multiplier is investigated by mea- the multiplier was driving a pad, which slowed it down
suring the total harmonic distortion (THD) of the circuit. A considerably.
SAXENA AND CLARK: A FOUR-QUADRANT CMOS ANALOG MULTIPLIER FOR ANALOG NEURAL NETWORKS 149

The maximum power consumption for the multiplier within ACKNOWLEDGMENT

its operating range was approximately 1 mW, which is towards The authors would like to thank Prof. R. W. Brockett, Prof.
the lower end for the four-quadrant multipliers mentioned W. Yang, Dr. D. J. Friedman and Dr. P. N. Belhumeur for
in this paper. The power consumption in the multiplier is their suggestions and support. They would also like to thank
proportional to the aspect ratio of the five transistors, M1-5, the reviewers for their helpful comments.
all other parameters remaining constant. Hence, we can further
reduce the power consumption of this circuit by decreasing the
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