DEPARTMENT OF

COMPUTER SCIENCE & ENGINEERING

LAB HAND BOOK

Computer Organization Lab

(KCS-352)
SUBMITTED TO

Mr. Rohit Agarwal

Ambalika Institute of Management and Technology,

Lucknow

Name of Student:
Roll No: Branch: Session:
 KCS-352 Computer Organization Lab

LIST OF EXPERIMENTS

S. No.: Experiments
1 Implementing HALF ADDER, FULL ADDER using basic logic
2 Implementing Binary -to -Gray, Gray -to -Binary code conversions.
3 Implementing 3-8 line DECODER.
4 Implementing 4x1 and 8x1 MULTIPLEXERS
5 Verify the excitation tables of various FLIP-FLOPS
6 Design of an 8-bit Input/ Output system with four 8-bit Internal Registers
7 Design of an 8-bit ARITHMETIC LOGIC UNIT.
8 Design and implementation of SISO and SIPO shift registers

Note: The Instructor may add/delete/modify/tune experiments, wherever he/she feels in a

justified manner.
 INDEX
SL NAME OF LAB EXPERIMENT DATE SIGN REMARK
1 Implementing HALF ADDER, FULL ADDER
using basic logic
2 Implementing Binary -to -Gray, Gray -to -
Binary code conversions.
3 Implementing 3-8 line DECODER.
4 Implementing 4x1 and 8x1 MULTIPLEXERS
5 Verify the excitation tables of various FLIP-
FLOPS
6 Design of an 8-bit Input/ Output system with
four 8-bit Internal Registers
7 Design of an 8-bit ARITHMETIC LOGIC
UNIT.
8 Design and implementation of SISO and SIPO
shift registers

Appendices
I. Institute Vision
II. Institute Mission
III. CSE Department Vision
IV CSE Department Mission
V CSE Department PEOs
VI Program Outcomes (POs)
AMBALIKA INSTITUTE OF MANAGEMENT & TECHNOLOGY, LUCKNOW
DEPARTMENT OF INFORMATION TECHNOLOGY

AIMT Vision (Institute)

To nourish the students, blossom them into tomorrow’s world class professionals and
good human beings by inculcating the qualities of sincerity, integrity and social ethics.

AIMT Mission (Institute)

1. To provide the finest infra structure and excellent environment for the academic
growth of the students to bridge the gap between academia and the demand of
industry.
2. To expose students in various co- curricular activities to convert them into skilled
professionals.
3. To grind very enthusiastic engineering and management student to transform him
into hard working, committed, having zeal to excel, keeping the values of devotion,
concern and honesty.
4. To involve the students in extracurricular activities to make them responsible citizens.
 CSE Department Vision
To embrace students towards becoming computer professionals having problem
solving skills, leadership qualities, foster research & innovative ideas inculcating moral
values and social concerns

CSE Department Mission

1. To provide state of art facilities for high quality academic practices.
2. To focus advancement of quality & impact of research for the betterment of
society.
3. To nurture extra-curricular skills and ethical values in students to meet the
challenges of building a strong nation.

CSE Department PEOs

1. To prepare our students to find the suitable employment commensurate with their
qualification.
2. To create good entrepreneur who may contribute to the nation building and generate
job opportunity for others.
3. To develop proficiency in students for higher studies and R&D for the solution of
complex problems for betterment of the society.
 Program Outcome

• PO 1 Engineering Knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.
• PO 2 Problem Analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
• PO 3 Design/development of solutions: Design solutions for complex engineering problems
and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
• PO 4 Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions
• PO 5 Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex engineering
activities with an understanding of the limitations.
• PO 6 The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant
to the professional engineering practice.
• PO 7 Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
• PO 8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice
• PO 9 Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
• PO 10 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
• PO 11 Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
• PO 12 Life-long learning: Recognize the need for, and have the preparation and ability to engage
in independent and life-long learning in the broadest context of technological change.
 Experiment-1
Aim: Implementing HALF ADDER, FULL ADDER using basic logic gates

Apparatus (Components): Power supply, breadboard, ICs 7486, 7432, 7408, 7404, LEDs

Theory:
A digital adder circuit adds binary signals & a subtractor subtracts binary signals. Half
Adder/Subtractor is a basic ckt. that adds / subtracts 2 bits and generates sum or difference
along with Carry / Borrow. Unlike half adder or subtractor a full adder / subtractor has the
provision to take consideration of previous carry / borrow also.

Procedure: To do these practical following steps should be done:

– A digital adder circuit adds binary signals & a subtractor subtracts binary signals. Half
Adder / subtractor is a basic ckt. that adds / subtracts 2 bits and generates sum or difference
along with Carry / Borrow. Unlike half adder or subtractor a full adder / subtractor has the
provision to take consideration of previous carry / borrow also.

Connection and gates:

Fig 3.1 shows the diagram of half adder, full adder ,half subtractor
and full subtractor .

Conclusion :

Thus half & full Adder / Subtractor is studied

 Experiment - 2
Aim: Implementing Binary -to -Gray, Gray -to -Binary code conversions
Component

Apparatus: 1-74LS04 hex-inverter (NOT) TTL IC

1-74LS08 Quad-two input AND TTL IC 1
+5V Power supply 1- DC Voltmeter
STUDENT KIT
Theory-
Binary to Gray Code Converter
Binary code is a very simple representation of data using two values such as 0’s and 1’s,
and it is mainly used in the world of the computer. The binary code could be
a high (1) or low (0) value or else even a modify in value. Gray code or reflected binary code
estimates the binary code nature that is arranged with on & off indicators, usually denoted
with ones & zeros. These codes are used to look at clarity as well as error modification in
binary. The conversion of binary to gray code can be done by using a logic circuit The gray
code is a non-weighted code because there is no particular weight is assigned for the position
of the bit. A n-bit code can be attained by reproducing a n-1 bit code on an axis subsequent to
the rows of 2n-1, as well as placing the most significant bit of 0 over the axis with the most
significant bit of 1 beneath the axis

Procedure: Following should be done to understand this practical.

Let assume the Binary code digits be bo, b1, b2, b3 whereas the particular Gray Code can be
attained based on the following concept

For example take the binary value b3, b2, b1, b0 = 1101 and find the gray code g3, g2, g1,
g0 based on the above concept

RESULT-
g3=b3=1
g2 = b3 XOR b2 = 1 XOR 1 =0
g1= b2 XOR b1= 1 XOR 0 = 1
g0= b1 XOR b0= 0 XOR 1 = 1
The final gray code for the value of binary 1101 is 1011

Gray to Binary Code Converter

This gray to binary conversion method also uses the working concept of the EX-OR logic
gate among the bits of gray as well as binary bits. The following example with step by step
procedure may help to know the conversion concept of gray code to binary code.
 OBERVATION-
To change gray to binary code, take down the MSB digit of the gray code number, as the
primary digit or the MSB of the gray code is similar to the binary digit.
To get the next straight binary bit, it uses the XOR operation among the primary bit or MSB
bit of binary to the next bit of the gray code.
Similarly, to get the third straight binary bit, it uses the XOR operation among the second bit
or MSB bit of binary to the third MSD bit of the gray code and so on.
Example of Gray to Binary Code Converter
Let assume the Gray Code digits g3, g2, g1, g0 whereas the particular Binary code digits are
bo, b1, b2, b3 can be attained based on the following concept.

From the above operation, finally we can get the binary values like b3 = g3, b2 = b3 XOR
g2, b1= b2 XOR g1, b0 = b1 XOR g0.
For example take the gray value g3, g2, g1, g0 = 0011 and find the binary code b3, b2, b1,
b0 based on RESULT-
b3=g3=0
b2 = b3 XOR g2 = 0 XOR 0 =0
b1= b2 XOR g1= 0 XOR 1 = 1
b0= b1 XOR g0= 1 XOR 1 = 0
The final binary code for the value of gray 0011 is 0010
 Experiment - 3
Aim: To impliment 3*8 line decoder
To learn about working principle of decoder To learn and understand the working of IC
74LS139 To realize using basic gates as well as universal gates.

Apparatus ():IC74LS139, IC 7400, IC 7408, IC 7432, IC 7404, IC 7410, Patch chords, &
IC Trainer Kit

Theory and procedure : A decoder is a combinational circuit that connects the binary
information from ‘n’ input lines to a maximum of 2n unique output lines. Decoder is also
called a min-term generator/max-term generator. A min-term generator is constructed using
AND and NOT gates. The appropriate output is indicated by logic 1 (positive logic). Max-
term generator is constructed using NAND gates. The appropriate output is indicated by logic
0 (Negative logic). The IC 74139 accepts two binary inputs and when enable provides 4
individual active low outputs. The device has 2 enable inputs (Two active low).

3 Line to 8 Line Decoder

This decoder circuit gives 8 logic outputs for 3 inputs and has a enable pin. The circuit is
designed with AND and NAND logic gates. It takes 3 binary inputs and activates one of the
eight outputs. 3 to 8 line decoder circuit is also called as binary to an octal decoder.

The decoder circuit works only when the Enable pin (E) is high. S0, S1 and S2 are three
different inputs and D0, D1, D2, D3. D4. D5. D6. D7 are the eight output
 CIRCUIT DIAGRAM

3 to 8 Line Decoder Truth Table

S0 S1 S2 E D0 D1 D2 D3 D4 D5 D6 D7
x x x 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 1
0 0 1 1 0 0 0 0 0 0 1 0
0 1 0 1 0 0 0 0 0 1 0 0
0 1 1 1 0 0 0 0 1 0 0 0
1 0 0 1 0 0 0 1 0 0 0 0
1 0 1 1 0 0 1 0 0 0 0 0
1 1 0 1 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
The below table gives the truth table of 3 to 8 line decoder

Result- study and implementation of 3to 8 line decoder is successfully done

 Experiment - 4
Aim: Implementing 4x1 and 8x1 MULTIPLEXERS

Apparatus (Software): Power supply, STUDENT kit, IC 74151,

Ic pinout:

Fig shows the IC 74151

Theory
Multiplexer is a combinational ckt. that is one of the most widely used in digital design. The
multiplexer is a data selector which gates one out of several i/ps to a single o/p. It has n data
i/ps &one o/p line & m select lines where 2m = n. Depending upon the digital code applied
at the select inputs one out of n data input is selected & transmitted to a single o/p channel.
Normally strobe(G) input is incorporated which is generally active low which enables the
multiplexer when it is LOW. Strobe i/p helps in cascading. A 4:1 Mux. using NAND gate
can be designed as shown in dgm 1. No. of ICs are available such as 74157, 74158 (Quad
2:1 mux), 74352, 74153 (dual 4:1 Mux.), 74151A, 74152 (8:1 Mux.), 74150 (16:1 Mux). IC
74151A is a 8 : 1 multiplexer which provides two complementary o/ps Y & Y. The o/p Y is
same as the selected i/p & Y is its complement. The n:1 multiplexer can be used to realize a
m variable function. (2m= n, m is no. of select inputs

Procedure: Following is required to be study under this practical.

1) Give biasing to the IC.

2) Do necessary connections.
Conclusion

Thus multiplexer is studied.

Assignment

1) Verify the truth table of IC 74151, 8:1 Mux.

2) Connect two 74151 ICs in cascading & verify its operation as a 16:1 Mux.
3) Implement the function Y = AB+BC using 74151 & verify the truth t
 EXPERIMENT 5

Aim: Verify the excitation table of various FLIP-FLOPS

Equipments & Components Required:

S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1
3. Components Required:
S.No. Components Specification Quantity
7400, 7402,
1 Digital ICs 7404, 1 each
7408, 7432,
7486.
2 Patch cords - 6

Theory:
Flip-flops are synchronous bi-stable devices. The term synchronous means the output changes state
only when the clock input is triggered. That is, changes in the output occur in synchronization with
the clock. A flip-flop circuit has two outputs, one for the normal value and one for the complement
value of the stored bit. Since memory elements in sequential circuits are usually flip-flops, it is
worth summarizing the behaviour of various flip-flop types before proceeding further. All flip -
flops can be divided into four basic types: SR, JK, D and
T. They differ in the number of inputs and in the response invoked by different value of input
signals. The four types of flip -flops are defined in the Table below.
Circuit Diagram
Procedure:
● Collect the components necessary to accomplish this experiment.
● Plug the IC chip into the breadboard.
● Connect the supply voltage and ground lines to the chips. PIN7 = Ground
● and PIN14 = +5V.
● Make connections as shown in the respective circuit diagram.
● Connect the inputs of the gate to the input switches of the LED.
● Connect the output of the gate to the output LEDs.
● Once all connections have been done, turn on the power switch of the breadboard
● Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if L1 is
OFF Apply the various combination of inputs according to the truth table and observe
the condition of Output LEDs.

Result & Conclusion: Verified excitation table of various flip flops.

 EXPERIMENT 6

Aim: Design and implement 8-bit Input/Output System with four 8-bit internal registers

Equipment’s & Components Required :

S.No. Equipments Specification Quantity

1 Logic Simulator - 1

S.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 15

Theory:
A register is capable of shifting its binary information in one or both directions is known as shift
register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of
one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which
causes the shift in the output of the flip-flop. The simplest possible shift register is one that uses
only flip flop. The output of a given flip flop is connected to the input of next flip flop of the
register. Each clock pulse shifts the content of register one bit position to right.
LOGIC DIAGRAM:
8-bit Input/Output System with four 8-bit
internal register

Procedure:
● Connections are given as per circuit diagram.
● Logical inputs are given as per circuit diagram.
● Observe the output and verify the truth table.
Result & Conclusion: Verified 8-bit Input/Output System with four 8-bit internal registers on
simulator.
 EXPERIMENT 7

Aim: Design of an 8- bit ARITHMETIC LOGIC UNIT.

Equipment’s & Components Required :

S.No. Equipments Specification Quantity

1 Logic Simulator - 1

Theory:
ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,
subtraction, division, multiplication and logical operations like and, or, xor, nand, nor etc. A simple
block diagram of a 4 bit ALU for operations and, or, xor and Add is shown in the Logic diagram.

LOGIC DIAGRAM:
Block diagram of a 4 bit ALU
Design Issues :
The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal S1 and
S0 the circuit operates as follows:
for Control signal S1 = 0 , S0 = 0, the output is A And B, for
Control signal S1 = 0 , S0 = 1, the output is A Or B, for
Control signal S1 = 1 , S0 = 0, the output is A Xor B, for
Control signal S1 = 1 , S0 = 1, the output is A Add B.
The truth table for 16-bit ALU with capabilities similar to 74181 is shown here:
Required functionality of ALU (inputs and outputs are active high)
Procedure:
● Connections are given as per circuit diagram.
● Logical inputs are given as per circuit diagram.
● Observe the output and verify the truth table.

Result & Conclusion: Verified the design of an 8 bit ALU.

 EXPERIMENT 8

Aim: Design and implementation of SISO and SIPO shift registers

Equipments & Components Required:

SL.No. Equipments Specification Quantity

1 Logic Simulator -

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
3. IC TRAINER KIT - 1
4. PATCH CORDS - 15

Theory:
A register is capable of shifting its binary information in one or both directions is known as shift
register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of
one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which
causes the shift in the output of the flip flop. The simplest possible shift register is one that uses
only flip flop. The output of a given flip flop is connected to the input of next flip flop of the
register. Each clock pulse shifts the content of register one bit position to right.
LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:

Truth table
Serial in Serial out
CLK
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

SERIAL IN PARALLEL OUT:

 TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

Procedure:
● Connections are given as per circuit diagram.
● Logical inputs are given as per circuit diagram.
● Observe the output and verify the truth table.

Result: All Shift registers have been implemented & verified through truth table.