EE 2245 Microelectronies Labs Lab 7; Experiment: Single-Stage and Multi-Stage MOSFET Amplifiers HME: ao fel Hob _Namesand ID Numbers: AN % ines Material, instrument and software * CD4007UB MOSFET array x 1; VN0606 (power transistor) resistors and capacitors + Power supply, funetion generator, oscilloscope, and digital multi-meter. ‘+ HSPICE and Awaves Procedure In this lab, the CD4007UB MOSFET array is chosen to build various MOSFET amplifiers. This array consists of three N-MOSFETs and three P-MOSFETs. The definition of each pin is depicted in Fig. 1 Note thatthe body terminal in N-MOSFETs should always be connected to the most negative voltage, while those of P-MOSFETS should be connected to the most positive voltage. The CD4007 is a delicate device. Make sure you turn off the power supply before changing any cireuit connections. Use the model that {you established in Lab 6 to design the amplifiers and compare with the measured results. The VNO606 power transistor will be used for building the output stage of the audio amplifier. om i Ghe| [Ara ae es oS fa Fig, L: The CD4007 MOSFET array. ee LHF Fig, 2: The common-soutce amplifier.Part I, Design and characterization of single-stage amplifiers A. Design of a common-source amplifier 1. According to Fig. 2, please build a common-source amplifier (with no body effect) on your breadboard with the power supply voltage and the gate voltage fixed at 5.0 V and 2.0 V, respectively. Please add a large bias resistor in the range of MO and a coupling capacitor of 0.1 jiF to apply the input signal to the ate, With simple hand calculation, please determine the load resistor (you are allowed to connect the resistors in series or parallel if one proper: it available) necessary to achieve a small-signal gain inthe range between 15 dB to 20 dB at the mid-band (10 kHz}. Please explain your design process. (abv Jene= V7 Avs ont C +L 05.506 Jot bn) Was-Van)?= 28.53 Ry 10.014 Pas Lola oe ye CY gates bese Sur design, measure the drain cuffent [5 (DC), the voltage across drain and source, and the ‘mid-band (for example, at 10 kHz) small-signal gain v/v. Compare the measured data with your analysis in the space provided below. Measured values: Vos™ 12334 Vilo=watta A; Vos= 2080 Vivin= Bic y Wi - Sent Comment: / 2. Perform HSPICE simulation based on the transistor parameters extracted in Lab 6. Compare the measured results with HSPICE simulation, and comment on what you observe Comment: bE fines poromelir Ven = (26030 ine atsad | Age 9.006659, {UR Lebot v ¥ Sanebiten SUED: Ves =20, Nose % PEDAL aaD , YEN. Shet Renee EOE MMOLE Te fol be ARMBAEE To URNS AD ALE zi f f >t 135 -1.566 Ve, ny ena LZ7AEE gon fa EAS 39 12 RE OTT Ko DC cope RAVE HAS du 6 AD Z GREAT SQ. 3. Based on your design, measure the output swing under a few different input signal levels (v)) and record these in the data sheet provided below. What is the maximum linear output swing of your desVa) (a) Ve (0) Were os) Yai te 50 (S44) ona glance ie 150 (158 ae 289 58) Bn ae (su) | 2.44 Maximum output swing: ¥eatanyes = 3.04 4. Plot the load line of your design together withthe simulated /o-Vis curves obtained from Lab 6 (attach the figure below). Is your design optimized for maximum output swing? Please explain. If not, adjust the gate voltage to achieve the maximum output swing under the same load resistor. Also, ‘measure the drain current Jo, the voltage across drain and source, and the mid-band (10 kHz) small-signal szain vv; under the optimized Vs. How does the gain chenge? Give a brief comment. Measured values: Vesiqamay = L8G Vs fo= 2064.4: Vos=_9 £3 Viv = 1.81% Comment: vee KASD BENG. EERE (9 AM RAED ee ID- ves sim) —e=VG5=3 sim) —weves=4 (amy VOS() (oem) emtoudine 5. Add a source degeneration resistor of 1 kQ in the CS amplifier. Note you should use a NMOS transistor (nodes 3-4-5) with the source and body terminals not connected. Node 7 and 14 should be connected to the _most negative voltage and the most positive voltage, respectively. Adjust the gate voltage to achieve the same drain current as in Step |, Measure the mid-band small ynal gain and maximum linear output swing, How does the gain compare to your hand calculation?aags( wa) Cd Ymeare™ 3-168 5 (VV Jee 2.5134; maximum output swing= 2.1) Comment: ; 46 6A Rye t.soain Z norwich BV gon f ia ., Nes Vis Wa -Mle- Wan » Me Tpy ; Naw = 2-206 es Vly 7 S286 A on WY B. Design of a common-drain amplifier (source follower) |. Design the common-drain amplifier with the transistor of nodes 6-7-8 to achieve a small-signal gain larger than 0.8 by selecting Rs, where Rs is connected to the source of the transistor directly (please refer to Fig. 3, but do not connect Re and 0.1 uF for now). Set Vao 5.0 V and Vo= 3.0 V. Please explain your oe NEGEES 5 Mes-Urn, ge (relorordirb,} = 12 Vo.a ARERR » a porod ‘compare that with the value by hand 1. You are required to build a speaker driving circuit using a easeade three-stage common-source amplifier as shown in Fig. 6(b). You will have to use the CD4007UB MOSFET array and the power transistor VN0606 to build the first two stages and the output stage, respectively. The fits two-stage amplifier is shown in Fig. 6(a). Based on the experience obtained in Pat I, please design the bias point of MI through ‘Roy and Rex, and design the load resistors Ro; and Rp2 to have a combined gain of at least $0 (V/V) for the first two stages. Set the power supply voltage to 5.0 V, Perform hand calculation and compare with the ‘measured results. Check if the upper -34B frequency is larger than 20 kHz Gain ofthe first two stages: Measured= 014; caleulated=_6l.2084, re 8GLae Nyvcgmiloys B-030 ANGIE Tet OV ZEB, ‘omy , ant Cee oe Abo = S- TaRy =AU6U = Voor Maar * 34%, KAeot Tay bha'L Wea-Vat's 602A YE, LOO Neo RE, aon ERIE TRAGHS aU «URS OY fy Pears SMA | Raa = 2020 Rot = U2 ovlen. , Ros = 21.891 a es om 4 Nas win 2.0” a Dain #EA°HR Ave, (Noe Tete Wavy eidak ee O™ Roxtne us wel © oe a wole Au Aus = 82004 one Gt = VASA a 2. You are advised to extract the VNO606 transistor model (e.g, threshold voltage) by 1’ measurements a5 performed in Lab 6, in order to design the Tast stage of the speaker driving cireuit as shown in Fig. 6(). “The complete circuit has to achieve a total gun of at least 25. Describe your design process below. Reoune thet (LS Vest Ween Fr Ruse oma * ole 2 ke Manlnc elite Tet : 3 ey UGhes onl WTR ae yale alagge) Bee BAHN otpt a8) TE ay, 2 Daen 2. wa st ye SH amt Ble ta : Res sam 21460. “nt 518 Fo anion, ou veto ty Da PRE 20 (engin) toa Mesto Seton ons en 06 20H Then! oe ss Sl fr Hse PANE BRE 1 aa : aeaiee ca ce " Fig.