Verilog Test Bench

Prepared By:
Jignesh Patoliya,
Sr. Assistant Professor,
EC Deparment, CSPIT,
CHARUSAT, Changa
 Test bench
 A test bench is a program used for exercising
and verifying the correctness of design.

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 Writing test bench
 Purpose:
1. To generate stimulus for simulation(waveforms).
2. To apply this stimulus to the module under test
and collect output responses.
3. To compare output responses with expected
values.

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 Writing test bench[cont’d]
 Format:
module test_bench;
// local reg and net declaration.
//instantiate module under test.
//generate waveform using initial & always
//statement.
//monitor output via $display, $monitor etc.
endmodule

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 Waveform with initial [cont’d]

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 Waveform with initial [cont’d]

Blocking assignment Non blocking assignment

(with relative delays) (with intra-statement delay)

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 Remember
 To repeat a sequence of values, use an always
statement instead of initial statement.
 Note:
always executes repeatedly.
initital executes only once.

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 Waveform with always [cont’d]

Figure :

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 Repetitive pattern
 Format: (This is not completely correct)

assign #(period/2) clock = ~clock

 Problem: If clock is net , only one net can be
assigned in a continous assignment.
Its initial value is an z and ~z is x , and ~x is x.
Therefore clock gets stuck at the value x forever.

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 Repetitive pattern [cont’d]

 Solution: way to initialize the clock

 This can be done using an initial statement.
initial
clock=0;
 Now clock is register data type (since only register
data type can be assigned values in an initial statement)
 Therefore the continuous assignment need to be
changed to an always statement.

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 Repetitive pattern [cont’d]

Complete clock generating

module

Figure

Figure
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 Alternate way of generating a clock

Generating clock with on-off width of 2.
module gen_clk_B(clk_B);
output clk_B;
reg start;
initial
begin
start=1;
#5 start=0;
end
nor #2(clk_B,start,clk_B);
endmodule

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 Clock with different on-off duration

No initialization is necessary

Model using always ststement

figure
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 Clock with start-up delay

To generate a varying on-off

period clock after a start-up
delay, a forever loop in an
initial statement can be used.

figure
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 Phase-delayed clock

module that generate two

clock
one of which is phase-delayed
from the other.

figure
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 System task:display
 The display system task are used for displaying and
printing information.
 These system task are further characterized into:
1. Display and write tasks.
2. Strobed monitoring.
3. Continuous monitoring.

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 System task:display [cont’d]

Format
specification

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 System task:display [cont’d]

 Display taks:
 Print with a end-of line character.
Executed at the time the statement is encountered.
$display
$displayb
$displayh
 $displayo

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 System task:display [cont’d]

 Write task:
Print without a end-of-line character.
Write
writeb
writeh
writeo

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 System task: display [cont’d]

 Strobe task:
Execution of the strobe task is postponed to the
end of the time step, that means all events have
been processed for the specified time step.
$strobe
$strobeb
$strobeh
$strobeo

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 System task: display [cont’d]

Example :
integer cool;
initial
begin
cool=1;
$display(“first assignment, cool %d”, cool);
$strobe(“when strobe is executed , cool %d”,
cool); //value hold at the end of time step.
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 System task-display [cont’d]

cool=2;
$display(“second assignment, cool %d”, cool);
end
Output:
 first assignment, cool 1
 second assignment, cool 2
 when strobe is executed, cool 2 //take updated value
at the end of time step
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 System task-monitor
 Similar in syntax to $display, but does not print
immediately.
 It will print the value whenever the value of some
variable in the given list changes.
 It has the functionality of event-driven print.
$monitor , $monitorb , $monitorh , $monitoro
$monitoron // enable all monitors.
$monitoroff // disable all monitors

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 Value change dump(VCD)
 A VCD file contains information about value changes on
specified variable in design.
 Its main purpose is to provide information for other post-
processing tool.
 $dumpfile(<file name>);
 Specifies the file that will be used for storing the values of
the selected variable so that they can be graphically
visualized later (waveform).
 The file type has an extension .vcd, and contain information
about any value change on the selected variables.
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 Value change dump(VCD) [cont’d]

 $dumpoff;
 This directive stop the dumpling of variables.
 $dumpon;
 This directive start previously stopped dumping of
variables.
 $dumpall;
 The current values of all variables will be written to
the file, irrespective of whether there has been any
changes in their values or not.
 $dumplimit (file size);
 Used to set the maximum size of the .vcd file.
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 Value change dump(VCD) [cont’d]

 dumpvars(level, list of variables OR modules);

Specifies which variables should be dumped to
the .vcd file.
Both the parameters are optional; if both are omitted,
all variables are dumped.
If level=0, then all variables within the modules
from the list will be dumped. if any module from
the list contains module instances, then all variable
from these module will also be dumped.
If level=1, then only listed variables and variables
of listed modules will be dumped.
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 Example 1
 2-bit equality checker :
`timescale 1ns / 100ps
module comparator(x , y , z);
input[1:0] x, y;
output z;
assign z=((x[0] & y[0] & x[1] & y[1] ) |(~x[0] &
~y[0] & x[1] & y[1]) | (~x[0] &~ y[0] & ~x[1] &
~y[1])|(x[0] & y[0] & ~x[1] & ~y[1]));
endmodule

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 Testbench :Example 1
`timescale 1ns / 100ps
module testbench;
reg[1:0] x , y;
wire z;
comparator DUT(.x(x), .y(y), .z(z));
initial
begin
$dumpfile(“comp.vcd”);
$dumpvars(0,testbench);
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 Testbench :Example 1 [cont’d]

x=2’b01; y=2’b10;
#10 x=2’b10; y=2’b10;
#10 x=2’b01; y=2’b11;
end
initial
begin
$monitor(“t=%d”, x=%2b, y=%2b, z=%d”, $time, x, y, z);
end
endmodule
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 Example 2: 3x8 decoder
1. module Decoderr3x8( 14. if(a==3'b011)
2. input [2:0] a, 15. y=8'b00001000;
3. output [7:0] y 16. if(a==3'b100)
4. ); 17. y=8'b00010000;
5. reg [7:0] y; 18. if(a==3'b101)
6. always@(a) 19. y=8'b00100000;
7. begin 20. if(a==3'b110)
8. if(a==3'b000) 21. y=8'b01000000;
9. y=8'b00000001; 22. if(a==3'b111)
10. if(a==3'b001) 23. y=8'b10000000;
11. y=8'b00000010; 24. end
12. if(a==3'b010) 25.endmodule
13. y=8'b00000100;
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 TB:3x8 decoder
1. module tb; 12. // Initialize Inputs
2. // Inputs 13. a =3'b000; #100;
3. reg [2:0] a; 14. a =3'b001; #100;
4. // Outputs 15. a =3'b010; #100;
5. wire [7:0] y; 16. a =3'b011; #100;
6. // Instantiate the Unit Under 17. a =3'b100; #100;
Test (UUT) 18. a =3'b101; #100;
7. Decoderr3x8 uut ( 19. a =3'b110; #100;
8. .a(a), 20. a =3'b111; #100;
9. .y(y) 21. end
10. ); 22.
11.initial
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begin 23.endmodule
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 Example 3: mux 4x1
1. module testbench;
2. reg [1:0] Select;
3. wire OUT;
4. integer i,j;
5. MUX_4x1 DUT (.I(INPUT), .Sel(Select), .MUX_Out(OUT));
6. initial
7. begin
8. for (i=0;i<16;i=i+1)
9. begin
10. for (j=0;j<4;j=j+1)
11. begin
12. {INPUT[0], INPUT[1], INPUT[2], INPUT[3]} = i;
13. {Select[0], Select[1]} = j;
14. #1;
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 Example 3: mux 4x1 [cont’d]

14. end
15. end
16. #5 $finish;
17. end
18. initial
19. begin
20. $dumpfile("df_4x1_mux_3.vcd");
21. $dumpvars;
22. end

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 Example 3: mux 4x1 [cont’d]

22. always @(INPUT, Select)

23. begin
24. $monitor ("Time: %d, I0: %b, I1: %b, I2: %b, I3: %b, Select[0]: %b,
Select[1]: %b, Output: %b",$time, INPUT[0], INPUT[1], INPUT[2],
INPUT[3], Select[0], Select[1], OUT);
25. end

26. endmodule

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 References
 Verilog HDL: A Guide to digital Design and
Synthesis, by Samir Palnitkar, Prentice Hall PTR
 A verilog HDL Primer by J.Bhasker, Star galaxy
publishing.
 Verilog HDL:Digital Design & Modeling by Joseph
Cavanagh, CRC press, Taylor & Francis Group

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03/17/2023 Verilog Introduction 37
 [email protected]

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