First Lecture

Integrated 21\22

Semiconductors

Insulators, Conductors, and Semiconductors:

All materials are made up of atoms. These atoms contribute to the electrical
properties of a material, including its ability to conduct electrical current. For
purposes of discussing electrical properties, an atom can be represented by the
valence shell and a core that consists of all the inner shells and the nucleus. This
concept is illustrated in Fig. 1 for a carbon atom.

Fig. 1

Carbon is used in some types of electrical resistors. Notice that the carbon atom
has four electrons in the valence shell and two electrons in the inner shell. The
nucleus consists of six protons and six neutrons, so the +6 indicates the positive
charge of the six protons. The core has a net charge of +4 (+6 for the nucleus and -
2 for the two inner-shell electrons).

Insulators:
An insulator is a material that does not conduct electrical current under normal
conditions. Most good insulators are compounds rather than single-element
materials and have very high resistivity. Valence electrons are tightly bound to the
atoms; therefore, there are very few free electrons in an insulator. Examples of
insulators are rubber, plastics, glass, mica, and quartz.

Conductors:
A conductor is a material that easily conducts electrical current. Most metals are
good conductors. The best conductors are single-element materials, such as copper
(Cu), silver (Ag), gold (Au), and aluminum (Al), which are characterized by atoms
with only one valence electron very loosely bound to the atom. These loosely
bound valence electrons can become free electrons with the addition of a small
amount of energy to free them from the atom. Therefore, in a conductive material
the free electrons are available to carry current.

Semiconductors:
A semiconductor is a material that is between conductors and insulators in its
ability to conduct electrical current. A semiconductor in its pure (intrinsic) state is
neither a good conductor nor a good insulator. Single-element semiconductors are
antimony (Sb), arsenic (As), astatine (At), polonium (Po), tellurium (Te), silicon
(Si), and germanium (Ge). Compound semiconductors such as gallium arsenide,
indium phosphide, gallium nitride, silicon carbide, and silicon germanium are also
commonly used. The single-element semiconductors are characterized by atoms
with four valence electrons. Silicon is the most commonly used semiconductor.

Band Gap:
In solid materials, interactions between atoms “smear” the valence shell into a
band of energy levels called the valence band. Valence electrons are confined to
that band. When an electron acquires enough additional energy, it can leave the
valence shell, become a free electron, and exist in what is known as the conduction
band. The difference in energy between the valence band and the conduction band
is called an energy gap or band gap. This is the amount of energy that a valence
electron must have in order to jump from the valence band to the conduction band.
Once in the conduction band, the electron is free to move throughout the material
and is not tied to any given atom. Fig. 2 shows energy diagrams for insulators,
semiconductors, and conductors. The energy gap or band gap is the difference
between two energy levels and electrons are “not allowed” in this energy gap based
on quantum theory. Although an electron may not exist in this region, it can
“jump” across it under certain conditions. For insulators, the gap can be crossed
only when breakdown conditions occur, as when a very high voltage is applied
across the material. The band gap is illustrated in Fig. 2.a. for insulators. In
semiconductors the band gap is smaller, allowing an electron in the valence band
to jump into the conduction band if it absorbs a photon. The band gap depends on
the semiconductor material. This is illustrated in Fig. 2.b. In conductors, the
conduction band and valence band overlap, so there is no gap, as shown in Fig. 2.c.
This means that electrons in the valence band move freely into the conduction
band, so there are always electrons available as free electrons.
Fig. 2

Silicon and Germanium:

The atomic structures of silicon and germanium are compared in Fig. 3. Silicon is
used in diodes, transistors, integrated circuits, and other semiconductor devices.
Notice that both silicon and germanium have the characteristic four valence
electrons.

Fig. 3

The valence electrons in germanium are in the fourth shell while those in silicon
are in the third shell, closer to the nucleus. This means that the germanium valence
electrons are at higher energy levels than those in silicon and, therefore, require a
smaller amount of additional energy to escape from the atom. This property makes
germanium more unstable at high temperatures and results in excessive reverse
current. This is why silicon is a more widely used semiconductive material.

Covalent Bonds:
Fig.4.a shows how each silicon atom positions itself with four adjacent silicon
atoms to form a silicon crystal, which is a three-dimensional symmetrical
arrangement of atoms. A silicon (Si) atom with its four valence electrons shares an
electron with each of its four neighbors. This effectively creates eight shared
valence electrons for each atom and produces a state of chemical stability. Also,
this sharing of valence electrons produces a strong covalent bond that holds the
atoms together; each valence electron is attracted equally by the two adjacent
atoms which share it. Covalent bonding in an intrinsic silicon crystal is shown in
Fig 4.b. An intrinsic crystal is one that has no impurities. Covalent bonding for
germanium is similar because it also has four valence electrons.

Fig.4

Current in Semiconductors:
The way a material conducts electrical current is important in understanding how
electronic devices operate. You can’t really understand the operation of a device
such as a diode or transistor without knowing something about current in
semiconductors.
As you have learned, the electrons in a solid can exist only within prescribed
energy bands. Each shell corresponds to a certain energy band and is separated
from adjacent shells by band gaps, in which no electrons can exist. Fig. 5 shows
the energy band diagram for the atoms in a pure silicon crystal at its lowest energy
level. There are no electrons shown in the conduction band, a condition that occurs
only at a temperature of absolute 0 Kelvin.

Fig.5

Conduction Electrons and Holes:

An intrinsic (pure) silicon crystal at room temperature has sufficient heat (thermal)
energy for some valence electrons to jump the gap from the valence band into the
conduction band, becoming free electrons. Free electrons are also called
conduction electrons. This is illustrated in the energy diagram of Fig. 6.a and in the
bonding diagram of Fig. 6.b.
Fig.6

When an electron jumps to the conduction band, a vacancy is left in the valence
band within the crystal. This vacancy is called a hole. For every electron raised to
the conduction band by external energy, there is one hole left in the valence band,
creating what is called an electron-hole pair. Recombination occurs when a
conduction-band electron loses energy and falls back into a hole in the valence
band. To summarize, a piece of intrinsic silicon at room temperature has, at any
instant, a number of conduction-band (free) electrons that are unattached to any
atom and are essentially drifting randomly throughout the material. There also an
equal number of holes in the valence band created when these electrons jump into
the conduction band.

N-type And P-type Semiconductors

Semiconductive materials do not conduct current well and are of limited value in
their intrinsic state. This is because of the limited number of free electrons in the
conduction band and holes in the valence band. Intrinsic silicon (or germanium)
must be modified by increasing the number of free electrons or holes to increase its
conductivity and make it useful in electronic devices. This is done by adding
impurities to the intrinsic material. Two types of extrinsic (impure) semiconductive
materials, n-type and p-type are the key building blocks for most types of
electronic devices.
Since semiconductors are generally poor conductors, their conductivity can be
drastically increased by the controlled addition of impurities to the intrinsic (pure)
semiconductive material. This process, called doping, increases the number of
current carriers (electrons or holes). The two categories of impurities are n-type
and p-type.
N-Type Semiconductor:
To increase the number of conduction-band electrons in intrinsic silicon,
pentavalent impurity atoms are added. These are atoms with five valence electrons
such as arsenic (As), phosphorus (P), bismuth (Bi), and antimony (Sb).
As illustrated in fig. 7, each pentavalent atom (antimony, in this case) forms
covalent bonds with four adjacent silicon atoms. Four of the antimony atom’s
valence electrons are used to form the covalent bonds with silicon atoms, leaving
one extra electron. This extra electron becomes a conduction electron because it is
not involved in bonding. Because the pentavalent atom gives up an electron, it is
often called a donor atom. The number of conduction electrons can be carefully
controlled by the number of impurity atoms added to the silicon. A conduction
electron created by this doping process does not leave a hole in the valence band
because it is in excess of the number required to fill the valence band.

Fig. 7

Majority and Minority Carriers:

Since most of the current carriers are electrons, silicon (or germanium) doped with
pentavalent atoms is an n-type semiconductor (the n stands for the negative charge
on an electron). The electrons are called the majority carriers in n-type material.
Although the majority of current carriers in n-type material are electrons, there are
also a few holes that are created when electron-hole pairs are thermally generated.
These holes are not produced by the addition of the pentavalent impurity atoms.
Holes in an n-type material are called minority carriers.
P-Type Semiconductor:
To increase the number of holes in intrinsic silicon, trivalent impurity atoms are
added. These are atoms with three valence electrons such as boron (B), indium
(In), and gallium (Ga). As illustrated in fig. 8, each trivalent atom (boron, in this
case) forms covalent bonds with four adjacent silicon atoms. All three of the boron
atom’s valence electrons are used in the covalent bonds; and, since four electrons
are required, a hole results when each trivalent atom is added. Because the trivalent
atom can take an electron, it is often referred to as an acceptor atom. The number
of holes can be carefully controlled by the number of trivalent impurity atoms
added to the silicon. A hole created by this doping process is not accompanied by a
conduction (free) electron.

Fig. 8

Majority and Minority Carriers:

Since most of the current carriers are holes, silicon (or germanium) doped with
trivalent atoms is called a p-type semiconductor. The holes are the majority carriers
in p-type material. Although the majority of current carriers in p-type material are
holes, there are also a few conduction-band electrons that are created when
electron-hole pairs are thermally generated. These conduction-band electrons are
not produced by the addition of the trivalent impurity atoms. Conduction-band
electrons in p-type material are the minority carriers.
 Second Lecture
2021 - 2022
Silicon wafer manufacturing
(Silicon Processing)

Introduction
The first step in integrated circuit (IC) fabrication is preparing the high purity
single crystal Si wafer. This is the starting input. Typically, Si wafer refers to a
single crystal of Si with a specific orientation, dopant type, and resistivity. The
wafer should have structural defects, like dislocations, below a certain permissible
level and impurity (undesired) concentration of the order of ppb (parts per billion).
Consider the specs (specifications) of a 300 mm wafer shown in table 1 below. The
thickness of the wafer is less than 1 mm, while its diameter is 300 mm. Also, the
wafers must have a plane parallel to the surface, to within 2◦ deviation, and typical
impurity levels should be of the order of ppm or less with metallic impurities of the
order of ppb. For doped wafers, there should be specific amounts of the desired
dopants (p type or n type) to get the required resistivity.

Table 1: Specs of a typical 300 mm wafer to be used in fabrication. The

specifications include the dimensions, orientation, resistivity, and oxygen and
carbon impurity content.

Table 2: Impurities in MGS

Polycrystalline Si manufacture
The starting material for Si wafer manufacture is called Electronic grade Si (EGS).
This is an ingot of Si that can be shaped and cut into the final wafers. EGS should
have impurity levels of the order of ppb, with the desired doping levels, so that it
matches the chemical composition of the final Si wafers. The doping levels are
usually back calculated from resistivity measurements. The starting material for Si
manufacture is quartzite (sandstone has been exposed to high temperatures and
pressures) or sand (SiO2).

SiO2 is mixed with coke and heated. It first forms SiC, which further reacts with
the remaining SiO2 forming silicon.

Silicon dioxide reacts with carbon upon heating to produce silicon carbide (SiC)
and carbon monoxide.

( ) ( ) ( ) ( ) (1)

( ) ( ) () ( ) ( ) (2)

The temperature is maintained above the melting point of silicon so that the molten
semiconductor is removed from the bottom. This is the MGS and is around 98%
pure.

Further purification is needed to make EGS since the impurity concentration must
be reduced to ppb levels. Si is reacted with HCl gas to form tricholorosilane, which
is in gaseous form.

( ) ( ) ( ) ( ) (3)

This process is carried out in a fluidized bed reactor at 300◦C, where the
trichlorosilane gas is removed and then reduced using H2 gas.

( ) ( ) ( ) ( ) (4)

The process flow is shown in Fig. 1. During the conversion of silicon to

trichlorosilane impurities are removed and process can be cycled to increase purity
of the formed Si. The final material obtained is the EGS. This is a polycrystalline
form of Si, like MGS, but has much smaller impurity levels, closer to what is
desired in the final single crystal wafer. The impurities in EGS are tabulated in
table 3. EGS is still polycrystalline and needs to be converted into a single crystal
Si ingot for producing the wafers.

Fig. 1: Schematic of the process to purify MGS and change it to EGS. The process
involves conversion of silicon to trichlorosilane gas, which is purified, and then
reduced to obtain silicon.

Table 3 Impurities in EGS after purification from MGS. Compared to table 2, the
concentration levels of metals have dropped to ppb levels.

Single Crystal Si Manufacture

There are two main techniques for converting polycrystalline EGS into a single
crystal ingot, which are used to obtain the final wafers.
Czochralski technique (CZ) - this is the dominant technique for manufacturing
single crystals. It is especially suited for the large wafers that are currently used in
IC fabrication.
Float zone technique - this is mainly used for small sized wafers. The float zone
technique is used for producing specialty wafers that have low oxygen impurity
concentration.

Czochralski crystal growth technique

A schematic of this growth process is shown in fig. 2. The various components of
the process are
1. Furnace
2. Crystal pulling mechanism
3. Ambient control - atmosphere
4. Control system
The starting material for the CZ process is electronic grade silicon, which is melted
in the furnace. To minimize contamination, the crucible is made of SiO2 or SiNx.
The drawback is that at the high temperature the inner liner of the crucible also
starts melting and has to be replaced periodically.

Fig. 2: Schematic of the Czochralski growth technique. The polycrystalline silicon

is melted and a single crystal seed is then used to nucleate a single crystal ingot.
The seed crystal controls the orientation of the single crystal.

Fig. 3: Single crystal Si ingot. This is further processed to get the wafers that are
used for fabrication.

The furnace is heated above 1500 ◦C, since Si melting point is 1412 ◦C. A small
seed crystal, with the desired orientation of the final wafer, is dipped in the molten
Si and slowly withdrawn by the crystal pulling mechanism. The seed crystal is also
rotated while it is being pulled, to ensure uniformity across the surface. The
furnace is rotated in the direction opposite to the crystal puller. The molten Si
sticks to the seed crystal and starts to solidify with the same orientation as the seed
crystal is withdrawn. Thus, a single crystal ingot is obtained. To create doped
crystals, the dopant material is added to the Si melt so that it can be incorporated in
the growing crystal. The process control, i.e. speed of withdrawal and the speed of
rotation of the crystal puller, is crucial to obtain a good quality single crystal.
There is a feedback system that controls this process. Similarly there is another
ambient gas control system. The final solidified Si obtained is the single crystal
ingot. A 450 mm wafer ingot can be as heavy as 800 kg. A picture of a such an
ingot is show in fig. 3.

Float zone technique

The float zone technique is suited for small wafer production, with low oxygen
impurity. The schematic of the process is shown in Fig. 4. A polycrystalline EGS
rod is fused with the single crystal seed of desired orientation. This is taken in an
inert gas furnace and then melted along the length of the rod by a traveling radio
frequency (RF) coil. The RF coil starts from the fused region, containing the seed,
and travels up, as shown in Fig. 4. When the molten region has been solidified, it
has the same orientation as the seed. The furnace is filled with an inert gas like
argon to reduce gaseous impurities.
 Fig. 4: Schematic of the float zone technique. The polycrystalline ingot is fused
with a seed crystal and locally melted by a traveling radio frequency coil. As the
ingot melts and re-solidifies it has the same orientation as the seed.

Also, since no crucible is needed it can be used to produce oxygen ’free’ Si wafers.
The difficulty is to extend this technique for large wafers, since the process
produces large number of dislocations. It is used for small specialty applications
requiring low oxygen content wafers.

Wafer manufacturing
After the single crystal is obtained, this needs to be further processed to produce
the wafers. For this, the wafers need to be shaped and cut. Usually, industrial grade
diamond tipped saws are used for this process. The shaping operations consist of
two steps
1. The seed and tang ends of the ingot are removed.
2. The surface of the ingot is ground to get a uniform diameter across the length of
the ingot.
Before further processing, the ingots are checked for resistivity and orientation.
Resistivity is checked by a four point probe technique and can be used to confirm
the dopant concentration. This is usually done along the length of the ingot to
ensure uniformity. Orientation is measured by x-ray diffraction at the ends (after
grinding). After the orientation and resistivity checks, one or more flats are ground
along the length of the ingot.
 Third lecture
2021 - 2022
Wafer Preparation
The ends of the boule are cut off.
 Cylindrical grinding ‫ تجليخ اسطىاوى‬is used to shape the boule ‫كتلخ السيليكىن الىبتجخ‬
into a more perfect cylinder
 One or more flats ‫ شطفخ‬are ground along the length of the boule, whose
functions, after the boule is cut into wafers, are the following:
 Identification
 Orientation of ICs relative to crystal structure
 Mechanical location during processing

Figure 1 - Grinding operations used in shaping the silicon ingot: (a) a form of
cylindrical grinding provides diameter and roundness control, and (b) a flat ground
on the cylinder

Wafer Slicing
 A very thin ring-shaped saw ‫ مىشبس على هيئخ حلقخ‬blade with diamond grit
bonded to internal diameter is the cutting edge
 The ID is used for slicing rather than the OD for better control over flatness,
thickness, parallelism, and surface characteristics of the wafer
 Wafers are cut
 0.5-0.7 mm thick, greater thicknesses for larger wafer diameters.
 To minimize kerf loss ‫مب يستهلك عىذ القطع‬, blades are made very thin: about
0.33 mm.
 Figure 2 Wafer slicing using a diamond abrasive cut-off saw
Wafer Preparation

 Wafer rims are rounded by contour-grinding wheel to reduce chipping

during handling.
 Wafers are chemically etched to remove surface damage from slicing.
 A flat polishing operation is performed to provide surfaces of high
smoothness for photolithography ‫ التصىيش الضىئى‬processes to follow.
 Finally, the wafer is chemically cleaned to remove residues ‫ مخلفبد‬/ ‫ ثىاقى‬and
organic films.

Lithography
 An IC consists of many microscopic regions on the wafer surface that make
up the devices and interconnections as specified in the circuit design.
 In the planar process, the regions are fabricated by steps that add, alter, or
remove layers in selected areas of the wafer surface.
 Each layer is determined by a geometric pattern representing circuit design
information that is transferred to the wafer surface by lithography ‫الطجبعخ على‬
‫الحجش‬.

Lithographic Technologies
 Several lithographic technologies are used in semiconductor processing:
 Photolithography
 Electron lithography
 X-ray lithography
 Ion lithography.
 The differences are in type of radiation used to transfer the mask pattern to
the wafer surface.
Photolithography
 Uses light radiation to expose a coating of photoresist ‫ مبدح مقبومخ للضىء‬on the
surface of the wafer.
 Common light source in wafer processing is ultraviolet light, due to its
short wavelength.
 A mask containing the required geometric pattern for each layer separates
the light source from the wafer, so that only the portions of the photoresist
not blocked by the mask are exposed ‫معشضخ للضىء‬.

The Mask in Photolithography

Flat plate of transparent glass onto which a thin film of an opaque ‫ معتمخ‬substance
has been deposited in certain areas to form the desired pattern
 Thickness of glass plate is around 2 mm, while deposited film is only a few
µm thick - for some film materials, less than one µm.
 The mask itself is fabricated by lithography, the pattern being based on
circuit design data, usually the output from the CAD system used by circuit
designer.

Photoresist
Photoresist is an organic polymer that is sensitive to light radiation in a certain
wavelength range.
 The sensitivity causes either an increase or decrease in solubility )‫ (روثبن‬of
the polymer to certain chemicals.
 Typical practice in semiconductor processing is to use photoresists that are
sensitive to ultraviolet light.
 UV light has a short wavelength compared to visible light, permitting
sharper imaging of microscopic circuit details on the wafer surface
 Also permits fabrication areas in plant to be illuminated at low light levels
outside UV band.

Contact Printing
Mask is pressed against resist coating during exposure
•Advantage: high resolution of the pattern onto wafer surface
•Disadvantage: physical contact with wafers gradually wears out mask
The following figure; Photolithography exposure techniques: (a) contact printing
 Figure 3 Photolithography exposure techniques: (a) contact printing

Proximity Printing
Mask is separated from the resist coating by a distance of 10-25 µm.
Eliminates mask wear, but image resolution is slightly reduced

Figure 4 Photolithography exposure techniques: (b) proximity ‫ قشة‬printing

Projection Printing
High-quality lens system projects image through mask onto wafer
 Preferred technique because non-contact (thus, no mask wear), and optical
projection ‫ اسقبط‬can obtain high resolution.

Figure 5 Photolithography exposure techniques: (c) projection printing.

Processing Sequence in Photolithography

 Surface of the silicon wafer has been oxidized to form a thin film of SiO2
 It is desired to remove the SiO2 film in certain regions as defined by mask
pattern
 Sequence for a negative resist proceeds as follows:
1. The wafer is properly cleaned to promote wetting and adhesion of resist

Figure 6.1 Photolithography process applied to a silicon wafer: (1) prepare surface

2. A metered amount of liquid resist is fed onto center of wafer and wafer is
spun ‫ داسد‬to spread liquid and achieve uniform coating thickness
 Figure 6.2 apply photoresist

3. Soft bake - purpose is to remove solvents ‫المزيجبد‬, promote adhesion,

and harden resist
• Temperature ~ 90 (190 ) for 10-20 minutes

Figure 6.3 soft-bake

4. Pattern mask is aligned relative to wafer and resist is exposed through mask

Figure 6.4 align mask and expose

5. Exposed wafer is immersed in developing solution, or solution is sprayed onto

surface
• For negative resist, unexposed areas are dissolved ‫تحل أو تزاة‬, thus leaving SiO2
surface uncovered in these areas
 Figure 6.5 develop ‫ يكشف عه أو يزيت‬resist

6. Hard bake to expel volatiles ‫ طشد المىاد المتطبسح‬remaining from developing

solution and increases adhesion of resist especially at newly created edges of resist
film.

Figure 6.6 hard-bake

7. Etching removes SiO2 layer at selected regions where resist has been removed

Figure 6.7 etch

8. Resist coating remaining on surface is removed

• Stripping is accomplished using either liquid chemicals or plasma etching

Figure 6.8 strip resist

Other Lithography Techniques
As feature size in integrated circuits continues to decrease and UV
photolithography becomes increasingly inadequate, other lithography techniques
that offer higher resolution are growing in importance:
 Extreme ultraviolet (EUV) lithography
 Electron beam lithography
 X-ray lithography
 Ion lithography
 Fourth lecture
2021 - 2022
Basic IC Processing
Simple Mask Set (Example).
Shown below is a highly simplified layout for a two transistor digital gate, and the
masks which would be required based on its layout.

Etching -Dry and Wet Processes:

 Etching is the selective removal of material from the chip surface.

 In dry etching, ions of a neutral material are accelerated toward the surface and
cause ejection of atoms of all materials.
 In wet etching, a chemical etchant is used to remove material via a chemical
reaction.

Etching -Selectivity and Anisotropy ‫تبايه خواص‬

Two most important issues in etching are selectivity and anisotropy
– Selectivity refers to the ability of an etchant to remove one material on the
surface while leaving another intact.
– Isotropic refers to the tendency of the etching to proceed laterally as well as
downward
Thermal Oxidation -Oxidation Furnace
 One of the simplest steps in IC processing is thermal oxidation, the growth of a
layer of silicon dioxide (SiO2) on the substrate surface.
 Requires only substrate heating to 900-1200 °C in a dry (O2) or wet (H20
steam) ambient using an oxidation furnace.
 Silicon oxidizes quite readily -one reason why Si is so widely used.

Thermal Oxidation -Oxide Formation:

 Oxide is formed due to the chemical reaction between oxygen in the ambient
and silicon in the substrate.
 Substrate silicon is consumed during the reaction, so oxide layer grows in both
directions from the original substrate surface (approx. 50/50).
Thermal Oxidation -Wet vs. Dry Rates
 Due to the different reaction mechanisms, oxidation in a wet ambient is many
times faster than oxidation in a dry ambient.
 However, the oxide quality is much better when a dry ambient is used.
 Thick isolation layers are therefore formed using wet oxidation, while
MOSFET gate oxides are formed with dry oxidation.

Local Oxidation
 The presence of another material such as silicon nitride (Si3N4) on the surface
inhibits ‫ يمنع‬the growth of oxide in that region.
 This allows selective or local oxidation of the substrate surface -will be used to
isolate devices or conductive layers.
 Some oxidation does occur laterally under the nitride layer, giving rise to the
bird’s beak effect.
Dopant Diffusion
 Dopant can be introduced into the substrate through diffusion.
 Diffusion is a general physical process which drives particles down a
concentration gradient.
 The substrate is heated in the presence of dopant atoms, which then diffuse into
the substrate.
 Diffusion may also occur into other layers which are present such as silicon
dioxide.
 Large amount of lateral diffusion also occurs.

Ion Implantation
In ion implantation, dopant atoms are accelerated toward the substrate surface and
enter due to their kinetic energy.
This is the preferred technique for introduction of dopant atoms since the amount
of lateral diffusion is much lower.
Ion Implantation System

Ion Implantation – Predep and Drive-in

Ion implantation can be used to form a deep region of doping using a two step
procedure:
 A high concentration of dopant is deposited near the surface in the pre-
deposition or predep stage.
 The dopant source is then removed and the wafer heated to cause redistribution
of the dopant via diffusion in the drive-in stage.

Deposition:
 Layers of materials such as metal (and in some cases silicon dioxide) may need
to be formed on the surface.
 General procedure of forming a layer of material on the surface is termed
deposition.
 Two types can be identified, physical and chemical:
– In physical deposition, a piece (target) of the material to be deposited is
bombarded with ions, ejecting atoms of material which then adhere to the
substrate surface.
– Chemical deposition uses an ongoing chemical reaction to form the desired
material as a precipitate on the substrate surface.
 A specialized form of deposition is epitaxy, the formation of a layer of
crystalline semiconductor material.
Patterning
 The use of a series of PR deposition, exposure, development and etching to
create regions of particular shape is called patterning.
 For example, if a newly deposited metal layer was coated with PR, exposed
using a mask, developed and etched using a method which selectively removed
the metal not covered by the PR, this would be referred to as “patterning” the
metal.
 There will be many individual patterning steps in the creation of a useful
integrated structure.

Scribing and Cleaving

Scribing:‫الخطوط األفقية والرأسية‬
Cleaving: ‫كسر رقاقة السيليكون‬
After processing is finished, the wafers are separated into individual dice by
scribing and cleaving.
– Scribing refers to creating a groove along scribe channels which have
been left
between the rows and columns of individual chips (during mask generation).
– Cleaving is the process of breaking the wafer apart into individual dice.
 Fifth Lecture
2021 – 2022
Planar Diode Fabrication

Lecture Outline:
 Last lecture described a number of processing techniques used to fabricate
integrated circuits.
 This lecture will show how those techniques are used together, some many
times, in fabricating three integrated diode structures.
 As more complex structures are considered, the level of detail in the
descriptions will be reduced.

Diode Types Considered:

Fabrication of three types of diodes examined:
 Substrate Diode: simple pn-junction fabricated from a single counter-doped
region in the substrate.
 Well Diode: slightly more complicated structure with a deeper region of counter
doping and a highly doped diffusion.
 Epitaxial Diode: More complicated processing using an epitaxial ‫ طبقة فوقية‬layer,
but offers the best performance.

Substrate Diode -Nitride Protection

 First step is to deposit a layer of silicon nitride over the wafer surface.
 It normally be done using chemical vapor deposition (CVD).

Substrate Diode –Photoresist Coating:

Surface (top of nitride layer) then coated with photoresist (PR).
Substrate Diode –Exposure:
Surface of PR is then exposed to UV radiation through a mask created from
geometry information supplied by the designer.

Substrate Diode -Development of Photoresist

Photoresists then developed chemically
A negative photoresist remains where it was exposed to UV

Substrate Diode -Etching of Nitride

The nitride layer is then etched chemically
Only the nitride areas where photoresist was removed will be etched

Substrate Diode -Finished Nitride Etch

When the nitride etching is complete, nitride layer outside the remaining area of
photoresist has been remove.
Both nitride and photoresist remain in the exposed area.
Substrate Diode –Photoresist Removal:
The photoresist still covering the remaining nitride area is now removed

Substrate Diode -Thermal Oxidation

A layer of silicon dioxide is grown using thermal oxidation.
The oxide is prevented from growing in the area covered by silicon nitride -this is
the purpose of the nitride layer.

Substrate Diode -Nitride Removal

When oxidation is complete, the nitride layer is removed.
The result is a structure with thick isolation oxide everywhere except the areas
which will become the active diode.

Substrate Diode -Implantation

An implantation (ion implantation or diffusion) is now done to create a counter-
doped region which will form one side of the pn-junction.
The oxide absorbs the dopant outside of the active area, preventing dopant from
penetrating into the substrate anywhere but the active area.
Substrate Diode -Surface Metal Patterning
Metal is now deposited over the entire wafer surface.
Another series of patterning steps is used, along with another mask, to remove
metal everywhere except the contact to the diode and wherever else the connection
is made.

Substrate Diode -Substrate Connection

Metal is deposited on the backside of the wafer to form the other connection.
Note that all substrate diodes share a common (substrate) connection.

Well Diode
Two problems with the substrate diode:
– Current flows through the entire thickness of the substrate (500 1000 μm) to
reach the back contact.
– Substrate is common for all diodes on the chip ∴diodes all have a common
connection.
Better solution is to use a well diode, which is formed in a region of opposite
doping (counter-doped) to the substrate, and a heavily doped region of the same
type as the substrate.
Eliminates long current path through the substrate, and allows two independent
terminals, since well is isolated from the substrate.
Well Diode -Nitride Deposition, Thermal Oxidation
A layer of nitride is deposited and patterned so that it exists on where the active
area (including the well) is to be formed.
Thermal oxidation used to form an oxide layer.

Well Diode -Well implant

A deep implantation is done to create the well-a counter-doped region which will
be one side of the diode.

Well Diode -Well Contact Implant

To connect to the well, a highly doped region of the same type as the well is
created.
All the usual patterning steps are used (PR deposition, exposure with mask,
development, removal of PR).

Well Diode -Diode Diffusion

The other side of the pn-junction structure is formed with a heavy implant into the
well

Well Diode -Isolation Oxide

A layer of silicon dioxide is deposited on the surface (thermal oxidation would
grow into the existing diffusion structure).
This layer is required because the two contacts to the diode are both at the surface
hence an isolation layer is required to prevent shorting.
Well Diode -Contact Cuts and Metallization
Contact cuts are etched through the isolation oxide to the diffusions using a full
series of patterning steps.
Metal is deposited on the surface and patterned for interconnections.
Provided the well to substrate junction is reverse biased, the well diode is isolated
from the substrate, and hence from other devices.

Epitaxial Diode
Well diode is an improvement over the substrate diode, but current flow is lateral
so the exact performance is hard to predict.
Best solution, but with corresponding process complexity, is the epitaxial diode,
fabricated on an epitaxial layer of silicon.

Epitaxial Diode -Thermal Oxidation

Starting material is lightly doped substrate assume p-for this example.
Layer of oxide grown using thermal oxidation step.

Epitaxial Diode -Buried Layer Formation

Using a photolithography step (and an associated mask) a window is formed in the
oxide and a heavy n-type implant performed to create a highly doped n-type (n+)
region called the buried layer.
The oxide is then removed using a selective etching step.
The result is a heavy n+ doping which will form the back connection to the diode.
Epitaxial Diode –Epitaxial Deposition
The next step is to use epitaxy to deposit a layer of high quality crystalline silicon
called the epilayeron the wafer surface.
Some diffusion of dopant from the n+ region occurs into the epilayer.
Another series of photolithography steps is used to form a masking oxide over the
region which will become the active diode area.

Epitaxial Diode -Isolation Implants

A heavy p-type (p+) implant is then used to form regions extending right through
the epi and into the substrate (lateral diffusion also results in extension under
masking oxide).
These isolation regions electrically isolate the device from all others fabricated in
the epi layer.

Epitaxial Diode n+ and p+ Implants

Oxide is deposited and patterned to open a window for an n+ doping which will
form a contact through the n-type epi layer down to the buried layer.
Oxide is again deposited and patterned to produce an opening for a heavy p-type
implant which will form the other side of the pn-junction with the epi layer.
Epi Diode -Metallization
Another layer of oxide is deposited to isolate the metal connections from the epi
and isolation p+ implants.
Openings are patterned to allow contact to the p+ diode diffusion and the n+ epi
contact diffusion.
Metal is deposited and patterned to form connections to the diode.

Epitaxial Diode -Current Flow

The active diode area is only a small portion of the epitaxial structure.
Current flow in the epi diode is through the active area, along the buried layer and
up and out the n+ contact diffusion.
Benefit is well controlled current flow path.
Also forms a major portion of the structure of an integrated BJT.

Summary of Diode Structures

Three diode structures examined
– Substrate: simple, but poor performance
– Well: better, and getting more complicated
– Epi: best, but most complicated
Lecture Summary
The use of the basic processing techniques from lecture 4 in creating three diode
structures was discussed.
Note that many of the techniques are performed over and over as successive
features are created.
The substrate diode is simple but suffers from at least one disadvantage –all
substrate diodes have one terminal connected together.
The well diode is an improvement, but has primarily lateral flow, which can be
difficult to characterize.
The epi diode gives the best performance, but is much more complex to fabricate
than the first two.
 Sixth Lecture
2021 – 2022
Integrated Circuit Devices and Modeling

Intrinsic silicon (i.e., undoped silicon) is a very pure crystal structure that has equal
numbers of free electrons and holes. These free carriers are those electrons that
have gained enough energy due to thermal agitation to escape their bonds, and the
resulting holes that they leave behind. At room temperature, there are
approximately carriers of each type per or equivalently
⁄ , defined as the carrier concentration of intrinsic
silicon. The number of carriers approximately doubles for every 11 °C increase in
temperature.
If one dopes silicon with a pentavalent impurity (i.e., atoms of an element having a
valence of five, or equivalently five electrons in the outer shell, available when
bonding with neighboring atoms), there will be almost one extra free electron for
every impurity atom. These free electrons can be used to conduct current. A
pentavalent impurity is said to donate ‫ يتبرع – يمنح‬free electrons to the silicon
crystal, and thus the impurity is known as a donor. Examples of donor elements are
phosphorus P, and arsenic As. These impurities are also called n-type dopants
‫ شوائب‬since the free carriers resulting from their use have negative charge. When an
n-type impurity is used, the total number of negative carriers or electrons is almost
the same as the doping concentration, and is much greater than the number of free
electrons in intrinsic silicon. In other words,

Where, denotes the free-electron concentration in n-type material and is the

doping concentration (with the subscript D denoting donor). On the other hand, the
number of free holes in n-doped material will be much less than the number of
holes in intrinsic silicon and can be given by;

Similarly, if one dopes silicon with atoms that have a valence of three, for
example, boron (B), the concentration of positive carriers or holes will be
approximately equal to the acceptor concentration,

And the number of negative carriers in the p-type silicon, , is given by

Problem 1
Intrinsic silicon is doped with boron at a concentration of ⁄ . At
room temperature, what are the concentrations of holes and electrons in the
resulting doped silicon? Assume that ⁄

Solution;
The hole concentration will approximately equals the doping concentration;
.
The electron concentration is found from
( )
= electrons/

Such doped silicon is referred to as p-type since it has many more free holes than
free electrons.

Superscripts are used to indicate the relative doping levels. For example, the
bulk region might have an impurity concentration of ⁄ ,
whereas the regions would be doped more heavily to a value around

( )
Built-in voltage of an open-circuit pn junction
 is the temperature in degree Kelven ( 300 at room temperature).
K is Boltzmann’s constant ,
is the charge of an electron .
At room temperature, is approximately is approximately 26 mv.

Problem 2:
A pn junction has and . What is the
built-in junction potential? Assume that .

Solution:
( )

( )
( )

This is a typical value for the built-in potential of a junction with one side heavily
doped. As an approximation, we will normally use for the built-in
potential of a junction having one side heavily doped.

⁄
( )
* +
( )

⁄
( )
* +
( )

: depletion width
applied reverse voltage
is the permittivity of free space (equals to
is the relative permittivity of silicon (equals to 11.8)
From the above equations, we see that if one side of the junction is more heavily
doped than the other, the depletion region will extend mostly on the lightly doped
side. For example, if (i.e., if the p region is more heavily doped), we can
approximate the above two equations to:

⁄
( )
* +
 ⁄
( )
* +
Dividing by ;

This special case is called a single-sided diode.

Problem 3:
For a pn junction having and ,
what are the depletion region depths for a 1-V reverse-bias voltage?

Solution
Since, and

⁄
( )
* +
( )

Since,

⁄
( )
* +

⁄
* +

Note that the depletion region width in the lightly doped n region is 1,000 times
greater than that in the more heavily doped p region.
 Seventh Lecture
2021 – 2022
BJT Structure and Fabrication
Fabrication of Double-Diffused BJT Structure:
Examine fabrication steps to create a vertical npn double diffused BJT structure on
an epitaxial layer
•Similar structure to the epi-diode
•Name derived from the fact that the base and emitter are formed by implants -in a
more modern device the emitter would be formed by another method
•Show more detail here than in notes and one small variation -separate sinker and
emitter diffusion steps.

BJT Fabrication -Starting Material

The starting material for a vertical npn structure is p-type substrate doped at
or less.

BJT Fabrication -First Oxide Deposition:

Using a chemical process (CVD), oxide is deposited on the wafer surface.

BJT Fabrication -Patterning of First Oxide:

Photo resist spun on top of the oxide is exposed using the buried layer mask (mask
#1).
The BL mask is usually generated automatically from other masks.
BJT Fabrication -Etching of First Oxide:
Using a wet etch, a window corresponding to the buried layer mask is opened in
the oxide.

BJT Fabrication -Final Buried Layer Window:

After the remaining PR is stripped, the deposited oxide has an opening etched in
the location specified by the buried layer mask.

BJT Fabrication -Buried Layer Implant:

The buried layer is formed with a high density (dose) implant of n-type dopant,
usually phosphorous.
Some lateral diffusion of dopants takes place during the implant.
Dopant is also introduced into the masking oxide.
BJT Fabrication -Final Buried Layer:
After the masking oxide is removed (etched), the result is a highly doped buried
layer region in the original silicon substrate.

BJT Fabrication -Deposition of Epi Layer:

Using epitaxial deposition (similar to CVD), a layer of very high quality
(crystalline) silicon is deposited on the surface.
Some diffusion of dopant soccurs from the highly doped buried ‫ مدفونة‬layer into
the more lightly doped epitaxial layer

BJT Fabrication -Final Epi Layer:

The resulting epitaxial layer will form the collector region in the BJT, with the
highly doped (low R) buried layer forming an equipotential region under the
device.
Note that the buried layer is now completely enclosed in silicon material.
BJT Fabrication -Isolation Region Exposure:
Layers of masking oxide layer and PR are formed on the surface
The PR is exposed using an isolation implant mask (mask #2)

BJT Fabrication -Isolation Implantation:

A heavy type doping forms the isolation regions
The masking oxide absorbs dopant, preventing implantation between the isolation
regions
BJT Fabrication -Final Isolated Structure:
After a long enough implant so that the isolation regions reach the underlying
substrate, the masking oxide is removed.

BJT Fabrication -Illustration of Isolation:

By connecting to the underlying substrate, the isolation implants electrically
disconnect regions of the epi layer from each other (recall that the entire wafer is
processed for any given step).
Electrical isolation is provided by the pn-junction formed between the implants
and the n-type epi layer.

BJT Fabrication -Sinker Mask Exposure:

Connection will be made to the buried layer (collector) using a sinker, an
implantation of high concentration and significant depth.
Oxide and PR layers are exposed using a sinker mask (mask #3).
BJT Fabrication -Sinker Implantation:

BJT Fabrication -Sinker Mask Exposure:

Once a window has been etched in the oxide, an n-type dopant implantation is
performed to create the sinker.

BJT Fabrication -Final Sinker Structure:

Depending on the implantation conditions and the thickness of the epi region, the
sinker may or may not reach right down to the buried layer.
BJT Fabrication -Base Region Implantation:
A p-type dopant (usually Boron) is implanted into the epi layer through the oxide
window to form the p-type base region.

BJT Fabrication -Final Base Region:

After implantation is complete, a p-type counter doped base region has been
formed in the n-type collector epi.

BJT Fabrication -Emitter Region Exposure:

Oxide/PR layers are exposed using an emitter mask(mask #5).
BJT Fabrication -Emitter Implant:
A heavy n-type dopant (usually As) is implanted through the oxide window
opening to form the emitter.
Control of this implant is critical to the BJT’s operation.

BJT Fabrication -Final Emitter Structure:

With the creation of the emitter region in the base (in the n-epi collector), the
basic BJT structure is complete, only metal contacts remain.

BJT Fabrication -Contact Cut Exposure:

Oxide is deposited which will isolate metal connections
PR is exposed using contact cut mask (mask #6)
BJT Fabrication -Contact Window Etching:
Etching of contact openings requires selectivity so etching does not remove
emitter, therefore wet etchant used

BJT Fabrication -Final Contact Cuts:

After etching, openings have been created in the oxide which will allow access to
the collector sinker, base and emitter regions

BJT Fabrication -Metal Deposition and Exposure:

After metal is deposited and PR formed on surface, exposure is performed using a
metal mask (mask #7)
BJT Fabrication -Final Interconnect Structure:
Once the metal has been etched to form interconnections between contacts, the
structure is complete.
Most modern processes would use more than one level of metal.

BJT Layout -Single Emitter, Base and Collector

Top view layout shows the various masks used to realize the basic structure.
Cross section is duplicated to show correspondence.
Buried layer and isolation masks can by generated automatically based on size of
base region and position of collector.
 Eighth Lecture
2021 – 2022
BJT Analysis

BJT Layout -Multiple base contacts:

Many other devices possible -example shows single emitter and collector with two
base contacts.
Large current devices have many emitter and base regions.

Current Flow in the Integrated npn BJT:

In the integrated BJT structure, the principle current flow for normal operation is
through the sinker, buried layer and up through the vertical npn structure.
The actual active area of the device is a relatively small portion of the overall
structure.
BJT Nomenclature ‫تسمية‬:

Quantity Emitter Base Collector Units

Doping /
Minority
Concentration
Diffusion
Coefficient

BJT Width Definitions:

An npn BJT has two pn-junctions, and hence two depletion regions.
Label the widths of the base-emitter and base-collector depletion regions and
, respectively.
Widths of remaining neutral region in collector, base and emitter are , and
, respectively.

BJT Depletion Widths:

Each depletion width is calculated using the previous pn junction expression with
the appropriate built in potential.
Example: BJT Width Calculations:
Calculate the equilibrium minority concentrations, diffusion coefficients and the
widths of the collector, base and emitter neutral regions for the structure given
below at the biases shown.

Example Solution:
Using the values of doping given and the applied potentials (note that is
calculated from and as 0.8 -1.5 = - 0.7V)

The collector neutral width is the collector material width minus the extent of the
BC depletion region into the collector
The emitter neutral width is the emitter material width minus the extent of the BE
depletion region into the emitter (note ≈emitter material width).

The base neutral width is the base material width minus the extents of the BE and
BC depletion regions into the base.
The equilibrium densities and diffusion coefficients are given by standard
formulas.
 Ninth Lecture
2021 – 2022
MOSFET Structure and Processing
To better understand how to model the behavior of the MOSFET, begin the same
way as the diode and bipolar, consider fabrication of the basic structure.
An important fundamental quantity, the oxide capacitance, will be identified from
the structure.
The layout of masks for the MOSFET structure will be considered, and the
effective channel length identified from processing considerations.

Substrate
The substrate of the MOSFET (Metal-Oxide-Semiconductor Field Effect
Transistor) is normally silicon, doped either p-type or n-type
P-type substrate → n-channel device
N-type substrate → p-channel device
Substrate is also termed bulk.
Substrate is connected using metal on the back side and/or a highly doped region
of similar type (substrate thickness is not shown to scale).

Gate
The MOSFET gate is a conductive region electrically isolated from the substrate.
Since the gate must provide an equipotential surface above the substrate, it must be
constructed from a very conductive material.
Older technology used metal (Al) gates, newer technology uses poly silicon, a
material with grains of crystalline structure separated by grain boundaries

1
Gate Oxide
The function of the gate oxide is to provide a high quality insulator between the
conductive gate and the substrate.
Although preventing current flow from gate to substrate, the oxide layer still
allows penetration of electric field from gate to substrate.
The gate oxide is usually silicon dioxide (hence the name), or can be other
insulators such as Si3N4

2
MOSFET Oxide Capacitance
If the thickness of the oxide insulating layer is labeled , the per unit area oxide
capacitance associated with the layer is defined as

The oxide permittivity is a tabulated value, for being 3.9 times the
permittivity of free space.

3
Example: Oxide Capacitance Calculation
Calculate the per unit area oxide capacitance for a MOSFET whose gate oxide is
20 nm thick.

Solution:
Converting the oxide thickness to cm gives

The per unit area oxide capacitance is therefore

Source and Drain

The source and drain of the MOSFET are two regions with high doping of opposite
type to the substrate immediately adjacent to the edges of the gate.
The source and drain regions are normally contacted with metal, separated from
the gate and substrate by a dielectric isolation layer.

Field Oxide
The MOSFET structure is surrounded by a thick (≈1 μm) layer of insulator,
normally silicon dioxide, called the field oxide.
The field oxide isolates the gate from the substrate outside the active device region
as well as preventing the formation of other parasitic MOSFET devices.

4
MOSFET Symbols
The symbols and potential definitions for the MOSFET are shown to the right.
An n-channel device has;
 type substrate
 source and drain regions
 Substrate normally connected to the most negative potential in a circuit.
A p-channel device has;
 type substrate
 source and drain regions
 Substrate normally connected to the most positive potential in a circuit.

Active Region Masking

Using a mask, silicon nitride is patterned to remain in the areas which will form the
active region of the MOSFET
A pad oxide is grown on the surface before deposition of the nitride to protect the
silicon surface from damage induced by the different bonding structure of the
nitride

5
Field Oxide Formation
Using wet oxidation (since the quality is not critical and a thick layer is required),
the field oxide is grown on the wafer surface outside the active areas

MOSFET Fabrication -Device Well Structure

After the nitride and pad oxide are stripped, the active area is surrounded by field
oxide and therefore lies inside a “well” in the field oxide.
This is the origin of the term device well to refer to the active area of the MOSFET
The active area mask is sometimes called the device well mask

Gate Oxide and Poly-silicon

A thin (10-30 nm) gate oxide is then grown on the surface since the quality of this
oxide is critical and the thickness is not large, a dry oxidation is used
•Poly-silicon is then deposited using CVD and the oxide and poly are patterned
using the poly-silicon mask.

6
Gate Connection
The gate within the MOSFET area as well as all other poly-silicon lines are formed
simultaneously
The gate is connected by running the poly-silicon up onto the field oxide and to
another point or eventually to a connection to metal

Source/Drain Implantation
The source and drain are then implanted with the gate in place
This process is called self-aligned since the source and drain do not need to be
optically aligned with the gate
Some lateral diffusion occurs which makes the actually distance between the
source and drain less than the length of the gate material

7
Dielectric Patterning
A second layer of dielectric is deposited using CVD and patterned to open
windows to the source and drain
This step uses a contact cut mask

MOSFET Fabrication -Metallization

Metal is deposited over the back side of the wafer to form the backside substrate
contact
Metal is also deposited on the surface and patterned using the metal mask

8
MOSFET Fabrication -Metallization
Metallization surrounds the contact cut area, which is normally constrained to be
within the source drain region
Metal to poly-silicon connection would have been made elsewhere (on top of field
oxide)

Simplified MOSFET Layout

A simple four mask representation is shown to the right
Note that poly crosses the active region (riding up onto the field oxide) -wherever
poly and active coincide, poly will be separated by gate oxide only
Because the process is self-aligned, the source and drain will be formed in any
active region not coincident with poly

9
MOSFET Effective Channel Length
Lateral diffusion LD of the source and drain cause the distance between the source
and drain edges to be less than the length of the gate poly-silicon
The drawn channel length refers to the length of the gate material specified on the
mask
The effective channel length L is the actual distance between the source and drain
edges, which will be the electrical channel length

MOSFET Geometry
The (effective) channel length L is the distance between the source and drain
regions under the gate
The channel width W is the width of the source and drain, and hence the channel,
regions
First order quantitative analysis will consider behavior to be independent of
location along W, therefore use a 2D analysis and multiply result by W

10
11