ESSDERC 02/9/25

Silicon Single-Electron Devices for Logic Applications

NTT Basic Research Laboratories

Yasuo Takahashi
Collaborators: Yukinori Ono, Hiroshi Inokawa, Kenji Shiraishi, Seiji Horiguchi, Kenji Yamazaki, Kenji Kurihara, Katsumi Murase Akira Fujiwara, Masao Nagase, Hideo Namatsu,
NTT

Outline
1. Background 2. Novel Fabrication Procedure for SETs (PatternDependent Oxidation: PADOX) 3. Advantages of SETs made by PADOX 4. Application of SETs for Logic Circuits (Single-Electron Inverter & Adder, Multigate SET, Multiple-Valued Operation) 5. New Device (Single-Electron CCD) 6. Summary
NTT

Si Single-Electron Transistor
Gate electrode Vg Silicon island Vd Source
Silicon MOS Transistor
Gate electrode Vg Channel Vd Source Drain Silicon

e-

Drain

Tunnel Barrier

Structure of Si SET
Si single-electron transistor (SET) and MOSFET have similar structure

Id Vth Vg NTT

Equivalent Circuit
Vg Silicon island Vd

Gate electrode

Tunnel capacitor Source Cs

Gate Cg Drain Cd Island

eSource Drain

Tunnel Barrier

Structure of Si SET

Equivalent Circuit of Si SET

NTT

Operation of SET
Single-electron Transistor (SET) Vd is small Cs Cd Vg Cg ++ + Vd The same number of electrons Ngate = CgVg/e

SET island Current flows only when the number of electrons in the gate is half-Integer

Nisland = Integer

0 0.5 1 1.5 2 2.5 3 Number of electrons in the island VgCg/e

Current (Conductance) oscillates as a function of gate voltage (Vg)

Single-Electron Transistor
Gate electrode Vg Silicon island Vd Source eDrain

Tunnel Barrier

Structure of SET

Difficulties in fabricating SETs Formation a small island (~10 nm) Attaching two tunnel barriers to the island

Strategy for Size Reduction

SIMOX (Very thin Si layer) EB lithography

Size Reduction Veretical Lateral

Three Dimensions Theremal Oxidation

NTT

Pattern-Dependent Oxidation
(PADOX) Self-aligned formation of a single Si island
1D-Wire
Gate electrode

Si Island (SET)
Drain Dr

SET
Island Quantum size effect
Potential

Source Buried SiO2 Substrate SIMOX

Wire Size Width=30 nm Length=30-100 nm Height=30 nm

Si layer

Stress

(Y. Takahashi, IEDM 1994)

Poisson NTT

Self-aligned formation of a single Si island

1D-Wire
Gate electrode

Pattern-Dependent Oxidation (PADOX)

Si Island (SET)
Drain Dr

Tunnel capacitor Source Cs Island

Gate Cg Drain Cd Cb Substrate

Source Buried SiO2 Substrate SIMOX

Wire Size Width=30 nm Length=30-100 nm Height=30 nm

Si layer

"Single-Electron Transistor (SET)"

(Y. Takahashi, IEDM 1994)

NTT

I-Vg Characteristics of Si SET

1.5

Drain current (nA)

Number of electrons
1

T = 40 K
L = 70 nm, W = 40 nm, Vd = 1mV

0.5

2 3 Gate Voltage (V)

NTT

Characteristics of Si SET Fabricated by PADOX

20x10
-9

Excited states

Conductance (S)

15 10 5

T = 40 K
L = 70 nm, W = 40 nm, Vd = 10 mV

0 1.0 1.5 2.0 2.5 3.0 3.5 4.0

Gate Voltage (V)

large charging energy and exited states NTT

Stability of I-Vg Characteristics

50

Drain Current (nA)

June 10, 1994

40 30 20 10 0

T = 40 K T = 30 K Vd = 10 mV

years
April 16, 2001 0 0.5 1 1.5 2

Gate Voltage (V) Gate Voltage (V)

NTT

0.3

Threshold Voltage for 1-st Electron

Vfp Vfp - e/(2Cfg)

Threshold Voltage Voltage (V) for 1-st Electron (V)

0.2 0.1 0.0 -0.1 0.0 0.5 1.0

Increase by quantum size effect Almost constant & -100 mV

1.5

2.0

2.5

Gate Capacitance (aF) Cfg (aF)

Island size
NTT

Advantages of Si SET (PADOX)

Small Total Capacitance ~1 aF (~300 K) Integration of Small Islands Reproducible and Controllable Fabrication Process (Capacitance and Conductance) Very Stable Operation like a MOSFET (No Effects of Offset Charge) Same Process as for Si MOS LSI/SOI
NTT

Logic Applications of Si SET

NTT

Logic Applications of Si SET

Special Features of SET
Oscillatory I-Vg Characteristics Operattion as a p-type and n-type Switch
(CMOS-type Inverter, Adder)

Multiple-valued Operation
(Multiple-valued memory, Quantizer)

Multigate Capavility Gate-Level Summation

(X-OR gate, Multi-bit Adder)
NTT

CMOS-type of SET Logic

NTT

CMOS-type Single-Electron Inverter

p-switch
VDD
GND

Input
VDD

Output Two SETs are connected in series

NTT

n-switch

GND

J. R. Tucker, JAP, 72, 4339 (1992).

SETs Connected Series (V-PADOX)

AFM Image

SET

Top Gate (Input) GND VDD

Control Gate A (VA) Output

Y. Ono et al., APL, 76, 3121 (2000).

Control Gate B (VB)

SET
NTT

Inverter Operation
Input-Output Transfer Characteristics
30

Output Voltage (mV)

VA = 0 V VB = 7 V

25 20 15 10 5 0

VDD = 20 mV dVout/dVin = 1.3 T = 27 K

T = 30 K
-10 0 10 20

Input Voltage (mV) Transfer of signal & CMOS-type logic Y. Ono et al., APL, 76, 3121 (2000). NTT

Multiple-Gate Si SET

NTT

Multi-gate MOSFET & SET

Multi-gate MOSFET

Multi-gate SET

T. Shibata et al., IEEE Tras. ED, 39, 1444 (1992).

Y. Takahashi et al., APL, 76, 637 (2000).

NTT

Multi-gate SET (X-OR gate)

Multi-gate SET

Cgi = Cg0 (I =1,2 N) VHini = e/2Cg0 Even number of High-gate Low states Odd number of High-gate High states
Y. Takahashi et al., APL, 76, 637 (2000).

NTT

SEM Images of Dual-gate SET

Dual-gate SET (Parallel Gates)
Drain

SET Island
200 nm

Drain 200 nm

Gate 1

Source

Source

Gate 2

Si wire (SET)

Ultra fine parallel gate (XOR Gate)

NTT

Y. Takahashi et al., APL, 76, 637 (2000).

XOR Operation of Dual-gate SET

V in1 V in2 Id Cg1 Cg2 Vdd SET Cg1= 0.42 aF Cg2= 0.36 aF

Y. Takahashi et al., APL, 76, 637 (2000).

NTT

Multiple-Valued Application of SET

NTT

Corresponding to Electron Number

Multiple-valued Memory V Vgg Id I MOSFET Io SET Vds-V V
gg

Multiple-Valued Application

I-Vg charac. (Current Output) Id Vgs

MOSFET

Multi-stable Voltage Output 4 V 5 6 Io NTT

th

Number of Electrons I 1 2 3

Vgs

H. Inokawa et al., DRC, (2001).

Integrated SET and MOSFET

Gate poly-Si

Top View
Silicon-OnInsulator

SET

MOSFET

H. Inokawa et al., DRC, (2001).

NTT

Corresponding to Electron Number

Multiple-valued Memory Word line Memory node Vgg I0 MOS FET2 MOSFET2 MOS FET1 SET
Io V
H. Inokawa et al., DRC, (2001).

Multiple-Valued Application
Memory node

Stable Points I

Bit line

SET

MOSFET1

400 nm NTT

SET-MOSFET 2-terminal I-V

7 6 I (nA) 5 4 3 2 1 0 1 2 a b e c d stability points 3 V (V) 4 f Io

H. Inokawa et al., DRC, (2001).

NTT

Single-Electron Quantizer
(Multiple-Valued Operation)
Pulse Generator Sync HP8110A Function Generator HP33120A Vdd CLK Vin Vgg external MOSFET1 Oscilloscope HP5450C MOSFET R Io Vdd2 external MOSFET2

Vout Vout 2

SET
Vss2

Multiple-Valued Memory
H. Inokawa et al., IEDM, (2001).

NTT

Single-Electron Quantizer
Input
Vin CLK fCLK: 25Hz
f e d c b a 7 6 5 4 3 2 1

Out put

Vout

Number of Electrons in the Island

H. Inokawa et al., IEDM, (2001).

NTT

New Device for Single-Electron Transfer & Detection (Single-Electron CCD)

NTT

Single-Electron CCD
Device Structure
Si wire MOSFETs Stored hole
n+drain #1 n+source n+ drain #2

n+poly-Si upper gate (sense)

Buried oxide Si substrate (back gate) Hole potential Stored hole

n+poly-Si lower gate (front)

Valence band
A. Fujiwara et al., Nature, 410, 560 (2001).

Gate oxide Si layer

Transfer of single hole

NTT

Structure & Operation principle

Si wire Electric field (~105 V/cm) V <0 fg Hole Electrons

Single-Electron CCD

Sense gate (Top gate)

Front gate (Fine gate)

Si wire 20 nm Oxide

Sense current Sensed Sensed by by electron current electron current

NTT

Vbg>0

Back gate

Electron-hole Electron-hole separation (15 nm) separation

A. Fujiwara et al., Nature, 410, 560 (2001).

Sensing of Single-Hole
flow of electrons oxide back gate Stored holes
4 3 2 1

front gate

nh = 0
Sense Gate Voltage

Vd= 0.1 V Vfg= -1.6 V Vbg= 60 V

No illumination

Current (A)

Si

nh

10 10 10 10 10 10

-9

-10 -11 -12 -13 -14

T= 25 K
nh =5 nh =6 nh =3 nh =4

nh =2

nh =1 nh =0

Gate Capacitance ~10 aF (90 nm-long Si wire MOSFET) e2/C~ 16 meV

-1.0

-0.5

0.0

0.5

1.0

1.5

Hole generation by illumination

A. Fujiwara et al., Nature, 410, 560 (2001).

Sense Gate Voltage (V)

NTT

Single-Hole Transfer
<Sense> Vsg =0.88 V (high) Current#1 Current#2
10
-8

< Sense (nh#1, nh#2) > < Transfer >

10 10
-8 -9

Current #1 (A)

10

-9

Vfg1
Vfg1 :-1.3 V

Vfg2
-2.5 V

10 10 10

-10

T=25 K 10
(0, 1) (1,0) (0,1) (1,0)

-10 -11 -12 -13 -14

Current #2 (A)

<Transfer> Vsg =-1 V (low)

-11

10 10

-12

10 0 100 200 300 10

Time (s)

A. Fujiwara et al., Nature, 410, 560 (2001).

NTT

Room Temperature Operation of Single-Hole CCD

1 2 nh=5 4 3 nh=0

Hole storage by One-shot illumination

NTT

Summary
PADOX: Pattern-Dependent Oxidation Self-aligned formation of small Si islands
Small size, Reproducible & Controllable, Stable operation, Compatible with Si MOS LSI
Multiple-gate structure Multiple-peak characteristics

Flexible fabrication for SETs

Single-electron Logic Circuit (Inverter, Adder, X-OR, Multiple-valued logic)
NTT

Summary
New Device: Single-Electron CCD
Simple structures High temperature operation

Single-electron Transfer & Ditection

NTT

End of Presentation
Yasuo Takahashi