1

CPU STRUCTURE &

FUNCTION
 Pre-requisite knowledge
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 Logic gates
 Sum of products
 Simplification/minimization
 Flip flops
Logic Gates
 Let recall: Sum of product &
4
Simplification
A B C D F
a. Write the Boolean function for the given truth
0 0 0 0 1
table and draw the circuit diagram
0 0 0 1 0
0 0 1 0 0 b. Using Boolean identities table, simplify the
0 0 1 1 1 Boolean function obtain in (a) and draw the
0 1 0 0 1 circuit diagram
0 1 0 1 0
0 1 1 0 1 c. Using Karnaugh Map, simplify the Boolean
0 1 1 1 1 function obtain in (a) and draw the circuit
1 0 0 0 1 diagram
1 0 0 1 0
d. Draw the circuit diagram using NAND gate
1 0 1 0 0
based on your answer in (c)
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
 Let recall: HA/FA
5

 Below show an addition example of two binary

numbers:
x1 x0 1 0
+ y1 y0 + 0 1
s1 s0 1 1

 Based on the addition above, design a circuit using

half/full adder where
▪ input1: x0, x1
▪ input2: y0, y1
▪ Sum: s0, s1
 Let recall: Flip flop
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Determine the value (FF1, FF2, FF3, w, x, y and z) of the following circuit by completing
the given truth table. Input A changes value as shown in the truth table. FF1, FF2 and
FF3 is the D Flip Flop while w, x, y and z is the output

A FF1 FF2 FF3 w x y z

0 0 0 0 1 0 0 0
FF1
1 1 0 0 1 1 0 0

0 1 0 0 1 1 0 0

1 1 1 0 0 1 1 0
FF2
0 1 1 0 0 1 1 0

1 0 1 1 1 0 1 1

0 0 1 1 1 0 1 1
FF3
1 1 0 1 1 1 0 1

0 1 0 1 1 1 0 1

1 1 1 0 0 1 1 0
7

Let’s look at CPU building block

 Contents
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I. Processor organization
II. Register organization
III. Instruction cycle & Data Flow
IV. Instruction pipelining
 Let watch video
9

 Scott CPU:
https://www.youtube.com/watch?v=cNN_tTXABUA
 ALU:
https://www.youtube.com/watch?v=UhxNciYUenA
https://www.youtube.com/watch?v=WvDogBOFYKA
CPU: SYSTEM BLOCK DIAGRAM
 Processor organization: 3 components
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 ALU (arithmetic logic unit)

 Performs calculations and comparisons (data changed)
 CU (control unit): performs fetch/execute cycle
 Functions:
◼ Moves data to and from CPU registers and other hardware
components (no change in data)
◼ Accesses program instructions and issues commands to the ALU
 Subparts:
◼ Memory management unit: supervises fetching instructions and data
◼ I/O Interface: sometimes combined with memory management unit as
Bust Interface Unit
 Registers
 Example: Program counter (PC) or instruction pointer (IP) determines next
instruction for execution
THE LITTLE MAN COMPUTER
 Internal view
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ALU - does the computation (or processing of data)

Control Unit - control the movement of data and instruction in & out of the processor and
operation of ALU
Registers - a set of storage locations
 CPU: Things that it must do
14

 Fetch instruction: The processor reads an instruction from memory

(register, cache, main memory).
 Interpret instruction: The instruction is decoded to determine what action
is required.
 Fetch data: The execution of an instruction may require reading data
from memory or an I/O module.
 Process data: The execution of an instruction may require performing
some arithmetic or logical operation on data.
 Write data: The results of an execution may require writing data to
memory or an I/O module.

Hence, a small amount of internal memory, called the registers, is needed by

the CPU to fulfill these requirements (i.e. remember location of last instruction,
store instruction & temporary data while instruction is being runs)
 What is register?
15

 Register is a special purpose memory.

 Built right into the CPU and contain data needed by the CPU (i.e. ALU). This
memory is vital for moving data in and out of the main memory and to
process the data.
 CPU uses the registers to handle the process of execution effectively and
efficiently.
 They are a part of the central processing unit but can not be considered as
a part of main memory. They can hold only one piece of data at a time.
 Registers receive the information, hold it temporarily and pass it on as
directed by the control unit.
 The number of registers varies from computer to computer, each one
designed to perform a specific function.
https://www.youtube.com/watch?v=V04dtxEUjsI
 Register
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 Perform two functions:

 User-Visible Registers
◼ Enable the assembly-language programmer to minimize main memory
references by optimizing use of registers
 Control and Status Registers
◼ Used by the control unit to control the operation of the CPU
◼ OS control the execution of programs.
◼ They are not visible to the user.
◼ Visible to machine instructions executed in a control or operating system
mode
 Register: User-visible (Categories of use)
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 General Purpose - can store data and address

 Data - available to the programmer for general
data manipulation.
 Address - hold addresses and are used by
instructions that indirectly access primary memory.
 Segment pointers - hold base address of the
segment in use
 Index registers - used for indexed addressing
and may be auto indexed
 Stack Pointer - a dedicated register that points to
top of a stack. Push, pop, and other stack
instructions need not contain an explicit stack
operand.
 Condition Codes - Contains flags set by the
processor during the execution of instructions (to
indicate the status of the processor).
 Register: Control and Status
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 Program counter (PC): Contains the address of an instruction to be

fetched.
 Instruction register (IR): Contains the instruction most recently fetched.
 Memory address registers (MAR): Contains the address of a location
in memory.
 Memory buffer register (MBR): Contains a word of data to be written
to memory or the word most recently read.

The four registers are used for the movement of data between the CPU and
memory. Within the CPU, data must be presented to the ALU for processing.
The ALU may have direct access to the MBR and user-visible registers.
Alternatively, there may be additional buffering registers at the boundary to
the ALU: these registers serve as input and output registers for the ALL and
exchange data with the MBR and user-visible registers.
 Register organizations
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 8086 CPU Registers
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 Fourteen (14) registers that are accessible to the programmer.

 Eight (8) of the registers are known as general purpose registers i.e. they can
be used by the programmer for data manipulation.
 Each of the registers is 16 bits long i.e. can contain a 16-bit binary number.
 The first four registers are referred to as data registers. AX, BX, CX and
DX registers.
 The second four are referred to as index/pointer registers. They are the
SP, BP, SI and DI registers.
 The data registers can be treated as 16-bit registers or they can each be
treated as two 8-bit registers.
 Each 8-bit register can be used independently.
 The AX register may be accessed as AH and AL (H and L refer to high-order
and low-order bytes). Similarly for BX may be accessed as BH, BL; CX may be
accessed as CH, CL and DX may be accessed as DH, DL.
 8086 CPU Registers (cont…)
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 Control and status register: instruction pointer (IP) and the status word, or
flags register.

 Instruction Pointer Register

 Used to control which instruction the CPU executes. The IP is used to store the
memory location of the next instruction to be executed.

 The CPU checks the program counter to ascertain which instruction to carry out
next. It then updates the program counter to point to the next instruction. Thus the
program counter will always point to the next instruction to be executed.
 8086 CPU Registers (cont…)
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 Status (Flags) Register

 Nine individual bits of the status register are used as control flags (3 of
them) and status flags (6 of them).
 The remaining 7 are not used.
 A flag can only take on the values 0 and 1. We say a flag is set if it has
the value 1.
 The status flags are used to record specific characteristics of arithmetic
and of logical instructions.
 8086 CPU Registers (cont…)
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 Status (Flags) Register

 Instruction Cycle
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 Include the following stages:

 Fetch: Read the next instructions from memory into the processor
 Decode/Execute: interpret the opcode and perform the indicated
operation
 Interrupt: If interrupt are enable and an interrupt has occurred, save the
current process state and service the interrupt.
 Indirect: requires additional memory accesses (i.e. indirect addressing)
 Data Flow (Fetch cycle)
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During the fetch cycle, an instruction is read

from memory.

a) The PC contains the address of the next

instruction to be fetched. This address is
moved to the MAR and placed on the
address bus.
b) The control unit requests a memory read,
and the result is placed on the data bus
and copied into the MBR and then moved
to the IR.
c) The PC is the incremented by 1,
preparatory for the next fetch.
Video:
https://www.youtube.com/watch?v=7hB2SEZ3zqg
https://www.youtube.com/watch?v=h8NO0POQY34

Example - http://www.eastaughs.fsnet.co.uk/cpu/execution-fetch.htm
 Data Flow (Indirect cycle)
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a) Once the fetch cycle is over, the control

unit examines the contents of the IR to
determine if it contains an operand
specifier using indirect addressing. If so, an
indirect cycle is performed.
b) The rightmost N bits of the MBR, which
contain the address reference, are
transferred to the MAR. Then the control
unit requests a memory read, to get the
desired address of the operand into the
MBR.

Example - http://www.eastaughs.fsnet.co.uk/cpu/execution-indirect.htm
 Data Flow (Decode/Execute cycle)
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 The execute cycle depends on the various machine instructions is in the IR.
 This cycle may involve transferring data among registers, read or write
from memory or I/O, and/or the invocation of the ALU.
 Data Flow (Interrupt cycle)
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a) The contents of the PC are transferred to

the MBR to be written into memory.
b) The special memory location reserved for
this purpose is loaded into the MAR from
the control unit. (for example, it might, be
a stack pointer).
c) The PC is loaded with the address of the
interrupt routine. As a result, the next
instruction cycle will begin by fetching the
appropriate instruction.
 Instruction pipelining
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“It is a technique used in the design of computers to increase their instruction throughput (the
number of instructions that can be executed in a unit of time). Pipelining does not reduce the
time to complete an instruction, but increases instruction throughput by performing multiple
operations in parallel”
- Wikipedia -

 Instruction pipelining - used to speed up processor execution.

 Pipelining involves breaking up the instruction cycle into a number of
separate stages that occur in sequence (e.g., fetch instruction, decode
instruction, determine operand addresses, fetch operands etc).
 Analogy: manufacturing assembly lines;
 By laying the production process out in an assembly line, products at various
stages can be worked on simultaneously.
 This process is also referred to as pipelining, because, as in a pipeline, new
inputs are accepted at one end before previously accepted inputs appear as
outputs at the other end.
30
 Let watch video
31

 Manufacturing assembly line

1. Audi TT - https://www.youtube.com/watch?v=mXI7K3GX0BM
2. Yamaha R25 - https://www.youtube.com/watch?v=wbUFXrBDtco

3. Factory - https://www.youtube.com/watch?v=ovMz2gTjvFA

 Pipeline theory:
1. https://www.youtube.com/watch?v=doJpguZFTe0
2. https://www.youtube.com/watch?v=l3Rvf7tv2dY
3. https://www.youtube.com/watch?v=r_LEyI5UTww
 Pipelining strategy
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 Example: subdividing instruction processing into two stages:

fetch instruction and execute instruction.

 During the execution of an instruction, there a times when main memory is not being
accessed. This time could be used to fetch the next instruction in parallel with the
execution of the current one.

 The first stage fetches an instruction and buffers it. When the second stage is free,
the first stage passes the buffered instruction (to be executed).

 While the second stage is executing the instruction, the first stage takes advantage
of any unused memory cycles to fetch and buffer the next instruction. This is called
instruction prefetch or fetch overlap.
 Pipelining strategy (cont…)
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 Note: pipelining requires registers to store data between stages.

 This process will speed up instruction execution.
 If the fetch and execute stages were of equal duration, the instruction cycle
time would be halved.

Example - http://www.eastaughs.fsnet.co.uk/cpu/further-pipelining.htm
 Pipeline - decomposition
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 Pipelining can severely cut the time taken but the instruction execution
process do not necessarily take an equal amount of time.
 E.g. Time taken to 'execute' generally longer than 'fetch‘ and this makes it
much harder to synchronise the various stages of the different instructions.
 Also, some instructions may be dependent on the results of other earlier
instructions. This can arise when data produced earlier needs to be used,
 when a conditional branch based on a previous outcome is used.
 Solution: breaking the instruction execution cycle into stages that are
more likely to be of an equal duration. For example, the diagram below
shows how the cycle can be broken down into six stages rather than
three:
 Pipelining – decomposition (cont…)
35

 Pipeline contain several stages. Consider the following

decomposition of the instruction processing.
 Fetch instruction (FI): Read the next expected instruction into a buffer.
 Decode instruction (DI): Determine the opcode and the operand specifiers.
 Calculate operands (CO): Calculate the effective address of each source
operand. This may involve displacement, register indirect, indirect, or other
forms of address calculation.
 Fetch operands (FO): Fetch each operand from memory. Operands in
registers need not be fetched.
 Execute instruction (EI): Perform the indicated operation and store the result,
if any, in the specified destination operand location.
 Write operand (WO): Store the result in memory.
 Pipelining – decomposition (cont…)
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 Figure 12.10 shows that a six-stage pipeline can reduce the execution time
for 9 instructions from 54 time units to 14 time units.
 Pipelining – decomposition (cont…)
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Assumptions (see figure 12.10)

 All instruction are equal duration
 Each instruction goes through all six stages of the pipeline (This will not
always be the case)
 All of the stages can be performed in parallel.
 There are no memory conflicts. For example, the FI, FO, and WO stages
involve a memory access. The diagram implies that all these accesses can
occur simultaneously. Most memory systems will not permit that. However,
the desired value may be in cache, or the FO or WO stage may be null.
Thus, much of the time, memory conflicts will not slow down the pipeline.
 Pipelining: Advantages
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 The cycle time of the processor is reduced by increasing the instruction

throughput. Pipelining doesn't reduce the time it takes to complete an
instruction; instead it increases the number of instructions that can be processed
simultaneously ("at once") and reduces the delay between completed
instructions (called 'throughput').
The more pipeline stages a processor has, the more instructions it can process
"at once" and the less of a delay there is between completed instructions.
 If pipelining is used, the CPU Arithmetic logic unit can be designed faster
39

Question and Answer

 *Do you know: Opcode
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 Opcode are represented by abbreviations, called mnemonics, that indicate

the operation. Common examples include
ADD Add
SUB Subtract
MUL Multiply
DIV Divide
LOAD Load data from memory
STOR Store data to memory

 Operands are also represented symbolically. For example, the instruction

ADD R, Y
may mean add the value contained in data location Y to the contents of
register R. In this example, Y refers to the address of a location in memory,
and R refers to a particular register. Note that the operation is performed
on the contents of a location, not on its address.
 Instruction Cycle
41

Instruction cycle state diagram

 Do you know that:
42

*http://www.teach-ict.com/as_as_computing/ocr/H447/F453/3_3_8/lowlevel/miniweb/pg4.htm
 Pipelining: Disadvantages
43

 The design of a non-pipelined processor simpler and cheaper to manufacture, non-pipelined

processor executes only a single instruction at a time.
 In pipelined processor, insertion of flip flops between modules increases the instruction latency
compared to a non-pipelined processor.
 Many designs include pipelines as long as 7, 10, 20, 31 and even more stages; a disadvantage
of a long pipeline is when a program branches, the entire pipeline must be flushed (cleared). The
higher throughput of pipelines falls short when the executed code contains many branches: the
processor cannot know in advance where to read the next instruction, and must wait for the
branch instruction to finish, leaving the pipeline behind it empty.
*This can be solve by predicting whether the conditional branch instruction will branch based on
previous activity. After the branch is resolved, the next instruction has to travel all the way through
the pipeline before its result becomes available and the processor resumes "working" again.
 When a programmer (or compiler) writes assembly code, they generally assume that each
instruction is executed before the next instruction is being executed. When this assumption is not
validated by pipelining it causes a program to behave incorrectly, thus is known as a ’hazard’.
*Various techniques for resolving hazards or working around such as forwarding and delaying
(by inserting a stall or a wasted clock cycle) exist.