Analysis and Design of

Low Drop-Out Regulator

REVISE FROM Lecture 12 Low Drop-Out Voltage Regulators Analog and Mixed-Signal Center, Texas A&M University

Nguyen Thanh Yen – [email protected]

Hanoi – May 2021

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 Linear Regulator: Principles

+
- VO must be constant and RC << RLOAD
RC
- VBAT is changing as a function of time:
RLOAD VO
VBAT RLOAD
VO  VBAT
RLOAD  RC
-

Thus in order to keep constant VO , the value of the controlling resistor RC yields:
 V  VO  V 
RC  RLOAD   BAT   RLOAD   LDO 
 VO   VO 
How can we automatically pick the value of RC such that VO = Vdesired; reg-voltage ?

RC
+

VC
Feedback RLOAD VO
VBAT
Control

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 How the RC and the Feedback Control
could be implemented?
ID
NMOS Transistor PMOS Transistor

a b a b
VGS

VC = VGS a b VC = -VGS = VSG

VDO(n) = VSAT + VGS VDO(p) = VSD(SAT)
ILOAD

Vdo = ILOADRC

VO VO

R
Error Amplifier R1 V V
2
0 Error Amplifier R1
R R
O REF
1 2

VC,NMOS VC,PMOS
R2  R  R2
V O UT
V REG
 V  1 
O
1
V REF

VREF  R 2  VREF

Make sure the closed loop is negative.

VREF is a band-gap voltage which is also supplied by VBAT=VIN.

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 LDO Parameters
 Dropout voltage (Vdo): minimum voltage drop across the input and output terminals of the LDO
with the system is able to regulate.
 Input rail range: range of the input supply voltage that the system is able to regulate in.
 Output current range: range of the output current handling capability of the regulated output
voltage.
 Output capacitor range: range of the output capacitance that the system is not unstable for a
given load current range.
 Output regulated voltage range: range of the output voltage that the system guarantees.
 Load regulation: the variation in output voltage as output current is swept from min to max.
 Line regulation: the variation in output voltage as input supply voltage is swept from min to max.
 Power Supply Rejection (PSR): the ac coupling of the input supply voltage on the output
voltage.
 Load/Line transient regulation: the response speed of the system at fast Load/Vsupply
transition.
 Short circuit current limit: current drawn at short circuited to ground of the output voltage.
 Power Efficiency: the ratio of the output load power consumption to input supply power.
 Overshoot: high transient output voltage at start-up or during load and line transients.
 Thermal Shut down: over temperature protection of the part from damage.

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 LDO Analysis
VIN

Error Amplifier
VX gm( Vx – ViN ) rop
Ref
VIN = VBAT PMOS Pass Transistor
VIN AEA( VDIV - VREF)
AEA Vo
R1
R1
Io VDIV RL
VDIV
Load (RL) R2
R2

Basic LDO Topology Small Signal Representation

 1 1 1 1   1  1 1  V
VO      VDIV   g m AEA   g m AEAVREF  VIN   g m  (1) and VDIV     O  0 (2)
r  r   R1 R2  R1
 op RL R1   R1   op 
VIN (1  APT )  VREF APT AEA
Solving the (1) and (2), VO becomes: VO 
r
(1  APT AEA  op )
RL
Where: APT = gmrop , β = R2/(R1 + R2) , and (R1 + R2) >> RL
Vin V
If APTAEAβ (open loop gain) and APT >> 1  VO   REF
AEA  
Observe that Vin is attenuated by AEA and VREF is not.
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 Line Regulation

The line regulation is a steady-state specification. It can be defined as:

VO 1  APT
LR  
VIN rop
(1  APT AEA  )
RL
Vo 1
OR LR  
Vin AEA

For a practical case with non-idealities such as offset Op-Amp voltage Vos
and reference voltage error Vref the line regulator becomes:

Vo 1  R  V  Vos 
  1  1  REF 
Vin AEA  R2  Vin 

Observe that designers should also minimize Vos and provide VREF to be independent of VBAT and
temperature and process variations.

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 Load Regulation
Io

R1

GEA ∆VDIV RL
RL
Vin Vo+∆Vo

R2

VREF

ΔIo = ΔVDIVGEAα = [R2/(R1 + R2)]ΔVoGEAα

Where:
- GEA : transconductance of the error amplifier.
- α : current gain of the pass transistor.

VO 1  R1 
The load regulation can be expressed as:    1
I O GEA  R2 

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 LDO ESR Statility

One of the most challenging problems in designing LDO is the stability problems due to the closed loop
and the parasitic components associated with the pass transistor and the error amplifier. In fact to
compensate the loop stability a large external capacitor is often connected at the output. i.e.

Vo
1  s / wL
Z CL ( s)  Im
sC L
RESR
Re
CL ωL = 1/RESRCL -wL

Where CL is of the order of μF with a small equivalent series resistor (RESR).

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 Different Compensation Techniques
for Stability Purposes (1/4)
1. Internal zero generation using a differentiator
– An auxiliary fast loop (differentiator) provides both a fast transient detector path as well as
internal ac compensation.
– The simplest coupling network might be a unity gain current buffer.
– Cf senses the changes in the output voltage in the form of a current that is then injected into
pass transistor gate capacitance.

Ref: Robert J. Milliken, Jose Silva-Martínez, and Edgar Sánchez-Sinencio “Full on-chip CMOS low-dropout voltage regulator,”
IEEE Trans. on Circuits and Systems – I, pp 1879-1890, vol. 54, Issue 9, Sept. 2007.

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 Different Compensation Techniques
for Stability Purposes (2/4)
2. Capacitive feedback for frequency compensation
– It introduces a left hand plane zero in the feedback loop to replace the zero generated by
ESR of the output capacitor.
– the capacitor is split into two frequency-dependent voltage-controlled current sources
(VCCS) and grounded capacitors.
– Instead of adding a pole–zero pair with zero at lower frequency than the pole, in this
technique only a zero is added.
– It needs a frequency dependent voltage control current source (VCCS).

Ref: Chaitanya K. Chava, and Jose Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,”
IEEE Trans. on Circuits and Systems – I, vol. 51, No.6, pp. 1041-1050, June 2004.
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 Different Compensation Techniques
for Stability Purposes (3/4)
3. DFC frequency compensation
– It is a pole-splitting compensation technique especially designed for compensating amplifier with
large-capacitive load.
– DFC block composed of a negative gain stage with a compensation capacitor Cm2, and it is
connected at output of the first stage. Another compensation capacitor Cm1 is required to
achieve pole-splitting effect.
– The feedback-resistive network creates a medium frequency zero for improving the LDO
stability.

Ref: K. N. Leung, and P.K.T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency
compensation,” IEEE J. Solid-State Circuits, vol.38, no.10, pp.1691-1702, Oct. 2003.

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 Different Compensation Techniques
for Stability Purposes (4/4)
4. Pole-zero tracking frequency compensation
– To have pole-zero cancellation, the position of the output pole po and compensation zero zc
should match each other.
– The resistor is implemented using a transistor Mc in the linear region, where its value is
controlled by the gate terminal.

Ref: K. C. Kwok, P. K. T. Mok. “Pole-zero tracking frequency compensation for low dropout regulator,”
2002 IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 735-738,May 2002.

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 Fast Transient Response

- A current-efficient adaptively biased regulation scheme is implemented using a low-voltage high-

speed super current mirror. It does not require a compensation capacitor.
- The adaptively error amplifier drives a small transconductance (MA9) to modulate the output
current IOUT through a transient-enhanced super current mirror.

Ref: Yat Lei Lam, Wing-Hung Ki, “A 0.9V 0.35µm Adaptively Biased CMOS LDO Regulator with Fast Transient
Response,” 2008 IEEE International Solid-State Circuit Conference, February 2008.

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 Power Supply Rejection & Existing Solutions
Vsupply

 Problem:
 Low frequency and high frequency noise affects the operation of the highly sensitive circuits
 External noise is mainly coupled through the supply lines
 A regulator (LDO) is mandatory with high PSR
 Current Solutions:
 RC filtering: Larger drop-out voltage, and larger power consumption
 Cascading of LDO: Larger area, power consumption, larger drop-out voltage
 Combined RC filtering and cascading: Larger area and power consumption, larger drop-out
voltage and complexity
VIN VIN

VIN VVDD
IN

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 Enhancing PSR over a wide frequency range
- The NMOS cascode, MNC, shields the entire Proposed Topology
regulator from fluctuations in the power supply.
- MNC gate needs to be biased at a voltage
above the supply using a charge pump.
- MNC acts as a voltage follower for noise at its
gate, it is critical to shield the gate of MNC from
supply fluctuations using an RC filter to shunt
supply ripple to ground.
- With the help of an NMOS cascode, a charge
pump, a voltage reference and an RC filter to
shield the entire regulator from power supply
fluctuations, a 5mA LDO regulator utilizing 60pF
of on-chip capacitance achieves a worst-case
PSR performance of -27dB over 50MHz.

Ref: G. A. Rincon-Mora, V. Gupta, “A 5mA 0.6mA CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case
Power-Supply Rejection Using 60pF of On-Chip Capacitance ,” ISSCC, feb. 2007.
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 Stability Simulations

Stability test (Open Loop)

Frequency Response

AC signal is injected here - Open loop gain shows a low pass frequency response
- Loop Gain ~ 65dB; Fu ~ 10MHz; PM ~ 600

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 PSR Simulations

PSR test (Close Loop)

AC signal is injected here

PSR Vs. Frequency

- PSR curve shows a Quasi-Band Pass frequency response

- it is less than -40 dB up to 10KHz, -30 dB at 100 KHz

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 Noise in Linear Regulators
 LDO noise is sometimes confused with PSRR
- PSRR is the amount of ripple on the output coming from the ripple of the input.
- On the other hand, noise is purely a physical phenomenon that occurs with the transistors and
resistors (ideally, capacitors are noise free) on a very fundamental level.

 Primary noise sources:

1. Bandgap-Reference (Primary source of noise)
 Possible solution: add a low-pass filter (LPF) to the output of the bandgap.
– Drawback: it can slow down the output startup.
2. The resistor divider ( thermal noise = 4KTR )
 Possible solution: Use resistors as small as possible.
– Drawback: Smaller resistors burn more current through the feedback divider.
 Possible solution: add a capacitor across the top resistor in the resistor feedback
divider. At high frequencies it reduces the close loop gain and thus the noise.
– Drawback: it could slow down start-up time significantly, since the capacitor would
have to be charged by the current in the resistor divider.
3. Input stage of the error amplifier (thermal and flicker noise)
 Possible Solution: Large input drivers.
– Drawback: larger area.

 Second order noise sources:

- Load current and output capacitance (Phase Margin)
 Low phase margin will cause peaking in the close-loop gain and since the close-loop gain
amplifies this noise, the total output noise increases.

Ref: J. C. Teel, “Understanding noise in linear regulators” Analog Application Journal, 2Q 2005, www.ti.com/aaj
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 LDO Design Example

Conventional LDO
Parameters Specifications

VIN 3.5V

Error Amplifier VOUT 3.3V

ILoad 0mA-50mA
Pass Transistor
VREF
VOUT IQ < 100µA

Technology 0.5µm CMOS

R1
CL
RL

R2
RESR

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 Design Flow Diagram

Vin Vout ILoad

Vdropout RL

W/L Design Error Amplifier

CGate RDS Cp Rp RA

Calculate non dominant poles: PND1, PND2

Adjust poles and zeros locations using CL and RESR

Check stability

Check transient, PSR, load regulation, line regulation, …

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 Hand Calculation
W  W 
VDSSATPass     
1 2I D
ID   p Cox  2
2 L   L   p Cox  VDSSATPass 2
Since Vdropout ~ 200mV  VDSSATPass ≦ 200mV and assuming μpCox = 65μA/V2 .
 W/L = 38462.
In order to minimize the gate capacitance, we use minimum length L = 0.6μm
W = 38462 x 0.6 μm = 23 mm
The gate capacitance of the pass transistor is given by the following equation:
Cgate = CGS + (gmpRpar + 1)CGD
Where CGS = (2/3)WLCox ; CGD = WLDCox ; Rpar = Rds // (R1 + R2) // RL ; Rds = 1/(λIds)
The value of CGS and CGD can be also obtained if we run a DC simulation and verify the
operating point of the Pass transistor. Using the last method, we found:
Rds = 1/gds = 15Ω ; CGS = 20pF ; CGD = 4.5pF
R1 and R2 are calculated using VO = (1 + R2/R1)VREF
Assuming VREF = 1.2V and choosing R1 = 240KΩ  R2 = 420KΩ

RL = VO/Iload = 3.3V/50mA = 66Ω  Rpar = 15//(240K+420K)//66 = 12Ω .

W 
Gmp  2   p  Cox     iload  130e  6  38462 50e  3  500mA / V
L
 Cgate = 20pF + 7*4.5pF = 51.5pF
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 Error Amplifier (AEA) Design
Error Amplifier Design and Considerations:

- High DC Gain to gurantee high loop gain over the range of load ( AV > 60dB)
- Low output impedance for higher frequency pole created with CGS of Pass Transistor
- Internal poles must be kept at high frequencies, preferably > Fu of the system (~1MHz)
- Low DC current consumption
- Low Noise

R OUT

Dominant pole

Ao = gM1Ro1gM8Rout
GBW = gm8/2πCgate
Cgate

R01

Two stage amplifier without miller compensation

using 0.5μm CMOS technology

Notes:
1. CGATE is connected to output node.
2. Miller Compensation is not required since the dominant pole is at the output.

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 Error Amplifier Simulation Results

Magnitude Plot Phase Plot

Ao = 65dB; GBW = 7.6MHz; PM = 51o

Note: This results were obtained using Cgate = 51.5pF as the load

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 Conventional LDO: Modeling
Close Loop Schematic Open Loop Transfer Function: TF = H1 x H2 x H3 x H4
VIN

Error Amplifier g R  g m3 R A
PND1CGs H  m1 p
H2 
VREF PD
1
R C s 1
p p
R A CGS   AV  1CGD   s  1
C Rds

 g mp RPAR RESR C L   s  RPAR 

Vout
R2
PND2 H3  H4 
B CGD R1 CL
RPAR  RESR C L  s  1 R2  R1
A D RL
z 1
1EH Av  g mp  RPAR RPAR  Rds R1  R2 RL Rds 
1EF R2 RESR I ds
VTest
W 
g  2  C  i
L
mp p ox load
Loop Breaking Point for Stability Analysis

Open Loop Block Diagram RPAR : Output impedance.

RL : Load resistance.
RDS : Drain to Source impedance of the Pass transistor.
R1 & R2 : Feedback resistor.
VDSSATPass : VDSAT of the pass transistor.

Note: The error amplifier is a two-stage amplifier without miller compensation

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 Mathlab/Simulink Macromodel
Pass Transistor Dominant Pole / Compensation Zero
Transconductance

Non-dominat Pole
due to Pass Transistor
Gate Capacitance Error Amplifier
Nondominant Pole Feedback
Factor

Formulas and Component Values

K = R2/(R1 + R2) Gm1 = 15.62μA/V Gm3 = 2.45mA/V gmp = 500mA/V resr = 3Ω

R1 = 420KΩ Rp = 64kΩ Ra = 736KΩ Rpar = 12Ω Co = 10μF

R2 = 240KΩ Cp = 100fF Cgate = 20pF Cgd = 4.5pF

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 Pole/Zero Locations

PND 2
P
ND1
P
D

Dominant Pole Location Second non-dominant pole location

1
PD   1.1KHz PND 2 
1
 24.9MHz
2 RPAR  RESR CL 2R p C p

First non-dominant pole location Zero location

1
PND1 
1
 4.2 KHz Z  5.14 KHz
2RACGate 2RESRCL

Notes:
1- RA was obtained from simulations. Basically, it is the output resistance of the error amplifier.
2- PND2 is greater than 5MHz. This is good news since we want this pole to be located above
the gain bandwidth product of the overall system.
3- RESR equal 3 was chosen for stability reasons (see next slide)

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 Stability Vs. RESR

UGB versus RESR Phase margin versus RESR

Note: RESR was swept from 0 to 10

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 System Simulation Results
Magnitude Plot (IL=50mA) Phase Plot (IL=50mA)

Phase Margin = 55°

DC Gain = 74dB

UGB = 6.3MHz

Magnitude Plot (IL=100µA) Phase Plot (IL=100µA)

Phase Margin = 90°

DC Gain = 75dB

UGB = 172KHz

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 System Simulation Results (con’t)

VIN Step Plot IL Step Plot

V  3.30352V
V  3.30206V
2
4

V  3.30238V
3

V  3.30238V
1

V  V 1.17mV
Load Regulation = 2
 1
 0.0234V / A
I I
L2
50mA
L1

V V 313V
Line Regulation =
2
1
 0.0031V / V
I I
L2
100mV
L1

Notes:
1- VIN step from 3.4 to 3.5V
2- ILOAD step from 0 to 50mA

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System Simulation Results (con’t)

PSR versus Frequency

PSR @ 100KHz = -35dB

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Summary of the Results

Parameters Results
VIN 3.5V

VOUT 3.3V

ILoad_max 50mA
ILoad_min 0mA
IQ 30µA

PSRR@100KHz -35dB

Line Regulation 0.0031V/V

Load Regulation 0.0234V/A

TR 1µs

Technology 0.5µm CMOS

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 References
[1] G. A. Rincon-Mora, V. Gupta, “A 5mA 0.6mA CMOS miller-compensated LDO regulator with -27dB
worst-case power-supply rejection using 60pF of on-chip capacitance,” ISSCC, Feb. 2007.
[2] L.-G. Shen et al., “Design of low-voltage low-dropout regulator with wide-band high-PSR
characteristic,” International Conference on Solid-State and Integrated Circuit Technology, ICSICT,
Oct. 2006.
[3] R. J. Milliken, J. Silva-Martínez, and E. Sánchez-Sinencio, “Full on-chip CMOS low-dropout
voltage regulator,” IEEE Trans. on Circuits and Systems – I, pp 1879-1890, vol. 54, Issue 9, Sept.
2007.
[4] C. K. Chava, and J. Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,”
IEEE Trans. on Circuits and Systems – I, vol. 51, No.6, pp. 1041-1050, June 2004.
[5] K. N. Leung, and P.K.T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-
control frequency compensation,” IEEE J. Solid-State Circuits, vol.38, no.10, pp.1691-1702, Oct.
2003.
[6] K. C. Kwok, P. K. T. Mok., “Pole-zero tracking frequency compensation for low dropout regulator,”
2002 IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 735-738, May 2002.
[7] J. C. Teel, “Understanding noise in linear regulators,” Analog Application Journal, 2Q 2005,
www.ti.com/aaj
[8] K. N. Leung, P. K. T. Mok, and W. H. Ki, "A novel frequency compensation technique for low-voltage
low-dropout regulator," IEEE International Symposium on Circuits and Systems, vol. 5, May 1999.
[9] G. A. Rincon-Mora and P. A. Allen, "A low-voltage, low quiescent current, low drop-out regulator,"
IEEE J. Solid-State Circuits, vol.33, no.1, pp.36-44, Jan. 1998.

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