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This is ECE 511 for digital electronic syllabus for University Students Curriculum.
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SOLOMON CHINEDUCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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/ 15
BECE 379 : DESIGN oF DiciraL AND
2000/2001 WintER Sesst
«make library packages visible
¢ declare components in architectures ‘and packages
© declare constants
© instantiate components into an architecture
3 © declare std-logie, std logie.vector, thd cncluisicned eegtel:
declare enumerated types and subtypes of array types in architectures and packages
‘© declare and use entities with generics
= se conditional signal assignments
. comer berween std Jogi ettor, unsigned and integer types
© instantiate stave owas
M memories
lescription as a behavioral, structural, or dataflow (RTL) ai en
ne
We will also learn an aia ‘to logic design called Register Transfer Level (RTL) or foe ‘design. This is the
method curently used fr he design of complex logic circuits such as microprocessors.
You should be able to:
« select a sufficient set of registers and logio/arithmeftefimetions required to implement arvalgorithn
‘© convert the algorithm into a sequence of register transfers through logiclarithmetic functions:
‘© write synthesizeable VHDL RTL code to implement the algorithm ey
We also cover three topics related to the design of interfaces to logic circuits: metastability, input synclipnization
and glitches. You should be able to: identify eireuts where metastable behaviour is possible: compute the mean time
between metastable outputs: identify circuits that could fail due fo asynchronous inputs; add synchronizer flip-flops
10 reduce the probability ojmetastability; remove race conditions by registering inputs; and use registered outputs to
or it can be sub-system of your design,
Before we use a component, we first need to de-
clare it, A component declaration is very similar to
n nd Components an entity declaration — it defines the input and out-
pul signals, not the functionality. +
Jn order to avoid declaring each component in ev-
pear, Where it is used, we typically place
as in “packages.” A package
of component declarations
Packages are themselves ert attribute begin block bo
mponent configuration co
else elsif end entity e»
inertial inout Is label library linkage lit
‘map mod nand new next nor not null of 0
‘or others out package port postponed pro
port return rol ror select severity signal si
‘sla sll sra srl subtype then to transport typ¢
affected units until use variable wait when
with xnor xor
stored in “libraries’
Table 1: VHDL reserved words,
Poe
esol
aa)
In the Synopsys Design Compiler! and
Max+Plusil VHDL implementations, a library
is a directory and each package is a file in that
directory, The package file is a database containing
information about the components in the package
(dhe component inputs, outputs, types, etc).
To use a component in a design, we use Library
statements to specify the libraries to be searched and
a use statement for each package we need to use.
; ‘The two most commonly used libraries are called
it TERE and WORK.
; ‘The WORK library is always available without hav-
ing to use a library statement. In Design Compiler
the WORK library is a subdirectory of the current di-
_ teetory cilled WORK while in Max-+Plusil it is the
} i ee Project directory,
Library and use statements must be used before
tee) design unit (entity or architecture) that uses
those ee For example, if you wanted to use
yt: sien hall ow,
pu need not repeat the Library and se statement.
Greating Cone bam
‘A component declaration is similar to an entity dec-
aration and defines the input and output signals.
‘Component declarations can be placed in an ar~
chitecture before the begin, But it’s usually more
‘convenient to put component declarations within a
package declaration. When we compile (or “ana-
lyze”) the package declaration the information about
‘the components in the package is saved in a file in the
WORK library. The components in the packages can
then be used in an architecture (in that same file or in
other files) by using the appropriate use statements,
For example, the following code declares a pack-
age called £1ipflops. This package contains only
‘one component, rs, with inputs r and s and an out-
put g:
package €)tpelops ts
in bit jg; out Bit ) 5
end component
end flipflops +
Exercise 36: Ifthis code was slorod in a file called ££, vhs, how
‘many files would be created? What would they contain? Where
would they be placed?
Solaupnent Instantiation
z component has been declared, it can be used
{nan architecture. A component in-
tion describes how the component is “hooked -parity-check circuit using component instantiation.
‘This type of description is called structural VHDL.
because we are defining the structure rather than the
behaviour of the circuit.
Inthis case we have put the component declaration
‘nto the file nypackage vd. The xor_pkg contains
the xor2 component (although a typical package de-
fines more than one component):
+ datine on 1082 conan Sa a pacage
‘package 2or_pig is #
‘component x0r2 : ee
pore (a, bs in bit; x: out bit);
fend componeat |
andwor ps
‘A second file, parity.vhd, describes the parity
‘entity that uses the xor2 component:
s+ parity function built fron xor gates
lute vork.xor_pkg.el2
entity parity is
port (a,b, eds in Bit; p: owe bel:
end parity +
srchitectuve rel of parity 16.
lage
signal x,
begin
xor2 port map ( a)
xor2 port mp (c, x) ¥
wo? port map (8, ¥, P
fend tl
resulting top-level schematic for the parity en-
ibd the connections within he party generator
{Ihe signal names used In the architecture.
‘parity.vhd file is analyzed (com-
izer will search the (WORK) direc-
parity.vhd).
‘Although components don’t necessarily have tobe
created using VHDL, we could have done so by us-
ing the following entity/architecture pair infile called =
xor2.vhd:
o> nor gate
entity xor? is
port (a,b: in bit; x:
end x08?
out bit)
architecture rtl of xor? is
begin
ker axor by
end rel
VHDL versus C Terminology
‘The following comparison shows some rough equiy-
alents between the VHDL concepts described above
and C programming?,
VHDL [C
analyze | compile
elaborate | link
‘component | fiction
instantiate | call
use #include
package | DLL
library directory
std logic Packages
‘The IEEE library contains two useful packages.
‘These packages define altematives to the bit and
bit_vector types for logic design.
The first package, std_logic_1164, de-
fines the types std logic (similar to bit) and
std_logic_vector (similar to bit_vector). The
advantage of the std_logic types is that they can
have values other than ’0’ and "1". For example, an
‘std_logic signal can also have undefined (’X") and
high-impedance values (’Z’). The std_logic_116¢
package also redefines (“overloads”) the standard
he effect of a cal is rather different than a component in-
stantiation: in VDL we gét an extra copy of the component
teach time itis used, In C we get only one copy of a function no
‘matter how many times itis called.
qyoula then be recreated every time we analyzed boolean operators (and, or, not, etc.) so that they.
work with std logic signals. f ‘i
The second package, st@_logic_arith defines
the types signed and unsigned. ‘These are sub-
types of std_logic_vector with overloaded oper-
ators that allow them to be used both as vectors Of 0
logic values and as as binary numbers (in signed
‘two's complement or unsigned representations), The
hierarchy of these logic types could be drawn as fol-
lows:
The standard arithmetic operators (+, -, *, /, **,
>» S <=, >=) =, /=) can be applied to signals of type
signed or unsigned. Note that it may not be practi-
cal or possible to synthesize complex operators such
as multiplication, division or exponentiation.
For example, we could generate the combinational
logic to build a 4-bit adder using the following archi-
tecture:
Libeary eee
‘use Lee. ctd_logic 1364. all
ene a
«J so that you can use the same func-
Beene ‘with more than one type, in many cases
‘you will need to use type conversion functions.
The following type conversion functions are found
in the the std_logic_1164 package in the ieee T=
brary:
function,
to bitvector (x)
to.stdlogicvector (x)
‘The abbreviations bv, 1v, un and in are used for
bit vector, std logic vector, unsigned and
integer respectively.
‘The following type conversion functions are found
in the the std_logic_arith package in the ieee li-
brary.
from | to | function
W | un | unsigned (=)
un | lv | std togic-vector (x)
un | in | conv_integer (x)
in | un | conv-amsigned (x, 1en)
in | Iv | conv.sté.logic-vector (x, len)
in the stdlogic_arith package
of the arithmetic and comparison
=) so that they take integer as well
ing an integer you must
iber of bits in the result
It’s often useful to make
We can do this in VHDL by.
The most common uses for
to create signals of given
to declare types that can only
possible values (called enumeration
‘Type declarations are often pl
to make them available to multiple
The following example shows a
dsp_types that declares two new types:
package dep types 48
type woue se (olov, medium, fast);
(Gs éouco 0)
Note that we need to use a subtype declaration in
the second example because the std_logic_vector
type is already defined.
Exercise $9: Wite 0 dociaraton for a signal that cont
whether the value in register should be loaded, incremented,
decremented, or held. Write the declaration for an &-bit signal
‘ype called byte
Generics
‘An entity can be declared with a bus or resister size
that is left undefined until the component is used
(“instantiated”) by adding a generic clause in its en-
tity and component declarations, For example, a reg-
ister with negated outputs could be declared in the
file nregister.vhd as:
eter with negated output
entity aregister is
(generic ( width: dot
fore (ds im bit vector (wideh-1 dowmto 0)
Gf out bit rvector (videhe1 dowste ©) 3
elk: in bit)
fend nregiater ;
architecture
eignal twp : 5)
vector widtb-1 dowmto 0) 4
begin
HE clk'event and elke!2" then
tp eds ‘you might declare the nregister component in a besin
package as: “9
“t00" ven bla) « ‘1° else
*o1a* wen B(2) = "2° else
BI ie Sti hen BOD) = 1! ae
ee seat es 30) = else
generic ( width : integer ) ; nd ve i
port (@: in bit_vector (width-1 downto 0] ; pa
Pm TG oat bitivector (widths dowto 0)
elk : in iti ii
a Be bit 5 Note that the conditions are tested in the
a they appear in the statement and only the
use vork.registers.al j
‘i: nregister
‘generic mp ( 8)
gement that models 2-
@ an array x as the input, signal sel 1°
| signal y 2s the output, Repeat for a 410-1
Sow an aay).
® of selected or conditional assignments
= logic that is generated, A conditional
es an ordered sequence of two-way
‘results in the multiplexer tree as
‘selected assignment implies a logic
es all possible inputs simultane-
implies a single-stage sum-of-products
circuit. The circuit generated by a se-
‘will typically require less logic but
er propagation delay.
Togic synthesizer may need 10 opti-
‘cirouit to meet either speed or space
final circuit may not match either of ‘TriState Buses
‘output can be set to high and low logic lev-
‘95 well as to a third state: high-impedance (‘2’).
This type of output is used where different devices’
‘outputs are connected together and drive a common
bus (hopefully at different times!). To specify that an
output should be set to the high-impedance state, we
use a signal of type std_logic and assign it a value
of 2".
‘The following example shows an implementation
of a 4-bit buffer with an enable output, When the
enable is not asserted the output isin high-impedance
mode :
Library ieee :
‘wap ieee.ct4 logic 1366/a11
architecture rel of thuf is
begin
ae
@ ven en = ‘1' else
sanz"
Memory Models
VHDL also allows the use of arrays with signal in-
dices to model random-access memory (RAM). The
following example demonstrates the use of VHDL.
arrays as well as bi-directional buses. We must use
the type-conversion function conv_integer because
the address input, a, is of type unsigned while the
array index must be of type integer.
Library ieee
tute Leee.std log!
use ieee etd logic_arith.all
van Le port (
= nindivectional data signal
@ + inout std logic vector (7 domto 9}
dress input
a: dn uneigned (2 downto 0)
TU" gutput enable and write strobe (clock)
oe, we: in atdlogic ) ;
end Fam j
architecture rel of ran ts
‘eubtype byte 49 etd logic vector (7 dowmto 0) ;
type byte_array is array [0 to 3) of byte 7
signal van : byte array
begin
=" output value de the indexed exray element
ae
‘Fan(cony_integer (al) when oF
saazaazea®
a else
+ register the indexed array element
process (wr)
Begin
yan(cony_integer(a)) <+
end if
end process
end rel
fythe design above to create a 18-cloment,4- For many implementation technologies (FPGAs,
gate arrays, or standard-cell ASICs) there are usu-
ally vendor-specific ways of implementing memory
arrays that give better results. However, using a
VHDL-only model with “random logic” as shown
above is more portable and may be practical for small
‘memories such as CPU “register files
Exercise 42: Why is portability desirable?
¥ Design Strategies
There are a number of strategies that are useful when
designing complex logic circuits. You may recognize
similar strategies that are used in computer program-
ming.
‘One y is to design at the most abstract
highest”) level possible with the tools available.
For example, using a behavioral design style with
VHDL instead of a structural style (e.g. schemat-
‘cs) will make it easier to write, read, document, and
ji
ae
debug your design.
Another design strategy is hierarchical deci;
sition. The device being designed should be
composed into a nuniber.of modules (represented =.
VHDL entities) that interface through well-definc.
interfaces (VHDL ports). The internal structure of
these modules should not be visible from outside the
module, Each of these modules should then be fur-
ther subdivided into other modules. The decomposi-
tion process should be repeated until the remaining
modules are simple enough to be easily written and
tested. This decomposition makes it easy to test the
‘modules individually, allows modules to be re-used
‘and allows more than one person to work on the same
project at the same time.
It's also a good idea to keep the design as portable
‘as possible. Avoid using language features that are
specific to a particular manufacturer or target tech-
nology unless they are necessary to meet other re-
quirements. This will make it possible to use dif-
ferent manufacturing processes and different devices
‘ith a minimum of redesign.
Structural Design
Structural design is the oldest digital logic design
method. In this method the designer does all the
work. The designer selecis the low-level components
and decides exactly how they are to be connected.
‘The parity generator described previously is an ex-
ample of structural design,
A structural design can be represented as a parts
list and a list ofthe ons between the pins on
the components (for example: “pin 12 on chip 3 is
connected fo pin 5 on chip 7”). This representation
of a circuit is called a netlist.
Schematic capture is the most common structural
design method. ‘The designer works with a program
similar toa drawing program that allows components
0 be inserted into the design and connected to other
‘components.
Exercise 4%: What would be the most common type of stato
meat in stetual VHDL description? Asa simple example, consider a device that needs
to add four numbers. In VHDL, given signals of the
correct type, we can simply write:
conceming itself about implementation de-
Thus a behavioral design may include opera-
s such as integer division or behaviour such as This particular description is simple enough that
opagation delays that are difficult or impossible to it ean be synthesized. However, the resulting eireuit
thesize. will be a fairly large combinational circuit eompris-
However, every design should start with a behav- ing three adder circuits as follows:
{oral description. The behavioral description can be
“simulated and used to verify that all of the required
aspects of the design have been identified. The out-
pit of a behavioral description can be compared to
" the output of structural or RTL description to check
perl (arb)selsay
bape
gatas
Exercise 44; A VHDL description contains non-synthesizoable
onstrucs such 8s propagation delays, st a behavioural or
ul 'A behavioral description, not being concemed
‘the sequence of trans- ith implementation details, would be eomplete at
-does not describe the hig point.
However, if we were concerned about the cost of
(1) determine the {he implementation we might decide to break down
needed to hold the he computation into a sequence of steps, each one
involving only a single addition:
‘where each operation is executed sequentially. The
Jogic required is now one adder, a register to hold
the value of ¢ in-between operations, @ multiplexer
to select the input to be added, and a circuit to clear
s at the start of the computation.
"Although this approach only needs one adder, the
procéss requires more steps and will ake longer. Cit
that divide up a computation into a sequence
‘operations are quite common
is called Register ‘Transfer An RTL design is composed of (1) registers and
combinational function blocks (e.g. adders and mul-
tiplexers) called the datapath and (2) a finite state
machine, called the controller that controls the trans-
fer of data through the function blocks and bi
the registers, (
1h VHDL RTL design the gate-level design
‘optimization of the datapath (registers, ‘multiplexers,
and combinational functions) is done by the synthe-
sizer. However, the designer must design the state
‘machine and decide which register transfers are per-
formed in which state,
The RTL designer can trade off datapath complex-
ity (@., using more adders and thus using more chip
area) against speed (e.g. having more adders means
fewer steps are required to obtain the result). RTL.
design is well suited for the design of CPUs and
special-purpose processors such as disk drive con-
ttollers, video display cards, network adapter car
tc, It gives the designer great flexibility in choosing
between processing speed and circuit complexity,
RTL Design Example
design is described in
ts involved, we will
This design will also demon
ages of components that can
of the register, or the sum of the
register and one of the four inputs. It includes one
8-bit register, an 8-bit adder and a multiplexer that
selects one of the four possible inputs as the value to
be added to the current value of the register. {sto the datapath from the controller are
lector for the multiplexer and two control
oad or clear (set to 0) the register.
Gum : out nun;
gel ; in std logic vector (1 downto 0) i
Mead, clear, clk : in std logic
vi
fend gatapeth :
“aromcecace sof arapch ts
aeeeoganees
ee es ns an
lane sno ra‘Sength)
input is an update signal that tells our
compute the sum (presumably because one OF More
of the inputs has changed), Te
This particular state machine sits at the shold”
state until the update signal is true. It then sequences
through the other five states and then stops atthe hold fe 78
state again. The other five states are used to clear the
register and to add the four inputs to the current ‘value
of the register.
++ controller
Library eee
tune dee. etd logic 1164.01) 1
‘ane work averager_types.22
‘entity controller is
‘port |
ee) dp std_togte +
et; ove ota losis vector (2 downto 0) 7
Youd, elear + out até Logie 1 Z
clk + in td togic
a 4 ,
nd ebaesoller + 4
arohiveceace ret of cogeesilar $8
Tignal ay holdan, 3 ( stabO 4 7
tel tap 7 aed lapse vector (2 downto 0) 3
an ee
c+ select next stare
sith a select 5 <=
‘adda when lx,
ada when ada,
sade when ada-b,
eda wien acdc, eye
hoa ven ada ;
Ipelang ven oxhere } -~ bold
ne next state 4f in hold state 7
holeas <= 4
(ele when update = '1' else ;
holds y
|= tate regioter
‘proces ell)
begin
HE gi evene and clk = "1" then
ent st 5
fend process +
= controller outputs
with e select sel <=
00" when add
sou" when aad}
noe wien acdc)
sit when others |
then @ « clz ox ¢ = held else ‘2
lane 36 wana he ae 0" + The next section of code is an example of how the
datapath and the controller entities can be placed in
a package, averager_components, as components,
In practice the datapath and controller component
declarations would probably have been placed in the
top-level architecture since they are not likely tobe
re-used in other designs, i
+ package for datapath and controller :
brary dete ;
‘use ieee.std logic a64.atb ;
‘se work. averager types.all ;
‘Package averager_cooponents is
component datapath,
ort (
a,b, 6, @ 5 Sn mum;
um + ett mom;
gel : An std logic vector (1 dowmto 0)
oad, clear,
ve
‘The result ofthe synthesizing the dats
PT Ten It is that each datapath register loads the description. The compiler does this
s* computed” uring one state at the end of that allocating registers and partitioning the
s(which is then the start of the computation for over as many clock cycles as are requl
uext state), high-level processing time requirer
@ can guarantee that the correct results will be
into registers if the longest propagation de- i
(pp) through any path through the combinational Metastability
that lies between register outputs and inputs is
than the clock period (fgjock) minus the regis-
» setup time (t,) and clock-to-output (tco) delays: The proper operation of a clocked flip-flop depends
‘on the input being stable for a certain potiod of time:
he before (the setup time) and after (the Hold time) the
ete roe clock edge. If the setup and hold time requirements
Be ee J earn are met, the correct output will appear at a valid
BN hd otc output level (between Vox and Vou) atthe Aip-lop
be ‘output after a maximum delay of tco (the clock-to-
ge non emma Wl output delay), However, if these setup and hold time
requirements are not met then the output of the flip
flop may take much longer than teo to reach a valid
logic level. This is called metastable behaviour or
metastability. /
‘An invalid logic level at the output of the flip-flop
may be interpreted by some logic gates as a1” and
wwe only need to com- by others as a *0°. This leads to unpredictable and
pinational logic blocks ysyally incorrect behaviour of the circuit.
hhaving to predict the Ip the synchronous circuits we have studied thus
cn clock signals. This far we have been able to prevent metastabilily by
Aigital cireuits are S¥7- clocking all flip-flops from the same clock and ensur-
© ing that the maximum propagation delay of any com-
binational logic path is less than the clock period mi-
nus the flip-flop setup time and clock-to-output de-
lay.
However, when inputs to a synchronous circuit are
not synchronized to the clock, it is impossible to en
sure that the setup and hold times will be met. This
‘will eventually lead to the incorrect behaviour of the
device. It is important to realize that all practical
logic circuits will eventually fail due to metastabil-
ity, However, the designer should try to ensure that
these failures happen very infrequently (e.g. once per
10° or 10° years of operation) so that other causes of
__ failure predominate.
Introduction
*p
