Genus - Tips and Tricks on MBIT

Genus – 19.10
October, 2019
Copyright Statement
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Cadence Design Systems, Inc. All others are the property of their respective holders.

This application note contains content that are being provided to assist Cadence licensed users adopt some tips and tricks on Mbit
designs using Genus, and they are the proprietary and confidential information of Cadence or its licensors, and are supplied subject to,
and may be used only by Cadence’s customer in accordance with a previously executed agreement between Cadence and that
customer.

"ALL MATERIALS FURNISHED BY CADENCE HEREUNDER ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, AND
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MERCHANTABILITY. CADENCE SHALL NOT BE LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF
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HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY, CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR
OTHERWISE."

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Disclaimer

• This application note introduces some hidden commands

and attributes.

• Although they are safe at the time this document is written

they are :
– Not documented
– Not officially supported
– Subject to change with no notice

• If you feel one of these hidden should be productized,

contact Cadence through a Case.

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Agenda
Introduction

Power reduction
•why is MBIT helping ?

MBIT cell
•Types
updated
•How do I locate them in Genus ?

MBCI Mapping Flows Updated for

•Automated flow
•Standalone flow Genus 18.1x and
•ISO/LS cells merging
some info about
NEW
Preventing cells from being merged
19.1 too.
Driving mapping with labels NEW

« Manual » mapping NEW

CUI version
MBIT cells naming updated

Reporting updated

Other good attributes / options updated

Clock Gating Considerations updated

Things to be aware of updated

Conformal LEC impact updated

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Introduction

• From past months/years, focus is not anymore only on

timing
– Power reduction becomes a requirement and is a challenge

• By putting several cells in an abstract and sharing some of

the driving logic we can reduce
– Overall power dissipation
– Area

• Cadence tools do support MBIT flow for while (several years

for RC/Genus)

• We’ll be discussing how to use MBIT features and possibly

increase the coverage
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Power Reduction

• As seen on various previous presentations, a fair amount of

power dissipation is in the clock tree

• Power is impacted by
1. The number of clock tree components
2. The power supply voltage
3. The frequency (Toggle Rate)
4. The capacitance (dynP=1/2(CxV²xTR))

=> to preserve good performance, we cannot change too much voltage

and frequency

=> reducing the number of clock tree components and the clock tree
capacitance is a good option

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Why is MBIT helping ?

• MBIT cells have 2 or more cells in one abstract

• For a similar external clock pin capacitance, the cell clock
port drives internally more than one DFF, reducing the
number of sinks for the clock tree

less power sinks => less clock tree elements => less power

single bit version multi-bit version

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MBIT cells in Genus

• In Genus there are three main types of MBIT cells

– Sequential (DFF (including retention) + LATCH)
– Combo
– ISO/LS

• Combo type contains cells like AND/NAND/OR...

• Pure Combo cells merging (AND/OR/MUX…) were far less

used until now, as the benefit was not obvious (no clock tree
considertion here), but we do see more interest for it lately,
and begin to see more libraries with such MB cells.
– They may be interesting for area purposes

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MBIT cells in Genus
How to locate the MBIT elements

• MBIT cells have a bit_width attribute > 1

• Few ways to get the libcells:
– All 2 bit libcells
get_db lib_cells -if {.bit_width == 2 && !.timing_model}

– All MBIT libcells

get_db lib_cells -if {.bit_width > 1 && !.timing_model}

– All MBIT DFFs

get_db lib_cells -if {(.bit_width > 1) && .is_flop && !.timing_model}

• To retrieve the MBIT instances

– All MBIT DFFs
get_db insts -if {(.lib_cell.bit_width > 1) && .is_flop && !.lib_cell.timing_model}

Note: the test on timing_model is to exclude cells like synchronizers from the list

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MBIT cells in Genus
How to locate the cells (Cont.)

• Other way with report. Will give more information at once

report_multibit_inferencing -lib [-no_header]
legacy_genus:/> report_multibit_inferencing -lib -no_header

Library : Combinational Multibit Libcells info

=======================================================================================================================================================================

Comb_Mbit libcell Avoid Bitwidth Leakage Power Area Library Library Domain
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
A2LVLUW2_X1N_A9PP96CTUL_C18 false 2 518.49 4.53 sc9mcpp96c_cln16fcll001_pmk_ulvt_c18_ssgnp_cworstccworstt_max_0p72v_0p72v_0c timing
A2LVLUW2_X2N_A9PP96CTUL_C18 false 2 616.36 4.64 sc9mcpp96c_cln16fcll001_pmk_ulvt_c18_ssgnp_cworstccworstt_max_0p72v_0p72v_0c timing
A2LVLUW2_X4N_A9PP96CTUL_C18 false 2 811.94 4.87 sc9mcpp96c_cln16fcll001_pmk_ulvt_c18_ssgnp_cworstccworstt_max_0p72v_0p72v_0c timing
A2LVLUW2_X8N_A9PP96CTUL_C18 false 2 1205.41 5.31 sc9mcpp96c_cln16fcll001_pmk_ulvt_c18_ssgnp_cworstccworstt_max_0p72v_0p72v_0c timing
A2LVLUW4_X1N_A9PP96CTUL_C18 false 4 958.49 6.41 sc9mcpp96c_cln16fcll001_pmk_ulvt_c18_ssgnp_cworstccworstt_max_0p72v_0p72v_0c timing
A2LVLUW4_X2N_A9PP96CTUL_C18 false 4 1162.24 6.64 sc9mcpp96c_cln16fcll001_pmk_ulvt_c18_ssgnp_cworstccworstt_max_0p72v_0p72v_0c timing
A2LVLUW4_X4N_A9PP96CTUL_C18 false 4 1569.97 7.08 sc9mcpp96c_cln16fcll001_pmk_ulvt_c18_ssgnp_cworstccworstt_max_0p72v_0p72v_0c timing
A2LVLUW4_X8N_A9PP96CTUL_C18 false 4 2433.02 7.96 sc9mcpp96c_cln16fcll001_pmk_ulvt_c18_ssgnp_cworstccworstt_max_0p72v_0p72v_0c timing
LVLUW2_X1N_A9PP96CTUL_C18 false 2 536.80 4.31 sc9mcpp96c_cln16fcll001_pmk_ulvt_c18_ssgnp_cworstccworstt_max_0p72v_0p72v_0c timing
[...]

Library : Sequential Multibit Libcells info

=======================================================================================================================================================================================

Seq_Mbit libcell Avoid Multibit_Usable Bitwidth Leakage Power Area Library Library Domain
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DFFQA2W_X1N_A9PP96CTUL_C16 true true 2 356.89 1.60 sc9mcpp96c_cln16fcll001_hpk_ulvt_c16_ssgnp_cworstccworstt_max_0p72v_0c timing
DFFQA2W_X2N_A9PP96CTUL_C16 true true 2 582.42 1.71 sc9mcpp96c_cln16fcll001_hpk_ulvt_c16_ssgnp_cworstccworstt_max_0p72v_0c timing
DFFQA4W_X1N_A9PP96CTUL_C16 true true 4 716.09 3.10 sc9mcpp96c_cln16fcll001_hpk_ulvt_c16_ssgnp_cworstccworstt_max_0p72v_0c timing
DFFQA4W_X2N_A9PP96CTUL_C16 true true 4 1084.77 3.26 sc9mcpp96c_cln16fcll001_hpk_ulvt_c16_ssgnp_cworstccworstt_max_0p72v_0c timing
DFFQL2W_X1N_A9PP96CTUL_C20 false true 2 178.41 1.71 sc9mcpp96c_cln16fcll001_hpk_ulvt_c20_ssgnp_cworstccworstt_max_0p72v_0c timing
DFFQL2W_X2N_A9PP96CTUL_C20 false true 2 263.85 1.82 sc9mcpp96c_cln16fcll001_hpk_ulvt_c20_ssgnp_cworstccworstt_max_0p72v_0c timing
DFFQL4W_X1N_A9PP96CTUL_C20 true true 4 359.63 3.15 sc9mcpp96c_cln16fcll001_hpk_ulvt_c20_ssgnp_cworstccworstt_max_0p72v_0c timing
[...]

• If some cells are missing, check the .lib is correctly written.

– Pay attention to the testcell part as well, which must be MBIT too
– It’ll anyway provide information about the cell type (parallel or serial scan
types)
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 MBCI Mapping Flows

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Automated Mapping flow
• To enable MBIT merging, set this attribute
set_db use_multibit_cells true

• MBIT Seq merging is run at the end of syn_map

– It is also run again in syn_opt, unless you reset the use_multibit_cells
attribute to false before starting syn_opt

Note : In syn_opt -spatial, merging may not be done as much as with

other syn_opt flavors. Should this be the case, set this attribute and
see if you get better coverage / results

set_db spatial_multibit_merge true

This may evolve in the future

• MBIT Combo/Iso-ls merging is run during syn_opt

– Applies to iso/ls and other combo cells (inv, and, or, mux etc.)

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Automated Mapping flow (Cont.)

• Physical aware replacement

– If you run syn_map -physical the sequential cells merging is physical
aware and uses the generic placement for the replacement

– If you run syn_opt -physical or syn_opt -spatial the combo/iso-ls cells

merging is physical aware and uses the placement for the
replacement

NOTE: logical replacement will be done if the design is not placed or if

the design is placed but the command merge_to_multibit_cell –logical is
used

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Standalone Flow

• To run standalone MBIT merging, still set this attribute

set_db use_multibit_cells true

• Then use the following command

merge_to_multibit_cells [[-sequential] [-combinational] [-iso_ls] | -all]
[-logical] [-single_thread] [design]

-sequential | -combinational | -iso_ls specifies the type to merge

-logical will ignore placement data
-single_thread will not spread on different CPUs

– This command runs pretty fast

– It may be used to further improve the coverage
– It can be used anywhere in the flow, as long as the design is mapped.
(in most cases post syn_map)

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More on the flow …

• Sequential / combo / Iso-Ls replacement is driven by these

attributes
use_multibit_seq_and_tristate_cells (default false)
use_multibit_combo_cells (default false)
use_multibit_iso_cells (default false)

=> When you set use_multibit_cells true, they are all set to true, then
you can set some back to false to prevent merging
=> So you can select the type of cells you’d like the tool to merge

• Example : to map only SEQ and ISO/LS

set_db use_multibit_cells true (effectively sets the 3 attributes to true)
set_db use_multibit_combo_cells false (excludes “regular“ combo)

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MBIT cells splitting

• MBIT SEQ are merged part of syn_map

• Later, during syn_opt, this may be necessary to undo this,

and Genus may split timing critical MBIT DFFs to MB DFFs
of smaller bit width

• If MB FFs are connected in scan chains then MB FFs would

be split only if the scan chains connections were made by
Genus and not done by 3rd party DFT tools, and the
following attribute is set (19.10) :
set_db split_scan_chain_multibit_flop true (Default : false)

• Only DFF may be split

– Combo / Iso-Ls split is currently not supported
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Flows : recap

• Current automated flow (17.1+)

read libs/RTL

elaborate - read constraints

syn_generic (-physical)

MBIT attributes
• set_db use_multibit_cells true
•…

syn_map (-physical)
• SEQ MBIT instances are present after syn_map

syn_opt (-physical)
• The tool will further try to merge to SEQ MBIT cells during this step No split on
• The tool may split some SEQ MBIT cells to improve performance combo/ISO
• MBIT cells (inv, and, mux, etc.) and iso-ls are mapped during syn_opt

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ISO/LS cells merging

• Isolation cells / Level shifter cells are merged when

use_multibit_iso_cells is set to true, during syn_opt

– You can trigger a standalone merge by using this command which

can be run as soon as the design is mapped (so after syn_map)
merge_to_multibit_cells -iso_ls

• Other attribute of interest for more ISO/LS merging

set_db force_merge_isos_into_multibit_cells true (hidden)

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Flows : recap with ISO mapping

• Current flow
read libs/RTL

elaborate - read constraints

syn_generic (-physical)

MBIT attributes
• set_db use_multibit_cells true
• set_db force_merge_isos_into_multibit_cells true (optional, attempts more merge)
• …

syn_map (-physical)
• SEQ MBIT libcells used after syn_map

merge_to_multibit_cells (for standalone replacement, otherwise done in syn_opt)

syn_opt (-physical)
• The tool will further try to merge to SEQ MBIT cells during this step No split on
• The tool may split some SEQ MBIT cells to improve performance combo/ISO
• MBIT cells (inv, and, mux, etc.) and iso-ls are mapped during syn_opt

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 Preventing cells from being merged

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Preventing cells from being merged

• Use preserve or dont_merge_multibit attributes

dont_merge_multibit {false | true}

Read-write inst attribute. Controls whether the instance should be avoided during multibit
merging.
As shown in the following table, the tool only avoids multibit merging for the instance when
the merge_multibit for this instance is not set.

Tool behavior based on the value of the attributes

dont_merge_multibit merge_multibit Multibit merging is
false false attempted if use_multibit_cells is set to true.
false true attempted.
true false not attempted.
true true attempted. dont_merge_multibit attribute is ignored.

Note: This attribute applies only to sequential and tristate instances. For combo cells, you
may use the dont_touch attribute instead.

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 Driving mapping with labels

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Driving mapping with labels

• The attribute map_to_multibit_bank_label defines a bank

label for a sequential instance.
• Instances with the same label can be considered for multibit
mapping to the same bank of multibit instance.
– If several instances have the same bank label and the same
map_to_multibit_register attribute value, those instances will be
considered to be mapped to the same bank of the multibit cells
specified by the map_to_multibit_register attribute.
– If this attribute is set on a flop but no value is given to the
map_to_multibit_register attribute, the flop is considered for regular
multibit cell inferencing.

• Example
set_db [get_db insts *collar_reg*] .map_to_multibit_bank_label collarRegs

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 « Manual » mapping

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Manual mapping
create_multibit_cells

• The hidden command create_multibit_cells replaces the

list of given 1-bit cells with n-bit cells
Important: only applies to DFF and Latches

• This may be used when you want to completely control the

process

create_multibit_cells [-force] [-skip_ordering] [-name_based_sorting] -instances <string>

[-force]: specifies that the multibit cell must be accepted
[-skip_ordering]: skips sorting of 1-bit cells. Sorting is based on cell type, drive etc.
[-name_based_sorting]: name based sorting of 1-bit cells
-instances <string>: list of libcells and single bit instances

See the usage on next slides

Important: do not mix up with the create_multibit_cell (no ‘s’) command which has a
different use model and is less generic. So prefer the one with the ‘s’ at the end.
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Manual mapping
create_multibit_cells

• Usage
-instances takes a string like below
create_multibit_cells -force –instances "{{sublist1} {sublist2} … {sublistn}}"

with sublists built like this :

– One libcell only. Use it if functionality is correct, even if QOR impact
{{libcell1} {DFF1 DFF2 DFF3 DFF4}}

– Uses the best libcell among the list if it is functionality correct

{{libcell1 libcell2} {DFF1 DFF2 DFF3 DFF4}}

– Chooses the best libcell among the ones available in the loaded libraries
{{} {DFF1 DFF2 DFF3 DFF4}}

Remarks
1. Please note both the “ and the {} are very important and above format should be followed, as this
is very customized command
2. The list of single bit instances should belong to same module.
3. This command runs in single thread. Its runtime will not be on par with parallel mbci.
4. You may use some commands / expression in the list elements
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Manual mapping If physical data is
create_multibit_cells available, the merge is
physical aware

• Some examples
– Put these 4 instances in a 2B-DFF
create_multibit_cells \
-instances “{{{DFF2W} {{inst:out_reg7} {inst:out_reg2} \
{inst:out_reg1} {inst:out_reg12}}}}”

– Put these 4 instances in a 4B-DFF, in that order

create_multibit_cells -skip_ordering \
-instances “{{{DFF4W} {{inst:out_reg7} {inst:out_reg2} \
{inst:out_reg1} {inst:out_reg12}}}}”

– Force all these instances in 2B and 4B-DFF (even if it degrades QoR)

create_multibit_cells -force \
-instances "{{{DFF2W DFF4W} {[get_db insts *out_reg*]}}}“

– Put all these instances in any MB you can find in the loaded libs
create_multibit_cells \
-instances "{{{} {[get_db insts *out_reg*]}}}“

– Put all these instances in any MB cells named DFFSPE*W*

create_multibit_cells \
-instances "{{{DFFSPE*W*} {[get_db insts *out_reg*]}}}"

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 MBIT cells naming

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MBIT cells naming

• MBIT cell naming is driven by the following attributes

multibit_seqs_instance_naming_style [concat|auto|short];#default concat
multibit_seqs_name_concat_string <string> ;#default “_MB_”
multibit_short_prefix_string <string> ;#default “CDN_CPX_”

given 2 registers u1_o_reg[1] and u1_o_reg[2]

• multibit_seqs_instance_naming_style concat
CDN_MBIT_u1_o_reg[1]_MB_u1_o_reg[2]

• multibit_seqs_instance_naming_style auto n:m = bits from n to m

n_m = bits n and m
CDN_MBIT_u1_o_reg[1:2]

• multibit_seqs_instance_naming_style short
CDN_MBIT_u1_o_reg_CDN_CPX_[1]_MB_[2]

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MBIT cells naming Only for
multibit_seqs_instance_naming_style = auto
(19.10)
• New naming enhancement for auto naming style
mbci_use_common_substr_naming
Example if we have 4 instances with below names
top_hierA_hierB_hierD_q_reg[1]
top_hierA_hierB_hierD_q_reg[4]
top_hierA_hierB_hierC[0]_q_reg[0]
top_hierA_hierB_hierC[0]_q_reg[2]

By default, with multibit_seqs_instance_naming_style = auto the mbci name will be :

CDN_MBIT_top_hierA_hierB_hierD_q_reg[1_4]_MB_top_hierA_hierB_hierC[0]_q_reg[0_2]

hierA_hierB is common in all the 4 instances.

By setting this attribute It will be present in the name only once as prefix:
CDN_MBIT_top_hierA_hierB_hierD_q_reg[1_4]_MB_hierC[0]_q_reg[0_2]

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 Reporting

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 MBIT merging reporting

• Use report_multibit_inferencing to get a status of your

coverage
report_multibit_inferencing
Sequential Multibit cells usage statistics
=============================================================================================================================

Merged Not Merged Multibit Conversion %

-----------------------------------------------------------------------------
All Sequentials 177756 15481 91.99
-FlipFlops 177756 15440 92.01
-Latches 0 41 0.00
------------------------------------------------------------------------------

Seq_Mbit libcell Bitwidth Count Total Area Multibit Conversion % Library

-----------------------------------------------------------------------------------------------------------------------------
SDFFQNL2W_X1N_A9PP96CTUL_C20 (F) 2 15689 35569.10 16.24 ulvt_ssgnp_cworstccworstt_max_0p72v_0c
SDFFRPQL2W_X1N_A9PP96CTUL_C20 (F) 2 6598 17512.46 6.83 ulvt_ssgnp_cworstccworstt_max_0p72v_0c
SDFFSQL2W_X1N_A9PP96CTUL_C20 (F) 2 408 1082.92 0.42 ulvt_ssgnp_cworstccworstt_max_0p72v_0c
SDFFQNL2W_X2N_A9PP96CTUL_C20 (F) 2 637 1514.61 0.66 ulvt_ssgnp_cworstccworstt_max_0p72v_0c
SDFFRPQL2W_X2N_A9PP96CTUL_C20 (F) 2 834 2351.96 0.86 ulvt_ssgnp_cworstccworstt_max_0p72v_0c
SDFFSQL2W_X2N_A9PP96CTUL_C20 (F) 2 34 95.88 0.04 ulvt_ssgnp_cworstccworstt_max_0p72v_0c
SDFFRPQNL2W_X1N_A9PP96CTUL_C20 (F) 2 420 1114.77 0.43 ulvt_ssgnp_cworstccworstt_max_0p72v_0c
SDFFQL2W_X1N_A9PP96CTUL_C20 (F) 2 63242 143378.21 65.46 ulvt_ssgnp_cworstccworstt_max_0p72v_0c
SDFFSQNL2W_X1N_A9PP96CTUL_C20 (F) 2 12 31.85 0.01 ulvt_ssgnp_cworstccworstt_max_0p72v_0c
SDFFRPQNL2W_X2N_A9PP96CTUL_C20 (F) 2 2 5.64 0.00 ulvt_ssgnp_cworstccworstt_max_0p72v_0c
SDFFQL2W_X2N_A9PP96CTUL_C20 (F) 2 1002 2382.48 1.04 ulvt_ssgnp_cworstccworstt_max_0p72v_0c
-----------------------------------------------------------------------------------------------------------------------------
Total 88878 205039.89 91.99

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MBIT merging reporting (Cont.)

• To get info on why some are not being merged use :

report_multibit_inferencing -not_merged_summary
Info : Reasons for not merging to multibit could get overwritten in multiple iterations of incremental optimization
: and the same captured below are specific to the last iteration.
: Recommendation is to run this command after each call of incremental optimization.

Sequential Multibit not merged statistics

=======================================================================================================================
Total Sequential instances not merged: 29147

Reason of not merging Sequential Instances Description

-----------------------------------------------------------------------------------------------------------------------
dont_merge 2904 Attribute dont_merge_multibit is set
first_flop_sr 2457 Instance is first flop of shift register
single_inst_in_bus 14632 Instance is skipped because bus had a single instance. Reset
multibit_cells_from_different_busses to true to allow merging across busses
single_inst_in_physical_cluster 5146 Physical cluster is of size one
single_seq 87 Only one single bit instance is present in module
single_seq_in_compatible_group 3921 Instance cannot be combined with other instances to form multibit as it
doesn't share common signal
------------------------------------------------------------------------------------------------------------------------

• Add -combinational to the above command to get the

reason for combo cells not merged to MBIT
Notes:
- Other options exist for this command. Refer to the Genus command reference manual
- There might be multiple reasons for a single bit instance to not get merged but tool reports
only one reason and bins the above summary based on that one only.

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 Other Good Attributes / Options

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Other good (root) attributes

• force_merge_seqs_into_multibit_cells
– this one will force the tool to evaluate all the DFF for merging.
– Some DFF may still be left not merged if the tool could not find proper
MB replacement for them.
– Note, similar attributes exist for combo and iso-ls cells
force_merge_combos_into_multibit_cells
force_merge_isos_into_multibit_cells

• multibit_mapping_effort_level
– This one is at auto by default. Possible values are auto|high|low
– For more merging, set it to high.
– This will increase the threshold above which merge will not occur due to
timing degradation (resulting in more merging)

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Other good (root) attributes (Cont.)

• multibit_cells_from_different_busses
– by default cells from different busses can be merged into a MB cell.
– If you do not want this, set this attribute to false
– there are two known limitations.
– Refer to the « things to be aware of » slide

• multibit_debug
– will enable some debug info

• mbci_complex_cell_support
– If you have complex DFF like a DFF including a MUX at the i/p, to
enable the merging to MB of such cells you have to set this attribute
to true

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Merging shift registers to MBIT

• Shift registers are by default marked preserved for DFT

purposes, and DFF part of them will not be merged to MBIT
Note: shift registers are identified during syn_map, before merging to MB cells, provided
‘dft_auto_identify_shift_registers’ is set to ‘true’

• To merge shift registers elements to MB, set this attribute

before syn_map.
set_db dft_shift_register_with_mbci true

• In addition, the following attributes should already have

been set
set_db use_multibit_cells true
set_db dft_auto_identify_shift_register true

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Merging shift_registers and scan_chains to MBIT

Shift registers + Scan chain register merging is supported.

• if user calls merge_to_multibit_cell -single_thread, scan chains,

shift register and normal registers all get merged into multibit.

• if user calls merge_to_multibit_cell (parallel mbci get called), only

shift registers and normal registers get merged.

– user needs to specify -include_scan_mapping option to include scan chain

merging in distributed.

Note: MBIT replacement can only be done for scan chains if they were
created by Genus and not by a 3rd party DFT tools

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 Clock Gating Considerations

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Clock Gating Considerations

• In the current flow, clock gating elements are inserted during

syn_generic

• Later, in syn_map, these are revisited to decide which CG

should be removed because not satisfying the min_flop
fanout number.
– Currently, the flop count is a libcell count. A single DFF will count 1,
like a 8bit DFF MBIT cell

 MBIT merging is done after CG are revisited, so we may

end-up with some CG not having a FO load equal or above
the min_flop spec, but overall the min number of actual DFF
requirement should be satisfied.

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Clock Gating considerations (Cont.)

• MBIT will only occur for flops connected to the same Clock
Gater
– avoid an odd number of DFF attached to a given CG cell
– If you set min_flop to 3 for example, then 2 DFF may be mapped to
1x2bMB-DFF, and one DFF will remain orphan
– may need to adjust the min flop for CG insertion to 2,4 or even 8, depending on the
kind of MB cells you have available.
• Do not give too low number of max flops per CG
– the more CG for a given amount of DFF, the more probability for
orphan DFFs to be left aside.

Note: in 19.10 there is a way to allow 2 CG to be merged into one if there

is an opportunity for more DFF merge.
This is driven by a hidden attribute and is OFF (false) by default
set_db declone_cg_in_mbci true

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 Things to be aware of

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Things to be aware of
scan_chains

• Some of the limitations of scan chain merge to MBIT are

– compressed scan chains are not supported.
– multi-modes scan chains are not supported.
=> This should be OK if the scan DFF are mapped to MBIT prior to
stitching the scan chains so this should not be blocking if we run
syn_map + connect_scan_chain (normal flow).
However these MBIT cells will not be revisited during syn_opt
Note: There is a hidden attribute option to split MB part of scan chains
set_db split_scan_chain_multibit_flop true
(however if scan is inserted by 3rd party tool, this may cause trouble)

– Parallel multibit scan libcell are not used for scan chain multibit
merging.
=> an enhancement is ongoing to make them supported

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Things to be aware of
multibit_cells_from_different_busses

• Currently, a bus is of any size. So registers F1_reg and

F2_reg are considered being in two different busses.
– so if you set this attribute to false, single bit DFF will not be merged !

• There is only one attribute, applying to Seq/Combo/Iso-ls

cells
– If you need to have different behaviors for different types of cells then
you have to script the MB merge, separating each type

– Example :
set_db multibit_cells_from_different_busses true
merge_to_multibit_cells -sequential
set_db multibit_cells_from_different_busses false
merge_to_multibit_cells -iso_ls

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Things to be aware of
report_multibit_inferencing (up to 19.10)

• ISO cells are considered Combo. Statistics about ISO cells

coverage are part of combo numbers, so you cannot get the
ISO coverage by itself using the report command
Combinational Multibit cells usage statistics
===============================================================================================
Total Combinational instances merged: 1678
Total Combinational instances not merged: 1508530

Comb_Mbit libcell Bitwidth Count Total Area Multibit Conversion % Library

-----------------------------------------------------------------------------------------------
LVLUW4_X1N_A9PP96CTUL_C18 4 419 2270.56 0.11 cworst_max
LVLUW2_X1N_A9PP96CTUL_C18 2 1 4.31 0.00 cworst_max
-----------------------------------------------------------------------------------------------
Total 420 2274.88 0.11

– The above coverage reports 0.11% whereas the actual ISO coverage
is 47% here !!!

Note: CCR 1630415 on this is fixed in 19.10.

In that version add the switch -iso_ls to get the coverage for these cells

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Things to be aware of
MBIT split

• MBIT split only occurs on DFF.

– No split of combo / iso-ls can be done in Genus currently.

• Innovus, at this time, does not consider combo cells merge

either. However, it can split them through some other tricks
i.e. structuring, of POD if they exists on critical paths.

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Things to be aware of
multiple iterations improve coverage

• R&D has worked on this subject, and normally you should

get pretty good coverage straight out of syn_map

• However, we still see in 18.1x that looping merging may

improve the coverage

• To do so run merge_to_multibit_cells
– This runs usually fast so if you are willing to get the best coverage,
might be good to add some iterations in your scripts.

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Things to be aware of
2+2 != 4 and 4 != 2+1+1

• Once DFFs have been merged to MBIT libcells, the tool will
not reconsider them for further merging
– So, for example, if you read a netlist with 2bit MBIT and open up 4bit
DFF, the 2bit ones will not take place into 4b cells
(CCR 1636239 : GN-ap42: Allow 2bit to be re-considered to enter 4bit if 4bit cells added )

• Genus is also able to split a cell, if this helps QoR

– However, a Nbit cell will be split in Nx 1b cells
– For example there is no support for this transform today :
4b => 2b + 1b + 1b
(CCR 1636242 : GN-ap43: Allow 4bit cells to be split in 2+1+1 if only one cell is critical.)
=> the fix is planned for 19.x . It’s available in 19.10 using a hidden attribute merge_non_critical_flops_after_split, but may not be 100%
qualified

Note: INVS supports the above (may need some specific vars though) so these
transforms may be done in INVS if this helps.

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 Conformal LEC Impact

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Conformal Logic Equivalence Checking Impact

• If you rely on write_do_lec, you should be all set as the tool

will handle the name mapping done during synthesis, by
generating the required files and reading this information
during the Logic Equivalence Checking run.

• If you have your own scripts (not recommended if you want

a smooth verification flow) you may need to create a
mapping file using the write_name_mapping command in
Genus, and read it in Conformal LEC so that the RTL to
gate MBIT name mapping is successful.

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Conformal Logic Equivalence Checking Impact

• If you have changed the way the names are built, or have
fancy configuration with mixed styles you may use SET
MULTIBIT OPTION in LEC

– for example, lets say you have some MBIT named

CDN_MBIT_…_MB_... and others MBIT_...MB_...

– use this to tell LEC

set_multibit_option -delimiter "_MB_" -prefix “(?:(?:MBIT_)|(?:CDN_MBIT_))”

• So this can handle pretty much all flavors 

=> but bear in mind: write_do_lec is your best friend !

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