International Journal of Computer Science and Application Issue 2010 ISSN 0974-0767

Design of SDRAM Memor y Controller using

VHDL
Abhishek Kumar, Yogesh. E. Wankhede, Kirti Shinde P., Nisha Sarwade

Abstract- Today's high-per for mance CPUs demand high- 5) Programmable wrap sequence: sequential or interleave
speed memor y. Conventional DRAM technology cannot 6) Multiple burst read with single write option
suppor t the data r ates that today's CPUs require. As the bus 7) Automatic and controlled precharge command
speed gets faster than 50 MHz, new memor y devices are 8) Data mask for read-write control
required. Synchronous DRAM (SDRAM) is the new memor y
for high-speed CPUs. DDR SDRAM is similar in function to
9) Auto refresh or self-refresh
the regular SDRAM but doubles the bandwidth of the
memor y by tr ansfer r ing data on both edges of the clock cycles Conventional DRAM is controlled asynchronously. The
SDRAM is the most prefer able memor y for stor ing lar ge system must insert wait states (latency cycles to allow the
amount of data stor age. SDRAM stands for synchronous DRAM to catch up with the CPU) to meet the
DRAM in this case all the I/O and control signal of memor y is specifications of the conventional DRAMs. Timing
synchronize to clock. In this paper we design a kind of depends on the speed of DRAM device used, and is
SDR AM con t r oller. SDAR M con t r oller p r ovid es a independent of the bus speed. With SDRAM, the
synchronous command inter face to the SDRAM memor y performance can be increased by up to 2.7 times that of the
along with sever al control signals.
fast page mode device (conventional, asynchronous
Keywords- SDARM; Memor y r ead-wr ite;memor y DRAM).
control action
SDRAM provides for programmable READ or WRITE
burst lengths of 2, 4, or 8 locations. An auto precharge
I. INTRODUCTION function may be enabled to provide a self timed row
With the development of semiconductor industry the speed precharge that is initiated at the end of the burst access this
and capacity of memory device enlarges increasingly from model has implemented in RTL by VHDL. The focus of
RAM to DRAM and SDRAM. DDR SDARM is an this work is to implement behavioral model of SDRAM.
enhancement in traditionally synchronous DRAM. It The Top level model is as shown in Fig.1. The core contains
supports data transfer on both edge of each clock cycle, mainly two parts, AHB Slave and DDR SDRAM
effectively doubling the data transfer throughput of the controller.
memory device. It is widely used on PC for its low cost. Of
all DRAMs manufactured today, approximately 70% are II. ARCHITECTURE OF SDRAM CONTROLLER
used in desktop and notebook PCs, where they are used to Fig.1 shows the block diagram of memory controller it
provide two different functions: main storage and buffers. consist of three component command module, signal
The operating frequency of CPU is much higher than generation module and data path module.
memory thus there is a gap exit between CPU and memory.
Most PCs are offered with L2 cache to bridge the
processor-memory performance gap [2]. This makes the
speed of the DRAM memory used for main storage an
important but secondary consideration to price. However
as multitasking increases with large programs, the
frequency of accesses to the L2 cache decreases, this
degrades overall system performance, since the processor
must wait for the DRAM to supply the requested data. To
recover lost system performance, larger L2 cache or faster
DRAM main memory are required. Therefore SDRAM is
the right main memory choice to increase the system Fig.1 Top Module
performance.
The features of the SDRAM are [1, 2] Command module consists of sub module initialization
1) Fully synchronous and command generation. Initialization module initializes
2) Dual banks the memory before use it. Initialization start with high on
3) Programmable CAS latency: 1, 2, 3 clock cycles input INIT_START. It also provides the control
4) Programmable burst length: 1, 2, 4, 8
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information for command and signal generator module. accessed (BA0-BA2 select the bank; A26-A13 select the
Command module accepts the command like read, write, row). The address bits registered coincident with the Read
active, refresh and precharge from user and generate or Write command are used to select the starting column
internal signal CSTATE. All the output of initialization and location for the burst access and to determine if the auto
command module are internally coded in the form of precharge command is to be issued.
ISTATE and CSTATE respectively. Depending on the
value of ISTATE and CSTATE signal generator generates Fig.2 shows the block diagram of SDRAM controller.
the value at the output. Signal WR_EN to enable write Input contains the necessary signal for bus system and
and read operation in data path module, to activate the data output side contains the signal for addressing the memory.
transfer between CPU and memory at data transfer states At the input a multiplexed 27 bit addresses bus. RD_WR
[1]. indicates type of access read or write, for read it would be
'1'. A three bit command input indicates the input command
A memory controller regulates the data transfer between defined by user. 'Burst' input indicates whether the input is
CPU and memory. All the command and address are the single data transfer or burst data transfer. With 14 rows bit
input of controller and it generates the necessary control address and 2 bit bank address we can address 512 MB
signal for addressing the memory. SDRAM is organized in SDRAM. An active command moves row from the
bank, row and column architecture. Bank row and column memory array into row buffer, thereby opening the row.
address are multiplexed into a single address bus Once the row has been opened any number of Read- Write
“ADDRESS”. The entire control signals are synchronized command issued to transfer data on into and out of the row.
with clock. A precharge command closes a row, restores it back to the
memory array and precharges the bank for next row
III. BASIC FUNCTIONALITY [3] activation.
The SDRAM is a high-speed CMOS, dynamic random-
access memory. It is internally configured as a dual bank 1) Register Definition
DRAM. The DDR SDRAM uses double data rate Fig.3 shows scheme of address bus multiplexing. A 27 bit
architecture to achieve high-speed operation. The double multiplexed address bus consists of address of bank row
data rate architecture is essentially 2n prefetch architecture and column.
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for
the DDR SDRAM effectively consists of a single 2n-bit
wide, one clock- cycle data transfer at the internal DRAM
core and two corresponding n-bit wide, one-half clock-
cycle data transfers at the I/O pins. A bidirectional data Figure.3 Address bus multiplexing
strobe (DQS) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe
transmitted by the DDR SDRAM during READs and by SDARM is organized as a set of rank that consists of
the memory controller during WRITEs. DQS is edge- independent memory bank. 2 bit bank can address
aligned with data for READ and center-aligned with data maximum 4 no. of bank. Each memory bank consists of
for WRITE. independent 2D memory cell.

2) BankAddress Bit Configuration:

Bank address bit BA0 and BA1 used to select the MR
and EMR register. Both bits BA0 and BA1 must be
decoded for Mode/Extended Mode Register Set
(MRS/EMRS) Commands. Users must initialize Mode
Registers.

Table1: Mode Selection of SDRAM[5]

BA1 BA0 Mode Register
0 0 MR
Figure 2. Block Diagram of SDRAM controller
0 1 EMR
+Accesses begin with the registration of an Active
Command, which is then followed by a Read or Write 1 0 EMR2
command. The address bits registered coincident with the
1 1 EMR3
Active command are used to select the bank and row to be

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3) Mode Register and Extended Mode register (EMRS), such as for the burst
The mode register stores the data for controlling the length, CAS latency, and additive latency, are configurable
various operating modes of SDRAM. It controls CAS in the design and determined by the value of top-level HDL
latency, burst length, burst sequence, test mode, DLL reset, parameters. During the initialization the mode register and
WR and various vendor specific options to make SDRAM extended mode register are initialized with user defined
useful for various applications. The Mode register is used value of burst length, CL latency, AL latency and other
to define the specific mode of operation of the DDR2 parameter.
SDRAM. Fig.4 shows the Mode register features used by
the controller. Bank Addresses BA1 and BA0 select the Initialization process provides the necessary signal
Mode registers[5]. (ISTATE) to the signal generator. Initialization starts with
IDLE followed by NOP and precharge all signal. EMRS
are initialized with specific bank address value.

Figure 4. Programming of mode registers [5]

4) Extended Mode Register

In addition to the functions controlled by the Mode
register, the Extended Mode register controls these
functions: DLL enable/disable; output drive strength
(ODS); on-die termination; posted CAS additive latency
(AL); off-chip driver impedance calibration (OCD);
differential DQS enable/disable; RDQS enable/disable;
OCD enable/disable and output disable/enable as shoen
in fig5.

Figure 6. Initialization sequence of SDARM [4]

Figure 5. Programming of extended mode registers [2,5]

5) Extended Mode Register 2 (EMR2) Mode register is initialized with value “0342” to reset DLL
Bank Address bits are set to 10 (BA1 is set High, and BA0 and programmed the other value like CAS latency.
is set Low). The address bits are all set to Low. Onwards all bank precharged and generates two refresh
signal. Again it loads mode register with value “0242” to
6) Extended Mode Register 3 (EMR3) reset DLL. EMR is loaded with value “2380” for default
Bank Address bits are set to 11 (BA1 and BA0 are set calibration and “2000” to ocd exit. Once the MR and EMR
High).Address bits are all set to Low, as in EMR2. are initializing with certain value it will remain same till
Extended mode register 2 and 3 are kept reserved by end. To change the values have to re-initialize again[1].
JEDEC (Joint Electron Device Engineering Council)[5]. After initialization completed it generates INIT_DONE
signal to the command module, it shows that memory is
IV. DIFFERENT MODULE initialized and it is ready for reading or writing.
A. Initialization Module Fig.7 shows the simulated result of initialization. All the
Prior to normal operation, the SDRAM must be initialized. simulation has been performed using Xilinx simulation
SDRAMs must be powered up and initialized in a tool. Initialization sequence (ISTATE) follows as 0-1-2-3-
predefined manner. The PHY layer of SDRAM executes a 4-5-6-7-8-9-A-B-C-D which is the coded value of Idle,
JEDEC-compliant initialization sequence for memory. Nop,PrecharfeAll,EMR2,EMR3,EMR,MR,PrechargeAll,
Fig6. Shows the memory initialization sequence executed Refresh1,Refresh2,Reset DLL,OCD Default, OCD Exit,
for the physical layer during initialization of memory Ready. After Ready state signal INIT_DONE indicate
certain bit values programmed to the Mode register (MR) initialization complete.

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The Finite State Machine of command generation module

is shown in fig8[3,4]

1) Initialization: The memory device intilized. In this state

the SDRAM will be precharged, refreshed and all row are
in the closed status after the intilization. The next state is
IDLE state.

2) Idle: In this state the system will wait until a memory

access is initiated. On registration of ACTIVE command
bank and row address is sent to the signal generation
module. Control module must wait on this state to opening
the row. Next state is active state.

Figure.7 Waveform of initialization cycle

3) Active: In this state the system will come in active mode
and it issued bank address and row address only NOP
B. Command Module command is allowed in this state. The next state will be
In order to improve the whole system's performance, a active wait.
SDRAM controller has been designed to make sure the
SDRAM normally and efficiently working. Command
module accepts the command from user and generates the 4) Active Wait: in this state RAS (row activation strobe)
internally coded signal CSTATE and WR_EN. Command command will be sent to the SDRAM. Next state will be
module is based on the finite machine based operation; all first read or first write depending on the value RD_WR.
the states are synchronizes with a single clock. CSTATE
indicates the different state. WR_EN signal is used to 5) First Read: In this state the CAS (column activation
enable read and write control circuitry. WR_EN is high for strobe) command will be sent to the SDRAM. WR_EN
writing in memory low for during reading from memory, signal o high .Read_wait is the next state.
data transfer takes place in either direction depending on
the RD_WR signal. If RD_WR is high read occurs and 6) Raed Wait: In this state the SDRAM Mode Register will
data read from memory to processor, while RD_WR ids be set to a burst length of 4 or 8 depending on the burst
low write occurs and data write from processor to input. If burst is '1' next state will be burst read else Idle.
memory. SDRAM can transfer data in burst. If burst Input
at the command is low means a burst of 4 otherwise 8. In
this design a burst of 8 is tested. During burst transfer no 7) First Write: In this state the CAS command will be sent
other command are accepted except NOP. During burst to the SDRAM. WR_EN signal, write_wait is the next
state.
transfer WR_EN & RD_EN signal will became high and it
enable the write and read data path respectively. After
completion of data transfer a precharge signal is issued to 8) Write Wait: In this state the SDRAM Mode Register will
close the bank [2, 4]. be set to a burst length of 4 or 8 depending on the burst
input. If burst is '1' next state will be burst write else Idle.

9) Burst Read/burst Write: In this state burst data transfer

takes place. WR_EN became high to enable the read –write
path. A precharge command is issued to close the bank.
Next state always is idle.

C. Signal Generator
This module accept the command from initialization
(Istate) and command module (Cstate) and activate the
DDR_CAS, DDR_RAS, DDR_WE signal at the output
upon the detection of initialization and command state.
fig.9 shows the generated signal. DDR_CKE signal
always remain high to enable the data transfer between
controller and memory. DDR_CS always remain low to
enable the memory device.

Figure 8. State machine of command module

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Fig.11 shows the simulation result of write cycle.

Controller is initialized at first. Then it sends command 2
which is Burst Write timing and at this time, data given to
the input port DATAIN is “12345678”. Controller writes
data at the port DDR_DQ is “1234” at the rising edge of
clock and “5678” at the falling edge of clock at the address
of bank '1' and row address “005B”. On writing each byte
signal ddr_dqs will increase by one. The simulation result
demonstrates the correctness of the design.

Figure 9 Signal generation Fig 12 shows the RTL schematic of top module. All the
D. DATAPATH design is simulated and tested in vertex5 Xilinx ISE
The data flow design between the SDRAM and the system simulator.
HDL Synthesis report of the core as shown below
interface. Fig10 shows the diagram of controller's Macro Statistics
datapath. The module in this reference design interfaces # FSMs :2
between the SDRAM with 16-bit bidirectional data bus # Registers : 44
and the bus master with 32 bit data bus. The data path Flip-Flops : 44
module performs the data latching and dispatching of the # Latches : 14
1-bit latch :1
data between the processor and SDRAM. This module 16-bit latch :7
accepts a data of 32 bit and convert into two 16 bit DDR 2-bit latch :1
data and issue the data at both rising and falling edge of 32-bit latch :1
clock. 8-bit latch :4
Minimum period : 2.653ns
(Maximum Frequency : 376.932MHz)
Minimum input arrival time before clock: 3.333ns
Maximum output required time after clock: 3.597ns

Figure 10 data path

DATAPATH functions with enable signal WR_EN. During

writing a 32 bit data SDR data is converted into 16 bit DDR
Figure12. RTL Schematic of Top module
data, while reading 16 bit DDR data is converted into 32 bit
SDR data. Read is always burst oriented, DQS signal will
increases on each byte of read or write access. On rising --------------------------------------
and falling edge of clock we can access byte of data which Selected Device: 5vlx30ff324-3
doubles the bandwidth and system performance. --------------------------------------
Slice Logic Utilization:
Number of Slice Registers :186 out of 19200 0%
Number of Slice LUTs :174 out of 19200 0%
Number used as Logic :174 out of 19200 0%

Slice Logic Distribution:

Number of Bit Slices used :208
Number with an unused Flip Flop: 22 out of 208 10%
Number with an unused LUT :34 out of 208 16%
Number of fully used Bit Slices :152 out of 208 73%

IO Utilization:
Number of IOs :161
Figure 11 waveform of write cycle

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Number of bonded IOBs :159 out of 220 72%

IOB Flip Flops/Latches :34

Specific Feature Utilization:

Number of BUFG/BUFGCTRLs : 3 out of 32 9% Dr. Nisha Sar wade
Professor
V. CONCLUSION V.J.T.I.(Mumbai)
In this paper a fully functional SDRAM controller is [email protected]
designed, with structure proven to be efficient. The
presented controller has two main control schemes.
Command generation and signal generation,
simultaneously these modules provide signal to the data
path for data transfer. Control module and data module can
be utilized free of charge. Memory system operates at
double the frequency of processor, without affecting the
performance we can reduce the data bus size. The
disadvantages of this controller at half the frequency using
a more complicated scheme and large number of buffer
leads to a noticeable increase in delay. This paper describes
the possible implementations of an SDRAM controller
using a XILINX Vertex 5 FPFAdevice.

REFERENCES
1. High-Performance DDR2 SDRAM Interface in Virtex-5 Devices
XAPP858 (v2.1) May 8, 2008
2. LatticeSC/M DDR/DDR2 SDRAM Memory interface User's
Guide,TechnicalNoteTN1099, July 2008
3. Implementing a Synchronous DRAM Controller in Cypress
CPLDs, Cypress Semiconductor Corporation CA95134 408-943-
2600 July 15, 1999
4. VHDL for Programmable Logic, Kevin S kahill, Cypress
Semiconductor
5. JEDEC Solid State Technology Association. DDR2 SDRAM
Specification.
6. Double Data Rate (DDR) SDRAM Specification, JEDEC
STANDARD JESD79E, May 2005

Abhishek kumar
M.Tech. (Student)
V.J.T.I. (Mumbai)
[email protected]

Kir ti Shinde P
M.Tech. (Student)
V.J.T.I.(Mumbai)
[email protected]

Yogesh E. Wankhede
M.Tech. (Student)
V.J.T.I. (Mumbai)
[email protected]

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